Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110844856

1

T1

1131

T2

21345

T3

2986

auto[1]

1496145

1

T2

2475

T3

396

T4

693

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110868198

1

T1

1131

T2

21246

T3

3085

auto[1]

1472803

1

T2

2574

T3

297

T4

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7857665	1			T1	107		T2	8569		T3	719
auto[IdleSt]	25642249	1			T1	16		T2	933		T3	1096
auto[ClkMuxSt]	37805	1			T1	1		T3	7		T4	10
auto[CntIncrSt]	37482	1			T1	1		T3	7		T4	10
auto[CntProgSt]	2037556	1			T1	100		T3	195		T4	85
auto[TransCheckSt]	29271	1			T1	1		T10	1		T11	1
auto[TokenHashSt]	42682076	1			T1	35		T10	58		T11	12
auto[FlashRmaSt]	29574	1			T12	50		T13	92		T14	48
auto[TokenCheck0St]	13414	1			T12	17		T13	39		T14	8
auto[TokenCheck1St]	10035	1			T12	17		T13	27		T14	8
auto[TransProgSt]	593954	1			T12	34		T13	715		T14	4290
auto[PostTransSt]	14431458	1			T1	870		T3	416		T4	598
auto[ScrapSt]	202481	1			T12	25		T31	3		T28	16
auto[EscalateSt]	7044679	1			T2	6980		T3	942		T4	1243
auto[InvalidSt]	11689118	1			T2	7330		T13	3974		T14	408

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2184	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11689118	1			T2	7330		T13	3974		T14	408
EscalateSt	7044679	1			T2	6980		T3	942		T4	1243
ScrapSt	202481	1			T12	25		T31	3		T28	16
PostTransSt	14431458	1			T1	870		T3	416		T4	598
TransProgSt	593954	1			T12	34		T13	715		T14	4290
TokenCheck1St	10035	1			T12	17		T13	27		T14	8
TokenCheck0St	13414	1			T12	17		T13	39		T14	8
FlashRmaSt	29574	1			T12	50		T13	92		T14	48
TokenHashSt	42682076	1			T1	35		T10	58		T11	12
TransCheckSt	29271	1			T1	1		T10	1		T11	1
CntProgSt	2037556	1			T1	100		T3	195		T4	85
CntIncrSt	37482	1			T1	1		T3	7		T4	10
ClkMuxSt	37805	1			T1	1		T3	7		T4	10
IdleSt	25642249	1			T1	16		T2	933		T3	1096
ResetSt	7857665	1			T1	107		T2	8569		T3	719
arcs[ResetSt=>IdleSt]	58327	1			T1	1		T2	72		T3	8
arcs[IdleSt=>ScrapSt]	341	1			T12	1		T31	1		T28	1
arcs[IdleSt=>ClkMuxSt]	37542	1			T1	1		T3	7		T4	10
arcs[ClkMuxSt=>CntIncrSt]	37482	1			T1	1		T3	7		T4	10
arcs[CntIncrSt=>PostTransSt]	1833	1			T16	4		T17	5		T18	4
arcs[CntIncrSt=>CntProgSt]	35580	1			T1	1		T3	7		T4	10
arcs[CntProgSt=>PostTransSt]	5263	1			T3	7		T4	10		T13	18
arcs[CntProgSt=>TransCheckSt]	29271	1			T1	1		T10	1		T11	1
arcs[TransCheckSt=>PostTransSt]	3857	1			T23	33		T16	11		T17	14
arcs[TransCheckSt=>TokenHashSt]	25285	1			T1	1		T10	1		T11	1
arcs[TokenHashSt=>PostTransSt]	11001	1			T1	1		T10	1		T11	1
arcs[TokenHashSt=>FlashRmaSt]	13525	1			T12	17		T13	39		T14	8
arcs[FlashRmaSt=>TokenCheck0St]	13414	1			T12	17		T13	39		T14	8
arcs[TokenCheck0St=>PostTransSt]	3357	1			T13	12		T23	14		T25	15
arcs[TokenCheck0St=>TokenCheck1St]	10035	1			T12	17		T13	27		T14	8
arcs[TokenCheck1St=>PostTransSt]	691	1			T13	1		T23	7		T25	1
arcs[TransProgSt=>PostTransSt]	8497	1			T12	17		T13	26		T14	8
arcs[IdleSt=>EscalateSt]	231	1			T20	4		T58	12		T59	5
arcs[ClkMuxSt=>EscalateSt]	60	1			T31	1		T57	2		T58	2
arcs[CntIncrSt=>EscalateSt]	69	1			T31	1		T20	1		T59	1
arcs[CntProgSt=>EscalateSt]	1046	1			T31	53		T20	8		T57	28
arcs[TransCheckSt=>EscalateSt]	129	1			T20	2		T57	3		T65	7
arcs[TokenHashSt=>EscalateSt]	759	1			T31	4		T20	16		T57	24
arcs[FlashRmaSt=>EscalateSt]	111	1			T31	1		T57	3		T58	3
arcs[TokenCheck0St=>EscalateSt]	22	1			T58	2		T63	1		T64	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T31	4		T20	5		T57	6
arcs[TransProgSt=>EscalateSt]	708	1			T31	26		T20	8		T57	24
arcs[PostTransSt=>EscalateSt]	5523	1			T3	7		T4	10		T13	18
arcs[InvalidSt=>EscalateSt]	15132	1			T2	51		T13	21		T14	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7857476	1			T1	107		T2	8569		T3	719
auto[0]	auto[IdleSt]	25642099	1			T1	16		T2	933		T3	1096
auto[0]	auto[ClkMuxSt]	37764	1			T1	1		T3	7		T4	10
auto[0]	auto[CntIncrSt]	37449	1			T1	1		T3	7		T4	10
auto[0]	auto[CntProgSt]	2036870	1			T1	100		T3	195		T4	85
auto[0]	auto[TransCheckSt]	29183	1			T1	1		T10	1		T11	1
auto[0]	auto[TokenHashSt]	42681589	1			T1	35		T10	58		T11	12
auto[0]	auto[FlashRmaSt]	29493	1			T12	50		T13	92		T14	48
auto[0]	auto[TokenCheck0St]	13397	1			T12	17		T13	39		T14	8
auto[0]	auto[TokenCheck1St]	9947	1			T12	17		T13	27		T14	8
auto[0]	auto[TransProgSt]	593466	1			T12	34		T13	715		T14	4290
auto[0]	auto[PostTransSt]	14428584	1			T1	870		T3	412		T4	591
auto[0]	auto[ScrapSt]	202441	1			T12	25		T31	2		T28	16
auto[0]	auto[EscalateSt]	5561387	1			T2	4530		T3	550		T4	557
auto[0]	auto[InvalidSt]	11681527	1			T2	7305		T13	3962		T14	407
auto[1]	auto[ResetSt]	189	1			T31	5		T20	3		T57	2
auto[1]	auto[IdleSt]	150	1			T20	2		T58	7		T59	4
auto[1]	auto[ClkMuxSt]	41	1			T31	1		T57	1		T58	1
auto[1]	auto[CntIncrSt]	33	1			T20	1		T59	1		T65	1
auto[1]	auto[CntProgSt]	686	1			T31	31		T20	7		T57	14
auto[1]	auto[TransCheckSt]	88	1			T20	2		T57	3		T65	2
auto[1]	auto[TokenHashSt]	487	1			T31	4		T20	7		T57	17
auto[1]	auto[FlashRmaSt]	81	1			T57	2		T58	2		T238	3
auto[1]	auto[TokenCheck0St]	17	1			T58	2		T63	1		T197	2
auto[1]	auto[TokenCheck1St]	88	1			T31	3		T20	4		T57	5
auto[1]	auto[TransProgSt]	488	1			T31	17		T20	6		T57	17
auto[1]	auto[PostTransSt]	2874	1			T3	4		T4	7		T13	10
auto[1]	auto[ScrapSt]	40	1			T31	1		T20	2		T57	1
auto[1]	auto[EscalateSt]	1483292	1			T2	2450		T3	392		T4	686
auto[1]	auto[InvalidSt]	7591	1			T2	25		T13	12		T14	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7857492	1			T1	107		T2	8569		T3	719
auto[0]	auto[IdleSt]	25642098	1			T1	16		T2	933		T3	1096
auto[0]	auto[ClkMuxSt]	37770	1			T1	1		T3	7		T4	10
auto[0]	auto[CntIncrSt]	37424	1			T1	1		T3	7		T4	10
auto[0]	auto[CntProgSt]	2036846	1			T1	100		T3	195		T4	85
auto[0]	auto[TransCheckSt]	29188	1			T1	1		T10	1		T11	1
auto[0]	auto[TokenHashSt]	42681575	1			T1	35		T10	58		T11	12
auto[0]	auto[FlashRmaSt]	29504	1			T12	50		T13	92		T14	48
auto[0]	auto[TokenCheck0St]	13402	1			T12	17		T13	39		T14	8
auto[0]	auto[TokenCheck1St]	9944	1			T12	17		T13	27		T14	8
auto[0]	auto[TransProgSt]	593494	1			T12	34		T13	715		T14	4290
auto[0]	auto[PostTransSt]	14428726	1			T1	870		T3	413		T4	595
auto[0]	auto[ScrapSt]	202436	1			T12	25		T31	2		T28	16
auto[0]	auto[EscalateSt]	5584538	1			T2	4432		T3	648		T4	949
auto[0]	auto[InvalidSt]	11681577	1			T2	7304		T13	3965		T14	407
auto[1]	auto[ResetSt]	173	1			T31	4		T20	3		T57	4
auto[1]	auto[IdleSt]	151	1			T20	4		T58	7		T59	1
auto[1]	auto[ClkMuxSt]	35	1			T57	1		T58	2		T239	2
auto[1]	auto[CntIncrSt]	58	1			T31	1		T59	1		T65	1
auto[1]	auto[CntProgSt]	710	1			T31	37		T20	5		T57	20
auto[1]	auto[TransCheckSt]	83	1			T65	6		T239	4		T63	2
auto[1]	auto[TokenHashSt]	501	1			T20	14		T57	12		T58	6
auto[1]	auto[FlashRmaSt]	70	1			T31	1		T57	2		T58	1
auto[1]	auto[TokenCheck0St]	12	1			T58	1		T63	1		T64	1
auto[1]	auto[TokenCheck1St]	91	1			T31	3		T20	4		T57	3
auto[1]	auto[TransProgSt]	460	1			T31	17		T20	6		T57	13
auto[1]	auto[PostTransSt]	2732	1			T3	3		T4	3		T13	8
auto[1]	auto[ScrapSt]	45	1			T31	1		T20	1		T57	1
auto[1]	auto[EscalateSt]	1460141	1			T2	2548		T3	294		T4	294
auto[1]	auto[InvalidSt]	7541	1			T2	26		T13	9		T14	1