Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200164724

1

T1

567796

T2

1091

T3

5432

auto[1]

2762479

1

T1

3241

T4

792

T5

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200174242

1

T1

567405

T2

1091

T3

5432

auto[1]

2752961

1

T1

3632

T4

495

T5

891

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	14396766	1			T1	41689		T2	102		T3	135
auto[IdleSt]	40146070	1			T1	102362		T2	136		T3	5297
auto[ClkMuxSt]	70186	1			T1	55		T4	13		T5	79
auto[CntIncrSt]	69694	1			T1	55		T4	13		T5	79
auto[CntProgSt]	2989358	1			T1	110		T4	26		T5	4275
auto[TransCheckSt]	54809	1			T1	39		T5	53		T10	8
auto[TokenHashSt]	85516767	1			T1	117481		T5	969		T10	491
auto[FlashRmaSt]	56303	1			T1	104		T5	55		T10	35
auto[TokenCheck0St]	25307	1			T1	39		T5	20		T10	8
auto[TokenCheck1St]	18721	1			T1	39		T5	12		T10	8
auto[TransProgSt]	781817	1			T1	78		T5	909		T10	1872
auto[PostTransSt]	23691999	1			T1	72157		T2	853		T4	914
auto[ScrapSt]	313558	1			T11	950		T18	647		T48	31
auto[EscalateSt]	12959286	1			T1	71154		T4	1726		T5	1524
auto[InvalidSt]	21832669	1			T1	165671		T10	623		T12	673

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3893	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	21832669	1			T1	165671		T10	623		T12	673
EscalateSt	12959286	1			T1	71154		T4	1726		T5	1524
ScrapSt	313558	1			T11	950		T18	647		T48	31
PostTransSt	23691999	1			T1	72157		T2	853		T4	914
TransProgSt	781817	1			T1	78		T5	909		T10	1872
TokenCheck1St	18721	1			T1	39		T5	12		T10	8
TokenCheck0St	25307	1			T1	39		T5	20		T10	8
FlashRmaSt	56303	1			T1	104		T5	55		T10	35
TokenHashSt	85516767	1			T1	117481		T5	969		T10	491
TransCheckSt	54809	1			T1	39		T5	53		T10	8
CntProgSt	2989358	1			T1	110		T4	26		T5	4275
CntIncrSt	69694	1			T1	55		T4	13		T5	79
ClkMuxSt	70186	1			T1	55		T4	13		T5	79
IdleSt	40146070	1			T1	102362		T2	136		T3	5297
ResetSt	14396766	1			T1	41689		T2	102		T3	135
arcs[ResetSt=>IdleSt]	106949	1			T1	122		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	601	1			T11	1		T18	2		T48	1
arcs[IdleSt=>ClkMuxSt]	69827	1			T1	55		T4	13		T5	79
arcs[ClkMuxSt=>CntIncrSt]	69694	1			T1	55		T4	13		T5	79
arcs[CntIncrSt=>PostTransSt]	3205	1			T5	15		T41	11		T17	9
arcs[CntIncrSt=>CntProgSt]	66360	1			T1	55		T4	13		T5	64
arcs[CntProgSt=>PostTransSt]	9440	1			T1	16		T4	13		T5	11
arcs[CntProgSt=>TransCheckSt]	54809	1			T1	39		T5	53		T10	8
arcs[TransCheckSt=>PostTransSt]	7503	1			T5	9		T41	12		T17	12
arcs[TransCheckSt=>TokenHashSt]	47076	1			T1	39		T5	44		T10	8
arcs[TokenHashSt=>PostTransSt]	20221	1			T5	24		T44	70		T47	82
arcs[TokenHashSt=>FlashRmaSt]	25499	1			T1	39		T5	20		T10	8
arcs[FlashRmaSt=>TokenCheck0St]	25307	1			T1	39		T5	20		T10	8
arcs[TokenCheck0St=>PostTransSt]	6531	1			T5	8		T41	7		T17	12
arcs[TokenCheck0St=>TokenCheck1St]	18721	1			T1	39		T5	12		T10	8
arcs[TokenCheck1St=>PostTransSt]	1373	1			T5	1		T41	1		T17	2
arcs[TransProgSt=>PostTransSt]	15673	1			T1	39		T5	11		T10	8
arcs[IdleSt=>EscalateSt]	367	1			T67	7		T68	11		T69	4
arcs[ClkMuxSt=>EscalateSt]	133	1			T64	2		T65	1		T66	2
arcs[CntIncrSt=>EscalateSt]	129	1			T64	1		T65	3		T66	2
arcs[CntProgSt=>EscalateSt]	2111	1			T64	20		T67	25		T65	30
arcs[TransCheckSt=>EscalateSt]	230	1			T64	1		T74	1		T69	1
arcs[TokenHashSt=>EscalateSt]	1356	1			T64	16		T67	8		T73	2
arcs[FlashRmaSt=>EscalateSt]	192	1			T64	1		T67	2		T65	1
arcs[TokenCheck0St=>EscalateSt]	55	1			T67	1		T65	1		T68	1
arcs[TokenCheck1St=>EscalateSt]	296	1			T64	2		T67	2		T65	5
arcs[TransProgSt=>EscalateSt]	1379	1			T64	6		T67	22		T65	15
arcs[PostTransSt=>EscalateSt]	9930	1			T1	16		T4	13		T5	11
arcs[InvalidSt=>EscalateSt]	27640	1			T1	54		T10	4		T12	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14396411	1			T1	41689		T2	102		T3	135
auto[0]	auto[IdleSt]	40145812	1			T1	102362		T2	136		T3	5297
auto[0]	auto[ClkMuxSt]	70105	1			T1	55		T4	13		T5	79
auto[0]	auto[CntIncrSt]	69610	1			T1	55		T4	13		T5	79
auto[0]	auto[CntProgSt]	2987970	1			T1	110		T4	26		T5	4275
auto[0]	auto[TransCheckSt]	54654	1			T1	39		T5	53		T10	8
auto[0]	auto[TokenHashSt]	85515858	1			T1	117481		T5	969		T10	491
auto[0]	auto[FlashRmaSt]	56168	1			T1	104		T5	55		T10	35
auto[0]	auto[TokenCheck0St]	25268	1			T1	39		T5	20		T10	8
auto[0]	auto[TokenCheck1St]	18521	1			T1	39		T5	12		T10	8
auto[0]	auto[TransProgSt]	780918	1			T1	78		T5	909		T10	1872
auto[0]	auto[PostTransSt]	23686935	1			T1	72148		T2	853		T4	906
auto[0]	auto[ScrapSt]	313453	1			T11	950		T18	647		T48	31
auto[0]	auto[EscalateSt]	10220347	1			T1	67946		T4	942		T5	1328
auto[0]	auto[InvalidSt]	21818801	1			T1	165647		T10	619		T12	672
auto[1]	auto[ResetSt]	355	1			T64	3		T67	5		T66	3
auto[1]	auto[IdleSt]	258	1			T67	5		T68	7		T69	3
auto[1]	auto[ClkMuxSt]	81	1			T66	1		T74	2		T269	1
auto[1]	auto[CntIncrSt]	84	1			T65	3		T66	2		T68	3
auto[1]	auto[CntProgSt]	1388	1			T64	13		T67	14		T65	21
auto[1]	auto[TransCheckSt]	155	1			T64	1		T74	1		T69	1
auto[1]	auto[TokenHashSt]	909	1			T64	11		T67	5		T65	2
auto[1]	auto[FlashRmaSt]	135	1			T67	2		T65	1		T66	2
auto[1]	auto[TokenCheck0St]	39	1			T67	1		T65	1		T68	1
auto[1]	auto[TokenCheck1St]	200	1			T64	2		T67	2		T65	3
auto[1]	auto[TransProgSt]	899	1			T64	4		T67	17		T65	7
auto[1]	auto[PostTransSt]	5064	1			T1	9		T4	8		T5	2
auto[1]	auto[ScrapSt]	105	1			T64	1		T67	2		T65	1
auto[1]	auto[EscalateSt]	2738939	1			T1	3208		T4	784		T5	196
auto[1]	auto[InvalidSt]	13868	1			T1	24		T10	4		T12	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14396419	1			T1	41689		T2	102		T3	135
auto[0]	auto[IdleSt]	40145839	1			T1	102362		T2	136		T3	5297
auto[0]	auto[ClkMuxSt]	70094	1			T1	55		T4	13		T5	79
auto[0]	auto[CntIncrSt]	69608	1			T1	55		T4	13		T5	79
auto[0]	auto[CntProgSt]	2987931	1			T1	110		T4	26		T5	4275
auto[0]	auto[TransCheckSt]	54650	1			T1	39		T5	53		T10	8
auto[0]	auto[TokenHashSt]	85515887	1			T1	117481		T5	969		T10	491
auto[0]	auto[FlashRmaSt]	56180	1			T1	104		T5	55		T10	35
auto[0]	auto[TokenCheck0St]	25269	1			T1	39		T5	20		T10	8
auto[0]	auto[TokenCheck1St]	18520	1			T1	39		T5	12		T10	8
auto[0]	auto[TransProgSt]	780890	1			T1	78		T5	909		T10	1872
auto[0]	auto[PostTransSt]	23686978	1			T1	72150		T2	853		T4	909
auto[0]	auto[ScrapSt]	313458	1			T11	950		T18	647		T48	31
auto[0]	auto[EscalateSt]	10229729	1			T1	67559		T4	1236		T5	642
auto[0]	auto[InvalidSt]	21818897	1			T1	165641		T10	623		T12	671
auto[1]	auto[ResetSt]	347	1			T64	4		T67	5		T68	3
auto[1]	auto[IdleSt]	231	1			T67	4		T68	4		T69	3
auto[1]	auto[ClkMuxSt]	92	1			T64	2		T65	1		T66	1
auto[1]	auto[CntIncrSt]	86	1			T64	1		T65	2		T66	1
auto[1]	auto[CntProgSt]	1427	1			T64	13		T67	20		T65	21
auto[1]	auto[TransCheckSt]	159	1			T74	1		T69	1		T270	7
auto[1]	auto[TokenHashSt]	880	1			T64	11		T67	6		T73	2
auto[1]	auto[FlashRmaSt]	123	1			T64	1		T67	2		T66	2
auto[1]	auto[TokenCheck0St]	38	1			T67	1		T65	1		T74	1
auto[1]	auto[TokenCheck1St]	201	1			T64	1		T67	1		T65	2
auto[1]	auto[TransProgSt]	927	1			T64	5		T67	14		T65	13
auto[1]	auto[PostTransSt]	5021	1			T1	7		T4	5		T5	9
auto[1]	auto[ScrapSt]	100	1			T64	2		T67	1		T66	2
auto[1]	auto[EscalateSt]	2729557	1			T1	3595		T4	490		T5	882
auto[1]	auto[InvalidSt]	13772	1			T1	30		T12	2		T13	2