| T1559 |
/workspace/coverage/default/20.lc_ctrl_state_post_trans.3977530951 |
|
|
Mar 05 02:40:42 PM PST 24 |
Mar 05 02:40:49 PM PST 24 |
275013781 ps |
| T1560 |
/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1876125183 |
|
|
Mar 05 01:47:18 PM PST 24 |
Mar 05 01:47:36 PM PST 24 |
553706352 ps |
| T1561 |
/workspace/coverage/default/9.lc_ctrl_smoke.186473595 |
|
|
Mar 05 02:39:37 PM PST 24 |
Mar 05 02:39:38 PM PST 24 |
76404593 ps |
| T1562 |
/workspace/coverage/default/0.lc_ctrl_security_escalation.2738869536 |
|
|
Mar 05 01:47:01 PM PST 24 |
Mar 05 01:47:12 PM PST 24 |
317958206 ps |
| T1563 |
/workspace/coverage/default/31.lc_ctrl_prog_failure.2582287823 |
|
|
Mar 05 01:48:33 PM PST 24 |
Mar 05 01:48:34 PM PST 24 |
149103161 ps |
| T1564 |
/workspace/coverage/default/30.lc_ctrl_security_escalation.3007396757 |
|
|
Mar 05 01:48:14 PM PST 24 |
Mar 05 01:48:22 PM PST 24 |
985335814 ps |
| T1565 |
/workspace/coverage/default/5.lc_ctrl_state_failure.3123605832 |
|
|
Mar 05 02:39:10 PM PST 24 |
Mar 05 02:39:43 PM PST 24 |
1438077654 ps |
| T1566 |
/workspace/coverage/default/43.lc_ctrl_prog_failure.3201811440 |
|
|
Mar 05 02:42:10 PM PST 24 |
Mar 05 02:42:12 PM PST 24 |
75067002 ps |
| T1567 |
/workspace/coverage/default/31.lc_ctrl_sec_token_digest.124512757 |
|
|
Mar 05 02:41:26 PM PST 24 |
Mar 05 02:41:36 PM PST 24 |
387597114 ps |
| T1568 |
/workspace/coverage/default/3.lc_ctrl_sec_token_mux.1749257670 |
|
|
Mar 05 01:47:16 PM PST 24 |
Mar 05 01:47:26 PM PST 24 |
3098603015 ps |
| T1569 |
/workspace/coverage/default/30.lc_ctrl_sec_mubi.1268684341 |
|
|
Mar 05 01:48:23 PM PST 24 |
Mar 05 01:48:36 PM PST 24 |
1458413578 ps |
| T1570 |
/workspace/coverage/default/8.lc_ctrl_jtag_smoke.750780049 |
|
|
Mar 05 02:39:32 PM PST 24 |
Mar 05 02:39:38 PM PST 24 |
327215954 ps |
| T1571 |
/workspace/coverage/default/9.lc_ctrl_state_failure.3752857042 |
|
|
Mar 05 02:39:42 PM PST 24 |
Mar 05 02:40:07 PM PST 24 |
952510459 ps |
| T1572 |
/workspace/coverage/default/28.lc_ctrl_sec_token_mux.1826966965 |
|
|
Mar 05 01:48:14 PM PST 24 |
Mar 05 01:48:25 PM PST 24 |
1964530337 ps |
| T1573 |
/workspace/coverage/default/24.lc_ctrl_sec_token_digest.3060342337 |
|
|
Mar 05 01:48:12 PM PST 24 |
Mar 05 01:48:23 PM PST 24 |
572892035 ps |
| T1574 |
/workspace/coverage/default/6.lc_ctrl_sec_token_mux.2453395784 |
|
|
Mar 05 01:47:23 PM PST 24 |
Mar 05 01:47:30 PM PST 24 |
455284296 ps |
| T1575 |
/workspace/coverage/default/7.lc_ctrl_jtag_errors.3839899824 |
|
|
Mar 05 02:39:28 PM PST 24 |
Mar 05 02:40:08 PM PST 24 |
43201284125 ps |
| T1576 |
/workspace/coverage/default/41.lc_ctrl_sec_mubi.3330592582 |
|
|
Mar 05 02:42:01 PM PST 24 |
Mar 05 02:42:10 PM PST 24 |
181119892 ps |
| T1577 |
/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.42443151 |
|
|
Mar 05 01:48:45 PM PST 24 |
Mar 05 01:48:46 PM PST 24 |
15154751 ps |
| T1578 |
/workspace/coverage/default/4.lc_ctrl_smoke.524817154 |
|
|
Mar 05 01:47:19 PM PST 24 |
Mar 05 01:47:22 PM PST 24 |
50616086 ps |
| T1579 |
/workspace/coverage/default/34.lc_ctrl_state_post_trans.3129277580 |
|
|
Mar 05 01:48:38 PM PST 24 |
Mar 05 01:48:46 PM PST 24 |
133750543 ps |
| T1580 |
/workspace/coverage/default/2.lc_ctrl_claim_transition_if.3880163732 |
|
|
Mar 05 02:38:39 PM PST 24 |
Mar 05 02:38:40 PM PST 24 |
11402283 ps |
| T1581 |
/workspace/coverage/default/8.lc_ctrl_security_escalation.2344356933 |
|
|
Mar 05 02:39:34 PM PST 24 |
Mar 05 02:39:45 PM PST 24 |
1769395021 ps |
| T1582 |
/workspace/coverage/default/12.lc_ctrl_stress_all.248378865 |
|
|
Mar 05 02:40:06 PM PST 24 |
Mar 05 02:44:45 PM PST 24 |
77869300760 ps |
| T100 |
/workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3225262312 |
|
|
Mar 05 01:47:05 PM PST 24 |
Mar 05 02:06:47 PM PST 24 |
163722597685 ps |
| T1583 |
/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1938464460 |
|
|
Mar 05 01:47:36 PM PST 24 |
Mar 05 01:47:48 PM PST 24 |
1830375899 ps |
| T1584 |
/workspace/coverage/default/20.lc_ctrl_alert_test.4285756369 |
|
|
Mar 05 01:48:03 PM PST 24 |
Mar 05 01:48:04 PM PST 24 |
76570985 ps |
| T1585 |
/workspace/coverage/default/30.lc_ctrl_sec_token_mux.1927548672 |
|
|
Mar 05 02:41:24 PM PST 24 |
Mar 05 02:41:33 PM PST 24 |
641389614 ps |
| T1586 |
/workspace/coverage/default/4.lc_ctrl_sec_mubi.896782555 |
|
|
Mar 05 02:39:02 PM PST 24 |
Mar 05 02:39:17 PM PST 24 |
917398665 ps |
| T1587 |
/workspace/coverage/default/24.lc_ctrl_smoke.3872016785 |
|
|
Mar 05 01:48:04 PM PST 24 |
Mar 05 01:48:08 PM PST 24 |
134568132 ps |
| T1588 |
/workspace/coverage/default/3.lc_ctrl_state_failure.2172515028 |
|
|
Mar 05 02:38:49 PM PST 24 |
Mar 05 02:39:20 PM PST 24 |
365154291 ps |
| T1589 |
/workspace/coverage/default/10.lc_ctrl_sec_token_mux.2748030562 |
|
|
Mar 05 01:47:42 PM PST 24 |
Mar 05 01:47:50 PM PST 24 |
2929523010 ps |
| T1590 |
/workspace/coverage/default/32.lc_ctrl_state_post_trans.1416717343 |
|
|
Mar 05 01:48:24 PM PST 24 |
Mar 05 01:48:31 PM PST 24 |
197800168 ps |
| T1591 |
/workspace/coverage/default/33.lc_ctrl_security_escalation.117771487 |
|
|
Mar 05 02:41:35 PM PST 24 |
Mar 05 02:41:45 PM PST 24 |
1519475996 ps |
| T1592 |
/workspace/coverage/default/12.lc_ctrl_state_post_trans.449785371 |
|
|
Mar 05 01:47:55 PM PST 24 |
Mar 05 01:48:02 PM PST 24 |
301793996 ps |
| T1593 |
/workspace/coverage/default/16.lc_ctrl_stress_all.3350357652 |
|
|
Mar 05 02:40:32 PM PST 24 |
Mar 05 02:42:36 PM PST 24 |
25604824917 ps |
| T1594 |
/workspace/coverage/default/17.lc_ctrl_errors.3477227611 |
|
|
Mar 05 02:40:32 PM PST 24 |
Mar 05 02:40:45 PM PST 24 |
842394440 ps |
| T1595 |
/workspace/coverage/default/19.lc_ctrl_state_failure.2953839427 |
|
|
Mar 05 02:40:33 PM PST 24 |
Mar 05 02:40:56 PM PST 24 |
233294189 ps |
| T1596 |
/workspace/coverage/default/14.lc_ctrl_alert_test.4151754716 |
|
|
Mar 05 01:47:51 PM PST 24 |
Mar 05 01:47:53 PM PST 24 |
98218424 ps |
| T1597 |
/workspace/coverage/default/7.lc_ctrl_prog_failure.3290918918 |
|
|
Mar 05 01:47:21 PM PST 24 |
Mar 05 01:47:25 PM PST 24 |
57245282 ps |
| T1598 |
/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3541597702 |
|
|
Mar 05 01:49:05 PM PST 24 |
Mar 05 01:49:06 PM PST 24 |
45243453 ps |
| T1599 |
/workspace/coverage/default/32.lc_ctrl_alert_test.3396772274 |
|
|
Mar 05 01:48:23 PM PST 24 |
Mar 05 01:48:24 PM PST 24 |
20928927 ps |
| T1600 |
/workspace/coverage/default/41.lc_ctrl_security_escalation.459196599 |
|
|
Mar 05 02:42:02 PM PST 24 |
Mar 05 02:42:11 PM PST 24 |
176509642 ps |
| T1601 |
/workspace/coverage/default/43.lc_ctrl_jtag_access.2396830116 |
|
|
Mar 05 01:49:09 PM PST 24 |
Mar 05 01:49:18 PM PST 24 |
1944670826 ps |
| T1602 |
/workspace/coverage/default/8.lc_ctrl_stress_all.1069589869 |
|
|
Mar 05 01:47:33 PM PST 24 |
Mar 05 01:50:16 PM PST 24 |
4926803496 ps |
| T1603 |
/workspace/coverage/default/42.lc_ctrl_smoke.1211176722 |
|
|
Mar 05 02:41:59 PM PST 24 |
Mar 05 02:42:02 PM PST 24 |
262060631 ps |
| T1604 |
/workspace/coverage/default/35.lc_ctrl_sec_mubi.1038706308 |
|
|
Mar 05 01:48:42 PM PST 24 |
Mar 05 01:48:52 PM PST 24 |
381926348 ps |
| T1605 |
/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.980626375 |
|
|
Mar 05 02:39:46 PM PST 24 |
Mar 05 02:39:57 PM PST 24 |
369403588 ps |
| T1606 |
/workspace/coverage/default/1.lc_ctrl_alert_test.2711343363 |
|
|
Mar 05 02:38:41 PM PST 24 |
Mar 05 02:38:43 PM PST 24 |
75122039 ps |
| T1607 |
/workspace/coverage/default/17.lc_ctrl_jtag_errors.2506747690 |
|
|
Mar 05 01:48:08 PM PST 24 |
Mar 05 01:49:13 PM PST 24 |
5253891105 ps |
| T1608 |
/workspace/coverage/default/41.lc_ctrl_jtag_access.508889328 |
|
|
Mar 05 02:42:07 PM PST 24 |
Mar 05 02:42:13 PM PST 24 |
168806793 ps |
| T1609 |
/workspace/coverage/default/3.lc_ctrl_stress_all.2330934184 |
|
|
Mar 05 02:39:06 PM PST 24 |
Mar 05 02:43:47 PM PST 24 |
34336981044 ps |
| T1610 |
/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2457660103 |
|
|
Mar 05 02:39:17 PM PST 24 |
Mar 05 02:39:21 PM PST 24 |
66090306 ps |
| T1611 |
/workspace/coverage/default/37.lc_ctrl_alert_test.3395301270 |
|
|
Mar 05 02:41:54 PM PST 24 |
Mar 05 02:41:55 PM PST 24 |
27638638 ps |
| T86 |
/workspace/coverage/default/6.lc_ctrl_stress_all.646431389 |
|
|
Mar 05 01:47:25 PM PST 24 |
Mar 05 01:49:47 PM PST 24 |
3495579649 ps |
| T1612 |
/workspace/coverage/default/30.lc_ctrl_errors.3584374006 |
|
|
Mar 05 01:48:21 PM PST 24 |
Mar 05 01:48:37 PM PST 24 |
370032109 ps |
| T1613 |
/workspace/coverage/default/25.lc_ctrl_stress_all.4184173099 |
|
|
Mar 05 02:41:05 PM PST 24 |
Mar 05 02:46:01 PM PST 24 |
37537896904 ps |
| T1614 |
/workspace/coverage/default/33.lc_ctrl_security_escalation.1529951191 |
|
|
Mar 05 01:48:33 PM PST 24 |
Mar 05 01:48:42 PM PST 24 |
320226830 ps |
| T1615 |
/workspace/coverage/default/20.lc_ctrl_errors.51537869 |
|
|
Mar 05 01:48:05 PM PST 24 |
Mar 05 01:48:18 PM PST 24 |
1425769346 ps |
| T1616 |
/workspace/coverage/default/44.lc_ctrl_sec_token_digest.2522517333 |
|
|
Mar 05 01:49:06 PM PST 24 |
Mar 05 01:49:17 PM PST 24 |
1067627018 ps |
| T1617 |
/workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2277404867 |
|
|
Mar 05 02:41:14 PM PST 24 |
Mar 05 02:44:39 PM PST 24 |
9969409849 ps |
| T1618 |
/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2799988349 |
|
|
Mar 05 01:47:21 PM PST 24 |
Mar 05 01:47:22 PM PST 24 |
21049451 ps |
| T1619 |
/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2260541206 |
|
|
Mar 05 02:39:59 PM PST 24 |
Mar 05 02:40:00 PM PST 24 |
12490351 ps |
| T1620 |
/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.152840977 |
|
|
Mar 05 02:40:44 PM PST 24 |
Mar 05 02:40:45 PM PST 24 |
33791833 ps |
| T1621 |
/workspace/coverage/default/17.lc_ctrl_security_escalation.132454561 |
|
|
Mar 05 01:48:01 PM PST 24 |
Mar 05 01:48:11 PM PST 24 |
1686019934 ps |
| T1622 |
/workspace/coverage/default/9.lc_ctrl_jtag_errors.4244474371 |
|
|
Mar 05 02:39:40 PM PST 24 |
Mar 05 02:40:03 PM PST 24 |
4241473285 ps |
| T1623 |
/workspace/coverage/default/13.lc_ctrl_prog_failure.1482209321 |
|
|
Mar 05 02:40:07 PM PST 24 |
Mar 05 02:40:10 PM PST 24 |
62916731 ps |
| T1624 |
/workspace/coverage/default/22.lc_ctrl_state_post_trans.4160842750 |
|
|
Mar 05 02:40:49 PM PST 24 |
Mar 05 02:40:52 PM PST 24 |
562398235 ps |
| T1625 |
/workspace/coverage/default/6.lc_ctrl_smoke.3238849381 |
|
|
Mar 05 02:39:22 PM PST 24 |
Mar 05 02:39:27 PM PST 24 |
516734713 ps |
| T1626 |
/workspace/coverage/default/12.lc_ctrl_state_failure.4274087906 |
|
|
Mar 05 02:39:59 PM PST 24 |
Mar 05 02:40:26 PM PST 24 |
444392037 ps |
| T1627 |
/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2476706709 |
|
|
Mar 05 02:41:14 PM PST 24 |
Mar 05 02:41:15 PM PST 24 |
48274183 ps |
| T1628 |
/workspace/coverage/default/0.lc_ctrl_security_escalation.1647742451 |
|
|
Mar 05 02:38:21 PM PST 24 |
Mar 05 02:38:31 PM PST 24 |
337110934 ps |
| T1629 |
/workspace/coverage/default/8.lc_ctrl_state_failure.3646796780 |
|
|
Mar 05 02:39:33 PM PST 24 |
Mar 05 02:40:10 PM PST 24 |
1452714642 ps |
| T1630 |
/workspace/coverage/default/28.lc_ctrl_state_failure.462019278 |
|
|
Mar 05 01:48:24 PM PST 24 |
Mar 05 01:48:43 PM PST 24 |
607162057 ps |
| T1631 |
/workspace/coverage/default/24.lc_ctrl_state_post_trans.772073663 |
|
|
Mar 05 01:48:05 PM PST 24 |
Mar 05 01:48:12 PM PST 24 |
375314467 ps |
| T1632 |
/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.261655468 |
|
|
Mar 05 02:39:24 PM PST 24 |
Mar 05 02:39:52 PM PST 24 |
2787030694 ps |
| T1633 |
/workspace/coverage/default/7.lc_ctrl_jtag_priority.2806163379 |
|
|
Mar 05 01:47:51 PM PST 24 |
Mar 05 01:47:57 PM PST 24 |
1669143188 ps |
| T1634 |
/workspace/coverage/default/34.lc_ctrl_state_failure.4241435070 |
|
|
Mar 05 01:48:42 PM PST 24 |
Mar 05 01:49:05 PM PST 24 |
1046022153 ps |
| T1635 |
/workspace/coverage/default/17.lc_ctrl_jtag_access.255469196 |
|
|
Mar 05 01:48:05 PM PST 24 |
Mar 05 01:48:10 PM PST 24 |
182564389 ps |
| T1636 |
/workspace/coverage/default/21.lc_ctrl_security_escalation.3378345497 |
|
|
Mar 05 02:40:49 PM PST 24 |
Mar 05 02:41:04 PM PST 24 |
441892239 ps |
| T1637 |
/workspace/coverage/default/3.lc_ctrl_state_post_trans.2100562964 |
|
|
Mar 05 01:47:14 PM PST 24 |
Mar 05 01:47:21 PM PST 24 |
399281784 ps |
| T1638 |
/workspace/coverage/default/42.lc_ctrl_stress_all.1827702314 |
|
|
Mar 05 02:42:12 PM PST 24 |
Mar 05 02:42:52 PM PST 24 |
2816678573 ps |
| T1639 |
/workspace/coverage/default/36.lc_ctrl_sec_mubi.1633467149 |
|
|
Mar 05 01:48:31 PM PST 24 |
Mar 05 01:48:47 PM PST 24 |
343672133 ps |
| T1640 |
/workspace/coverage/default/19.lc_ctrl_alert_test.118154642 |
|
|
Mar 05 02:40:42 PM PST 24 |
Mar 05 02:40:43 PM PST 24 |
69184048 ps |
| T1641 |
/workspace/coverage/default/41.lc_ctrl_stress_all.4032918478 |
|
|
Mar 05 01:48:55 PM PST 24 |
Mar 05 01:50:39 PM PST 24 |
16319210680 ps |
| T1642 |
/workspace/coverage/default/32.lc_ctrl_alert_test.136186799 |
|
|
Mar 05 02:41:27 PM PST 24 |
Mar 05 02:41:29 PM PST 24 |
65524216 ps |
| T1643 |
/workspace/coverage/default/29.lc_ctrl_stress_all.3735406007 |
|
|
Mar 05 01:48:28 PM PST 24 |
Mar 05 01:52:09 PM PST 24 |
25799740839 ps |
| T1644 |
/workspace/coverage/default/23.lc_ctrl_prog_failure.356041987 |
|
|
Mar 05 01:48:04 PM PST 24 |
Mar 05 01:48:06 PM PST 24 |
456051886 ps |
| T1645 |
/workspace/coverage/default/8.lc_ctrl_regwen_during_op.1762377371 |
|
|
Mar 05 02:39:34 PM PST 24 |
Mar 05 02:39:46 PM PST 24 |
291260886 ps |
| T1646 |
/workspace/coverage/default/31.lc_ctrl_jtag_access.1794009137 |
|
|
Mar 05 02:41:29 PM PST 24 |
Mar 05 02:41:37 PM PST 24 |
271544326 ps |
| T1647 |
/workspace/coverage/default/42.lc_ctrl_security_escalation.3881628163 |
|
|
Mar 05 01:48:48 PM PST 24 |
Mar 05 01:48:58 PM PST 24 |
412671006 ps |
| T1648 |
/workspace/coverage/default/18.lc_ctrl_errors.3742422889 |
|
|
Mar 05 02:40:33 PM PST 24 |
Mar 05 02:40:49 PM PST 24 |
575121556 ps |
| T1649 |
/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1170069755 |
|
|
Mar 05 02:40:41 PM PST 24 |
Mar 05 02:41:36 PM PST 24 |
5121252861 ps |
| T1650 |
/workspace/coverage/default/6.lc_ctrl_sec_token_mux.2692961933 |
|
|
Mar 05 02:39:27 PM PST 24 |
Mar 05 02:39:35 PM PST 24 |
242771374 ps |
| T1651 |
/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1391327875 |
|
|
Mar 05 01:47:51 PM PST 24 |
Mar 05 01:48:01 PM PST 24 |
669982680 ps |
| T1652 |
/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3333516278 |
|
|
Mar 05 01:48:02 PM PST 24 |
Mar 05 01:48:03 PM PST 24 |
47359501 ps |
| T1653 |
/workspace/coverage/default/44.lc_ctrl_state_failure.3650721000 |
|
|
Mar 05 01:48:55 PM PST 24 |
Mar 05 01:49:24 PM PST 24 |
301050545 ps |
| T1654 |
/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.524242516 |
|
|
Mar 05 02:42:31 PM PST 24 |
Mar 05 02:42:32 PM PST 24 |
23408767 ps |
| T1655 |
/workspace/coverage/default/19.lc_ctrl_jtag_errors.3356319793 |
|
|
Mar 05 02:40:43 PM PST 24 |
Mar 05 02:41:26 PM PST 24 |
1500897517 ps |
| T1656 |
/workspace/coverage/default/21.lc_ctrl_security_escalation.3900635657 |
|
|
Mar 05 01:48:17 PM PST 24 |
Mar 05 01:48:25 PM PST 24 |
185676621 ps |
| T101 |
/workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3011063020 |
|
|
Mar 05 01:48:07 PM PST 24 |
Mar 05 01:53:15 PM PST 24 |
81280548133 ps |
| T1657 |
/workspace/coverage/default/8.lc_ctrl_jtag_errors.3439466760 |
|
|
Mar 05 02:39:33 PM PST 24 |
Mar 05 02:40:12 PM PST 24 |
16450829477 ps |
| T1658 |
/workspace/coverage/default/34.lc_ctrl_prog_failure.3992141103 |
|
|
Mar 05 02:41:35 PM PST 24 |
Mar 05 02:41:37 PM PST 24 |
134999201 ps |
| T1659 |
/workspace/coverage/default/20.lc_ctrl_sec_token_mux.84077270 |
|
|
Mar 05 01:48:23 PM PST 24 |
Mar 05 01:48:34 PM PST 24 |
1100823639 ps |
| T1660 |
/workspace/coverage/default/46.lc_ctrl_state_post_trans.4163965324 |
|
|
Mar 05 01:48:54 PM PST 24 |
Mar 05 01:49:03 PM PST 24 |
211499746 ps |
| T1661 |
/workspace/coverage/default/31.lc_ctrl_stress_all.3143161507 |
|
|
Mar 05 01:48:18 PM PST 24 |
Mar 05 01:49:04 PM PST 24 |
2770257378 ps |
| T1662 |
/workspace/coverage/default/23.lc_ctrl_prog_failure.1871527085 |
|
|
Mar 05 02:41:00 PM PST 24 |
Mar 05 02:41:03 PM PST 24 |
212859413 ps |
| T1663 |
/workspace/coverage/default/0.lc_ctrl_jtag_smoke.1182523812 |
|
|
Mar 05 02:38:20 PM PST 24 |
Mar 05 02:38:34 PM PST 24 |
613525824 ps |
| T1664 |
/workspace/coverage/default/26.lc_ctrl_security_escalation.3779842224 |
|
|
Mar 05 02:41:17 PM PST 24 |
Mar 05 02:41:27 PM PST 24 |
635127906 ps |
| T1665 |
/workspace/coverage/default/42.lc_ctrl_prog_failure.3393714390 |
|
|
Mar 05 02:42:02 PM PST 24 |
Mar 05 02:42:05 PM PST 24 |
294625862 ps |
| T1666 |
/workspace/coverage/default/30.lc_ctrl_jtag_access.3303668587 |
|
|
Mar 05 01:48:13 PM PST 24 |
Mar 05 01:48:21 PM PST 24 |
900079574 ps |
| T1667 |
/workspace/coverage/default/21.lc_ctrl_alert_test.2204014720 |
|
|
Mar 05 01:48:01 PM PST 24 |
Mar 05 01:48:02 PM PST 24 |
37904920 ps |
| T1668 |
/workspace/coverage/default/14.lc_ctrl_state_post_trans.1111668416 |
|
|
Mar 05 02:40:13 PM PST 24 |
Mar 05 02:40:21 PM PST 24 |
373012180 ps |
| T1669 |
/workspace/coverage/default/16.lc_ctrl_sec_token_mux.1688759552 |
|
|
Mar 05 01:48:01 PM PST 24 |
Mar 05 01:48:11 PM PST 24 |
8414821286 ps |
| T1670 |
/workspace/coverage/default/14.lc_ctrl_errors.2245756423 |
|
|
Mar 05 01:47:45 PM PST 24 |
Mar 05 01:47:59 PM PST 24 |
1096569612 ps |
| T1671 |
/workspace/coverage/default/32.lc_ctrl_security_escalation.2705811280 |
|
|
Mar 05 02:41:27 PM PST 24 |
Mar 05 02:41:37 PM PST 24 |
433322092 ps |
| T1672 |
/workspace/coverage/default/42.lc_ctrl_state_post_trans.2847772198 |
|
|
Mar 05 02:42:04 PM PST 24 |
Mar 05 02:42:10 PM PST 24 |
63525416 ps |
| T1673 |
/workspace/coverage/default/11.lc_ctrl_sec_token_mux.468127982 |
|
|
Mar 05 02:39:52 PM PST 24 |
Mar 05 02:40:06 PM PST 24 |
2074915004 ps |
| T1674 |
/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2912705728 |
|
|
Mar 05 01:48:47 PM PST 24 |
Mar 05 01:48:49 PM PST 24 |
14252578 ps |
| T1675 |
/workspace/coverage/default/6.lc_ctrl_regwen_during_op.3867868114 |
|
|
Mar 05 01:47:23 PM PST 24 |
Mar 05 01:47:46 PM PST 24 |
400958631 ps |
| T1676 |
/workspace/coverage/default/1.lc_ctrl_claim_transition_if.2637639884 |
|
|
Mar 05 01:47:13 PM PST 24 |
Mar 05 01:47:14 PM PST 24 |
30963481 ps |
| T1677 |
/workspace/coverage/default/16.lc_ctrl_jtag_errors.4271236301 |
|
|
Mar 05 02:40:32 PM PST 24 |
Mar 05 02:41:24 PM PST 24 |
14964792946 ps |
| T1678 |
/workspace/coverage/default/28.lc_ctrl_sec_mubi.1113625893 |
|
|
Mar 05 01:48:11 PM PST 24 |
Mar 05 01:48:24 PM PST 24 |
359839482 ps |
| T1679 |
/workspace/coverage/default/19.lc_ctrl_jtag_access.2420562273 |
|
|
Mar 05 01:48:03 PM PST 24 |
Mar 05 01:48:08 PM PST 24 |
387287627 ps |
| T168 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1647884613 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:21 PM PST 24 |
271153257 ps |
| T139 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2374586797 |
|
|
Mar 05 01:16:37 PM PST 24 |
Mar 05 01:16:41 PM PST 24 |
435310850 ps |
| T136 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.676369425 |
|
|
Mar 05 01:16:32 PM PST 24 |
Mar 05 01:16:35 PM PST 24 |
51630634 ps |
| T142 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1048376708 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
402130868 ps |
| T137 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3706549127 |
|
|
Mar 05 01:16:22 PM PST 24 |
Mar 05 01:16:26 PM PST 24 |
730432107 ps |
| T138 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.858113310 |
|
|
Mar 05 01:16:27 PM PST 24 |
Mar 05 01:16:28 PM PST 24 |
48128173 ps |
| T148 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2439976151 |
|
|
Mar 05 01:16:11 PM PST 24 |
Mar 05 01:16:13 PM PST 24 |
42389124 ps |
| T169 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1420376252 |
|
|
Mar 05 01:16:30 PM PST 24 |
Mar 05 01:16:33 PM PST 24 |
43182507 ps |
| T1680 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3560015557 |
|
|
Mar 05 01:16:12 PM PST 24 |
Mar 05 01:16:14 PM PST 24 |
66741218 ps |
| T167 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3417715719 |
|
|
Mar 05 01:16:22 PM PST 24 |
Mar 05 01:16:24 PM PST 24 |
342762617 ps |
| T1681 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1024084708 |
|
|
Mar 05 01:16:39 PM PST 24 |
Mar 05 01:16:41 PM PST 24 |
89041536 ps |
| T1682 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.308542651 |
|
|
Mar 05 01:16:22 PM PST 24 |
Mar 05 01:16:30 PM PST 24 |
13218960399 ps |
| T232 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.995738759 |
|
|
Mar 05 01:16:34 PM PST 24 |
Mar 05 01:16:35 PM PST 24 |
85864609 ps |
| T211 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1315434429 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
129817289 ps |
| T166 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2167937209 |
|
|
Mar 05 01:16:38 PM PST 24 |
Mar 05 01:16:41 PM PST 24 |
97622296 ps |
| T1683 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1060108621 |
|
|
Mar 05 01:16:17 PM PST 24 |
Mar 05 01:16:19 PM PST 24 |
216702235 ps |
| T182 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3322588105 |
|
|
Mar 05 01:16:15 PM PST 24 |
Mar 05 01:16:17 PM PST 24 |
12562947 ps |
| T233 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1928587960 |
|
|
Mar 05 01:16:21 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
61609383 ps |
| T140 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4171285897 |
|
|
Mar 05 01:16:43 PM PST 24 |
Mar 05 01:16:47 PM PST 24 |
41778319 ps |
| T1684 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2496447833 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:29 PM PST 24 |
8707361646 ps |
| T1685 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1133866235 |
|
|
Mar 05 01:16:17 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
226837504 ps |
| T1686 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1066234489 |
|
|
Mar 05 01:16:39 PM PST 24 |
Mar 05 01:16:41 PM PST 24 |
45521596 ps |
| T143 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3245668977 |
|
|
Mar 05 01:16:17 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
131629123 ps |
| T141 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3391730285 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:50 PM PST 24 |
233516749 ps |
| T1687 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2698032511 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:48 PM PST 24 |
22807987 ps |
| T234 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3224432873 |
|
|
Mar 05 01:16:35 PM PST 24 |
Mar 05 01:16:37 PM PST 24 |
107618168 ps |
| T235 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.14857952 |
|
|
Mar 05 01:16:42 PM PST 24 |
Mar 05 01:16:44 PM PST 24 |
61134483 ps |
| T1688 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1152092610 |
|
|
Mar 05 01:16:21 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
32606990 ps |
| T1689 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2582309990 |
|
|
Mar 05 01:16:16 PM PST 24 |
Mar 05 01:16:18 PM PST 24 |
272231760 ps |
| T144 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.829853537 |
|
|
Mar 05 01:16:33 PM PST 24 |
Mar 05 01:16:35 PM PST 24 |
88413229 ps |
| T1690 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2635627258 |
|
|
Mar 05 01:16:23 PM PST 24 |
Mar 05 01:16:25 PM PST 24 |
152419212 ps |
| T1691 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2940535291 |
|
|
Mar 05 01:16:43 PM PST 24 |
Mar 05 01:16:47 PM PST 24 |
23565005 ps |
| T1692 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4117224624 |
|
|
Mar 05 01:16:32 PM PST 24 |
Mar 05 01:16:33 PM PST 24 |
77629544 ps |
| T152 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3212384208 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
71355442 ps |
| T1693 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3098856696 |
|
|
Mar 05 01:16:48 PM PST 24 |
Mar 05 01:16:50 PM PST 24 |
207281827 ps |
| T1694 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1577606215 |
|
|
Mar 05 01:16:14 PM PST 24 |
Mar 05 01:16:17 PM PST 24 |
77954837 ps |
| T161 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.614422002 |
|
|
Mar 05 01:16:45 PM PST 24 |
Mar 05 01:16:51 PM PST 24 |
71220288 ps |
| T1695 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3960909104 |
|
|
Mar 05 01:16:12 PM PST 24 |
Mar 05 01:16:14 PM PST 24 |
64957214 ps |
| T1696 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1368610161 |
|
|
Mar 05 01:16:16 PM PST 24 |
Mar 05 01:16:32 PM PST 24 |
1414289719 ps |
| T1697 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.417095531 |
|
|
Mar 05 01:16:38 PM PST 24 |
Mar 05 01:16:42 PM PST 24 |
17228373 ps |
| T236 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.651817617 |
|
|
Mar 05 01:16:43 PM PST 24 |
Mar 05 01:16:46 PM PST 24 |
71058001 ps |
| T163 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.297628295 |
|
|
Mar 05 01:16:18 PM PST 24 |
Mar 05 01:16:21 PM PST 24 |
65990307 ps |
| T237 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3841648113 |
|
|
Mar 05 01:16:38 PM PST 24 |
Mar 05 01:16:41 PM PST 24 |
33235302 ps |
| T222 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1693270751 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:21 PM PST 24 |
63366518 ps |
| T238 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1740813965 |
|
|
Mar 05 01:16:43 PM PST 24 |
Mar 05 01:16:45 PM PST 24 |
27692795 ps |
| T1698 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.648275634 |
|
|
Mar 05 01:16:37 PM PST 24 |
Mar 05 01:16:39 PM PST 24 |
725928300 ps |
| T1699 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1632093185 |
|
|
Mar 05 01:16:26 PM PST 24 |
Mar 05 01:16:31 PM PST 24 |
362771663 ps |
| T156 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1671941834 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:49 PM PST 24 |
81543601 ps |
| T239 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4204954339 |
|
|
Mar 05 01:16:52 PM PST 24 |
Mar 05 01:16:53 PM PST 24 |
38239044 ps |
| T223 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1939429952 |
|
|
Mar 05 01:16:16 PM PST 24 |
Mar 05 01:16:17 PM PST 24 |
29842417 ps |
| T145 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1063401616 |
|
|
Mar 05 01:16:46 PM PST 24 |
Mar 05 01:16:50 PM PST 24 |
1082505454 ps |
| T240 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.109049301 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
141551909 ps |
| T1700 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2701919389 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:48 PM PST 24 |
36902327 ps |
| T1701 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.512900318 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:48 PM PST 24 |
73532683 ps |
| T155 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.118259603 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:49 PM PST 24 |
264368387 ps |
| T1702 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2722758715 |
|
|
Mar 05 01:16:16 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
1091552870 ps |
| T224 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2866845605 |
|
|
Mar 05 01:16:42 PM PST 24 |
Mar 05 01:16:44 PM PST 24 |
26303152 ps |
| T1703 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1653789813 |
|
|
Mar 05 01:16:30 PM PST 24 |
Mar 05 01:16:32 PM PST 24 |
133310542 ps |
| T153 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1208870760 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:51 PM PST 24 |
132945122 ps |
| T1704 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3801097815 |
|
|
Mar 05 01:16:43 PM PST 24 |
Mar 05 01:16:46 PM PST 24 |
91392085 ps |
| T1705 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4073253040 |
|
|
Mar 05 01:16:49 PM PST 24 |
Mar 05 01:16:50 PM PST 24 |
19247725 ps |
| T157 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2227327301 |
|
|
Mar 05 01:16:38 PM PST 24 |
Mar 05 01:16:43 PM PST 24 |
121871335 ps |
| T149 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2068032226 |
|
|
Mar 05 01:16:32 PM PST 24 |
Mar 05 01:16:34 PM PST 24 |
219511509 ps |
| T1706 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2451961810 |
|
|
Mar 05 01:16:13 PM PST 24 |
Mar 05 01:16:16 PM PST 24 |
30388514 ps |
| T1707 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3146991880 |
|
|
Mar 05 01:16:09 PM PST 24 |
Mar 05 01:16:12 PM PST 24 |
93901241 ps |
| T1708 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1674166149 |
|
|
Mar 05 01:16:21 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
406510952 ps |
| T1709 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3138585044 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
1381749758 ps |
| T1710 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3475162761 |
|
|
Mar 05 01:16:14 PM PST 24 |
Mar 05 01:16:16 PM PST 24 |
78896340 ps |
| T1711 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2575061183 |
|
|
Mar 05 01:16:15 PM PST 24 |
Mar 05 01:16:19 PM PST 24 |
289749054 ps |
| T225 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3281361924 |
|
|
Mar 05 01:16:21 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
24802849 ps |
| T226 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1818465818 |
|
|
Mar 05 01:16:14 PM PST 24 |
Mar 05 01:16:16 PM PST 24 |
22485685 ps |
| T1712 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.571748590 |
|
|
Mar 05 01:16:22 PM PST 24 |
Mar 05 01:16:24 PM PST 24 |
29607730 ps |
| T1713 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3585183679 |
|
|
Mar 05 01:16:33 PM PST 24 |
Mar 05 01:16:35 PM PST 24 |
203148683 ps |
| T158 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2130641176 |
|
|
Mar 05 01:16:43 PM PST 24 |
Mar 05 01:16:48 PM PST 24 |
108150350 ps |
| T1714 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2327751588 |
|
|
Mar 05 01:16:22 PM PST 24 |
Mar 05 01:16:25 PM PST 24 |
100059954 ps |
| T1715 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2982279612 |
|
|
Mar 05 01:16:21 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
147397370 ps |
| T1716 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3045788892 |
|
|
Mar 05 01:16:46 PM PST 24 |
Mar 05 01:16:48 PM PST 24 |
53086986 ps |
| T1717 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.528558169 |
|
|
Mar 05 01:16:48 PM PST 24 |
Mar 05 01:16:54 PM PST 24 |
608931218 ps |
| T146 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2081066031 |
|
|
Mar 05 01:16:16 PM PST 24 |
Mar 05 01:16:21 PM PST 24 |
277585725 ps |
| T1718 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.345671007 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:47 PM PST 24 |
12519006 ps |
| T1719 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3475494529 |
|
|
Mar 05 01:16:18 PM PST 24 |
Mar 05 01:16:20 PM PST 24 |
153059557 ps |
| T1720 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3633133644 |
|
|
Mar 05 01:16:54 PM PST 24 |
Mar 05 01:16:55 PM PST 24 |
17686095 ps |
| T1721 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.103515899 |
|
|
Mar 05 01:16:33 PM PST 24 |
Mar 05 01:16:35 PM PST 24 |
105416848 ps |
| T1722 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4111607545 |
|
|
Mar 05 01:16:34 PM PST 24 |
Mar 05 01:16:36 PM PST 24 |
1626285227 ps |
| T1723 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3205847640 |
|
|
Mar 05 01:16:55 PM PST 24 |
Mar 05 01:16:56 PM PST 24 |
48696253 ps |
| T1724 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.644758605 |
|
|
Mar 05 01:16:35 PM PST 24 |
Mar 05 01:16:51 PM PST 24 |
675894439 ps |
| T1725 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.220134598 |
|
|
Mar 05 01:16:12 PM PST 24 |
Mar 05 01:16:14 PM PST 24 |
158353989 ps |
| T1726 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1511765560 |
|
|
Mar 05 01:16:37 PM PST 24 |
Mar 05 01:16:48 PM PST 24 |
3285577432 ps |
| T1727 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1444148107 |
|
|
Mar 05 01:16:22 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
37617511 ps |
| T1728 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3884881412 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:22 PM PST 24 |
24735391 ps |
| T1729 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.58636449 |
|
|
Mar 05 01:16:13 PM PST 24 |
Mar 05 01:16:18 PM PST 24 |
367886927 ps |
| T1730 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3986846525 |
|
|
Mar 05 01:16:39 PM PST 24 |
Mar 05 01:16:42 PM PST 24 |
49613953 ps |
| T1731 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.185743804 |
|
|
Mar 05 01:16:10 PM PST 24 |
Mar 05 01:16:19 PM PST 24 |
928557589 ps |
| T1732 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2411795722 |
|
|
Mar 05 01:16:22 PM PST 24 |
Mar 05 01:16:31 PM PST 24 |
349208511 ps |
| T1733 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.406812186 |
|
|
Mar 05 01:16:35 PM PST 24 |
Mar 05 01:16:41 PM PST 24 |
744722618 ps |
| T1734 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.772965136 |
|
|
Mar 05 01:16:21 PM PST 24 |
Mar 05 01:16:28 PM PST 24 |
2223090624 ps |
| T1735 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2067291834 |
|
|
Mar 05 01:16:11 PM PST 24 |
Mar 05 01:16:12 PM PST 24 |
24121551 ps |
| T1736 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1206505462 |
|
|
Mar 05 01:16:11 PM PST 24 |
Mar 05 01:16:12 PM PST 24 |
173488622 ps |
| T1737 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2864584804 |
|
|
Mar 05 01:16:19 PM PST 24 |
Mar 05 01:16:21 PM PST 24 |
160264961 ps |
| T165 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3787702842 |
|
|
Mar 05 01:16:34 PM PST 24 |
Mar 05 01:16:36 PM PST 24 |
238325536 ps |
| T1738 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.498750635 |
|
|
Mar 05 01:16:10 PM PST 24 |
Mar 05 01:16:13 PM PST 24 |
216624957 ps |
| T1739 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1761973810 |
|
|
Mar 05 01:16:10 PM PST 24 |
Mar 05 01:16:27 PM PST 24 |
2830605153 ps |
| T1740 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2923339617 |
|
|
Mar 05 01:16:33 PM PST 24 |
Mar 05 01:16:35 PM PST 24 |
68751686 ps |
| T1741 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3998404305 |
|
|
Mar 05 01:16:17 PM PST 24 |
Mar 05 01:16:20 PM PST 24 |
44419611 ps |
| T1742 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.322740896 |
|
|
Mar 05 01:16:43 PM PST 24 |
Mar 05 01:16:46 PM PST 24 |
24513128 ps |
| T162 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2578880579 |
|
|
Mar 05 01:16:32 PM PST 24 |
Mar 05 01:16:34 PM PST 24 |
72096181 ps |
| T1743 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1755322577 |
|
|
Mar 05 01:16:26 PM PST 24 |
Mar 05 01:16:28 PM PST 24 |
26694453 ps |
| T160 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3823706469 |
|
|
Mar 05 01:16:12 PM PST 24 |
Mar 05 01:16:15 PM PST 24 |
44694461 ps |
| T1744 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1121359757 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:50 PM PST 24 |
726444999 ps |
| T150 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1402030129 |
|
|
Mar 05 01:16:46 PM PST 24 |
Mar 05 01:16:51 PM PST 24 |
197216106 ps |
| T1745 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.504086292 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:48 PM PST 24 |
29788909 ps |
| T1746 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1234486500 |
|
|
Mar 05 01:16:14 PM PST 24 |
Mar 05 01:16:16 PM PST 24 |
15252298 ps |
| T1747 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2872516473 |
|
|
Mar 05 01:16:34 PM PST 24 |
Mar 05 01:16:46 PM PST 24 |
4851396344 ps |
| T1748 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2514806569 |
|
|
Mar 05 01:16:17 PM PST 24 |
Mar 05 01:16:19 PM PST 24 |
412266852 ps |
| T227 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3134959339 |
|
|
Mar 05 01:16:16 PM PST 24 |
Mar 05 01:16:18 PM PST 24 |
191454857 ps |
| T1749 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2558943104 |
|
|
Mar 05 01:16:45 PM PST 24 |
Mar 05 01:16:50 PM PST 24 |
148628530 ps |
| T1750 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1487907017 |
|
|
Mar 05 01:16:35 PM PST 24 |
Mar 05 01:16:36 PM PST 24 |
24497120 ps |
| T147 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2150750156 |
|
|
Mar 05 01:16:33 PM PST 24 |
Mar 05 01:16:37 PM PST 24 |
430913436 ps |
| T1751 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2191030112 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:21 PM PST 24 |
38051512 ps |
| T1752 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.688354431 |
|
|
Mar 05 01:16:12 PM PST 24 |
Mar 05 01:16:14 PM PST 24 |
38771343 ps |
| T1753 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1902317047 |
|
|
Mar 05 01:16:18 PM PST 24 |
Mar 05 01:16:19 PM PST 24 |
15894989 ps |
| T1754 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.891703373 |
|
|
Mar 05 01:16:14 PM PST 24 |
Mar 05 01:16:20 PM PST 24 |
91499861 ps |
| T1755 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.614156305 |
|
|
Mar 05 01:16:19 PM PST 24 |
Mar 05 01:16:20 PM PST 24 |
19653320 ps |
| T1756 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1054920957 |
|
|
Mar 05 01:16:20 PM PST 24 |
Mar 05 01:16:23 PM PST 24 |
63821735 ps |
| T1757 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3988702986 |
|
|
Mar 05 01:16:11 PM PST 24 |
Mar 05 01:16:13 PM PST 24 |
30498839 ps |
| T1758 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3544072975 |
|
|
Mar 05 01:16:44 PM PST 24 |
Mar 05 01:16:49 PM PST 24 |
598394107 ps |