Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

196327113

1

T1

4499

T2

1275

T3

127999

auto[1]

2820132

1

T3

3430

T5

4508

T6

11810

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

196324661

1

T1

4499

T2

1275

T3

127607

auto[1]

2822584

1

T3

3822

T5

3136

T6

11412

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	14540021	1			T1	1333		T2	82		T3	21009
auto[IdleSt]	39466198	1			T1	1335		T2	1193		T3	4584
auto[ClkMuxSt]	69238	1			T1	14		T4	9		T6	186
auto[CntIncrSt]	68769	1			T1	14		T4	9		T6	186
auto[CntProgSt]	3130817	1			T1	516		T4	18		T6	306
auto[TransCheckSt]	53804	1			T1	14		T4	9		T6	138
auto[TokenHashSt]	78516128	1			T1	264		T4	246		T6	871993
auto[FlashRmaSt]	55714	1			T1	50		T4	9		T6	131
auto[TokenCheck0St]	24532	1			T1	14		T4	9		T6	61
auto[TokenCheck1St]	18003	1			T1	14		T4	9		T6	48
auto[TransProgSt]	827057	1			T1	381		T4	18		T6	94
auto[PostTransSt]	24672603	1			T1	523		T4	576		T6	93255
auto[ScrapSt]	248360	1			T1	27		T6	260		T14	9
auto[EscalateSt]	13558412	1			T3	26037		T5	62106		T6	69089
auto[InvalidSt]	23893606	1			T3	79795		T5	235252		T6	169473

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3983	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	23893606	1			T3	79795		T5	235252		T6	169473
EscalateSt	13558412	1			T3	26037		T5	62106		T6	69089
ScrapSt	248360	1			T1	27		T6	260		T14	9
PostTransSt	24672603	1			T1	523		T4	576		T6	93255
TransProgSt	827057	1			T1	381		T4	18		T6	94
TokenCheck1St	18003	1			T1	14		T4	9		T6	48
TokenCheck0St	24532	1			T1	14		T4	9		T6	61
FlashRmaSt	55714	1			T1	50		T4	9		T6	131
TokenHashSt	78516128	1			T1	264		T4	246		T6	871993
TransCheckSt	53804	1			T1	14		T4	9		T6	138
CntProgSt	3130817	1			T1	516		T4	18		T6	306
CntIncrSt	68769	1			T1	14		T4	9		T6	186
ClkMuxSt	69238	1			T1	14		T4	9		T6	186
IdleSt	39466198	1			T1	1335		T2	1193		T3	4584
ResetSt	14540021	1			T1	1333		T2	82		T3	21009
arcs[ResetSt=>IdleSt]	106623	1			T1	15		T2	1		T3	88
arcs[IdleSt=>ScrapSt]	519	1			T1	1		T6	1		T14	1
arcs[IdleSt=>ClkMuxSt]	68866	1			T1	14		T4	9		T6	186
arcs[ClkMuxSt=>CntIncrSt]	68769	1			T1	14		T4	9		T6	186
arcs[CntIncrSt=>PostTransSt]	3390	1			T6	23		T14	16		T15	3
arcs[CntIncrSt=>CntProgSt]	65241	1			T1	14		T4	9		T6	163
arcs[CntProgSt=>PostTransSt]	9292	1			T6	25		T13	21		T14	20
arcs[CntProgSt=>TransCheckSt]	53804	1			T1	14		T4	9		T6	138
arcs[TransCheckSt=>PostTransSt]	7323	1			T6	15		T14	21		T15	8
arcs[TransCheckSt=>TokenHashSt]	46249	1			T1	14		T4	9		T6	123
arcs[TokenHashSt=>PostTransSt]	20070	1			T6	62		T10	54		T12	60
arcs[TokenHashSt=>FlashRmaSt]	24742	1			T1	14		T4	9		T6	61
arcs[FlashRmaSt=>TokenCheck0St]	24532	1			T1	14		T4	9		T6	61
arcs[TokenCheck0St=>PostTransSt]	6469	1			T6	13		T13	6		T14	22
arcs[TokenCheck0St=>TokenCheck1St]	18003	1			T1	14		T4	9		T6	48
arcs[TokenCheck1St=>PostTransSt]	1288	1			T6	1		T13	1		T14	5
arcs[TransProgSt=>PostTransSt]	14895	1			T1	14		T4	9		T6	47
arcs[IdleSt=>EscalateSt]	395	1			T56	6		T59	6		T57	8
arcs[ClkMuxSt=>EscalateSt]	97	1			T56	1		T57	1		T58	1
arcs[CntIncrSt=>EscalateSt]	138	1			T56	2		T59	6		T57	2
arcs[CntProgSt=>EscalateSt]	2145	1			T56	7		T59	14		T30	15
arcs[TransCheckSt=>EscalateSt]	232	1			T56	9		T59	13		T30	7
arcs[TokenHashSt=>EscalateSt]	1436	1			T14	4		T15	1		T56	29
arcs[FlashRmaSt=>EscalateSt]	210	1			T56	2		T59	1		T30	2
arcs[TokenCheck0St=>EscalateSt]	60	1			T56	1		T30	1		T62	1
arcs[TokenCheck1St=>EscalateSt]	308	1			T56	3		T59	2		T30	4
arcs[TransProgSt=>EscalateSt]	1512	1			T56	12		T59	7		T30	10
arcs[PostTransSt=>EscalateSt]	9794	1			T6	25		T13	21		T14	20
arcs[InvalidSt=>EscalateSt]	28584	1			T3	74		T5	78		T6	211

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14539672	1			T1	1333		T2	82		T3	21009
auto[0]	auto[IdleSt]	39465929	1			T1	1335		T2	1193		T3	4584
auto[0]	auto[ClkMuxSt]	69164	1			T1	14		T4	9		T6	186
auto[0]	auto[CntIncrSt]	68664	1			T1	14		T4	9		T6	186
auto[0]	auto[CntProgSt]	3129380	1			T1	516		T4	18		T6	306
auto[0]	auto[TransCheckSt]	53654	1			T1	14		T4	9		T6	138
auto[0]	auto[TokenHashSt]	78515189	1			T1	264		T4	246		T6	871993
auto[0]	auto[FlashRmaSt]	55593	1			T1	50		T4	9		T6	131
auto[0]	auto[TokenCheck0St]	24501	1			T1	14		T4	9		T6	61
auto[0]	auto[TokenCheck1St]	17801	1			T1	14		T4	9		T6	48
auto[0]	auto[TransProgSt]	826060	1			T1	381		T4	18		T6	94
auto[0]	auto[PostTransSt]	24667637	1			T1	523		T4	576		T6	93242
auto[0]	auto[ScrapSt]	248269	1			T1	27		T6	260		T14	9
auto[0]	auto[EscalateSt]	10762317	1			T3	22642		T5	57644		T6	57399
auto[0]	auto[InvalidSt]	23879300	1			T3	79760		T5	235206		T6	169366
auto[1]	auto[ResetSt]	349	1			T56	2		T59	4		T30	5
auto[1]	auto[IdleSt]	269	1			T56	2		T59	4		T57	7
auto[1]	auto[ClkMuxSt]	74	1			T56	1		T57	1		T58	1
auto[1]	auto[CntIncrSt]	105	1			T56	2		T59	5		T57	1
auto[1]	auto[CntProgSt]	1437	1			T56	4		T59	8		T30	8
auto[1]	auto[TransCheckSt]	150	1			T56	7		T59	7		T30	4
auto[1]	auto[TokenHashSt]	939	1			T14	2		T15	1		T56	21
auto[1]	auto[FlashRmaSt]	121	1			T56	1		T57	2		T253	1
auto[1]	auto[TokenCheck0St]	31	1			T56	1		T62	1		T254	1
auto[1]	auto[TokenCheck1St]	202	1			T56	3		T59	1		T30	2
auto[1]	auto[TransProgSt]	997	1			T56	9		T59	4		T30	5
auto[1]	auto[PostTransSt]	4966	1			T6	13		T13	5		T14	13
auto[1]	auto[ScrapSt]	91	1			T56	2		T30	1		T253	1
auto[1]	auto[EscalateSt]	2796095	1			T3	3395		T5	4462		T6	11690
auto[1]	auto[InvalidSt]	14306	1			T3	35		T5	46		T6	107

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14539674	1			T1	1333		T2	82		T3	21009
auto[0]	auto[IdleSt]	39465944	1			T1	1335		T2	1193		T3	4584
auto[0]	auto[ClkMuxSt]	69177	1			T1	14		T4	9		T6	186
auto[0]	auto[CntIncrSt]	68687	1			T1	14		T4	9		T6	186
auto[0]	auto[CntProgSt]	3129394	1			T1	516		T4	18		T6	306
auto[0]	auto[TransCheckSt]	53653	1			T1	14		T4	9		T6	138
auto[0]	auto[TokenHashSt]	78515150	1			T1	264		T4	246		T6	871993
auto[0]	auto[FlashRmaSt]	55562	1			T1	50		T4	9		T6	131
auto[0]	auto[TokenCheck0St]	24488	1			T1	14		T4	9		T6	61
auto[0]	auto[TokenCheck1St]	17788	1			T1	14		T4	9		T6	48
auto[0]	auto[TransProgSt]	826040	1			T1	381		T4	18		T6	94
auto[0]	auto[PostTransSt]	24667631	1			T1	523		T4	576		T6	93243
auto[0]	auto[ScrapSt]	248282	1			T1	27		T6	260		T14	9
auto[0]	auto[EscalateSt]	10759880	1			T3	22254		T5	59002		T6	57793
auto[0]	auto[InvalidSt]	23879328	1			T3	79756		T5	235220		T6	169369
auto[1]	auto[ResetSt]	347	1			T56	7		T59	4		T30	6
auto[1]	auto[IdleSt]	254	1			T56	6		T59	5		T57	5
auto[1]	auto[ClkMuxSt]	61	1			T56	1		T254	2		T255	1
auto[1]	auto[CntIncrSt]	82	1			T56	2		T59	4		T57	1
auto[1]	auto[CntProgSt]	1423	1			T56	5		T59	11		T30	11
auto[1]	auto[TransCheckSt]	151	1			T56	5		T59	11		T30	5
auto[1]	auto[TokenHashSt]	978	1			T14	2		T56	18		T59	10
auto[1]	auto[FlashRmaSt]	152	1			T56	2		T59	1		T30	2
auto[1]	auto[TokenCheck0St]	44	1			T56	1		T30	1		T254	1
auto[1]	auto[TokenCheck1St]	215	1			T56	3		T59	1		T30	4
auto[1]	auto[TransProgSt]	1017	1			T56	7		T59	6		T30	7
auto[1]	auto[PostTransSt]	4972	1			T6	12		T13	16		T14	7
auto[1]	auto[ScrapSt]	78	1			T56	2		T57	1		T253	1
auto[1]	auto[EscalateSt]	2798532	1			T3	3783		T5	3104		T6	11296
auto[1]	auto[InvalidSt]	14278	1			T3	39		T5	32		T6	104