Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212777280

1

T1

15956

T2

1235

T3

18889

auto[1]

2868843

1

T4

3663

T12

9455

T13

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212746367

1

T1

15956

T2

1235

T3

18889

auto[1]

2899756

1

T4

3168

T12

11184

T13

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	15532746	1			T1	103		T2	110		T3	4861
auto[IdleSt]	44323978	1			T1	15853		T2	1125		T3	4674
auto[ClkMuxSt]	73302	1			T3	51		T5	56		T12	87
auto[CntIncrSt]	72748	1			T3	51		T5	56		T12	83
auto[CntProgSt]	3379207	1			T3	844		T5	1769		T12	329
auto[TransCheckSt]	56767	1			T3	51		T5	56		T12	67
auto[TokenHashSt]	84071449	1			T3	489		T5	5948		T12	15776
auto[FlashRmaSt]	58362	1			T3	14		T5	20		T12	87
auto[TokenCheck0St]	26247	1			T3	14		T5	20		T12	33
auto[TokenCheck1St]	19422	1			T3	5		T5	6		T12	31
auto[TransProgSt]	892761	1			T12	63		T13	2813		T14	10
auto[PostTransSt]	26663629	1			T3	7835		T5	8626		T12	8
auto[ScrapSt]	382885	1			T12	12		T7	2893		T21	20
auto[EscalateSt]	14304385	1			T4	9541		T12	15537		T13	1015
auto[InvalidSt]	25784032	1			T4	9604		T13	580		T15	3650

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	4203	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	25784032	1			T4	9604		T13	580		T15	3650
EscalateSt	14304385	1			T4	9541		T12	15537		T13	1015
ScrapSt	382885	1			T12	12		T7	2893		T21	20
PostTransSt	26663629	1			T3	7835		T5	8626		T12	8
TransProgSt	892761	1			T12	63		T13	2813		T14	10
TokenCheck1St	19422	1			T3	5		T5	6		T12	31
TokenCheck0St	26247	1			T3	14		T5	20		T12	33
FlashRmaSt	58362	1			T3	14		T5	20		T12	87
TokenHashSt	84071449	1			T3	489		T5	5948		T12	15776
TransCheckSt	56767	1			T3	51		T5	56		T12	67
CntProgSt	3379207	1			T3	844		T5	1769		T12	329
CntIncrSt	72748	1			T3	51		T5	56		T12	83
ClkMuxSt	73302	1			T3	51		T5	56		T12	87
IdleSt	44323978	1			T1	15853		T2	1125		T3	4674
ResetSt	15532746	1			T1	103		T2	110		T3	4861
arcs[ResetSt=>IdleSt]	112600	1			T1	1		T2	1		T3	52
arcs[IdleSt=>ScrapSt]	581	1			T12	4		T7	2		T21	1
arcs[IdleSt=>ClkMuxSt]	72869	1			T3	51		T5	56		T12	87
arcs[ClkMuxSt=>CntIncrSt]	72748	1			T3	51		T5	56		T12	83
arcs[CntIncrSt=>PostTransSt]	3587	1			T7	23		T16	29		T17	7
arcs[CntIncrSt=>CntProgSt]	69044	1			T3	51		T5	56		T12	83
arcs[CntProgSt=>PostTransSt]	9939	1			T20	15		T7	28		T16	45
arcs[CntProgSt=>TransCheckSt]	56767	1			T3	51		T5	56		T12	67
arcs[TransCheckSt=>PostTransSt]	7589	1			T3	27		T5	30		T7	28
arcs[TransCheckSt=>TokenHashSt]	48998	1			T3	24		T5	26		T12	65
arcs[TokenHashSt=>PostTransSt]	21345	1			T3	10		T5	6		T22	1
arcs[TokenHashSt=>FlashRmaSt]	26427	1			T3	14		T5	20		T12	35
arcs[FlashRmaSt=>TokenCheck0St]	26247	1			T3	14		T5	20		T12	33
arcs[TokenCheck0St=>PostTransSt]	6753	1			T3	9		T5	14		T7	26
arcs[TokenCheck0St=>TokenCheck1St]	19422	1			T3	5		T5	6		T12	31
arcs[TokenCheck1St=>PostTransSt]	1298	1			T3	5		T5	6		T7	4
arcs[TransProgSt=>PostTransSt]	16324	1			T12	3		T13	5		T14	3
arcs[IdleSt=>EscalateSt]	404	1			T47	11		T48	4		T50	14
arcs[ClkMuxSt=>EscalateSt]	121	1			T12	4		T45	1		T46	1
arcs[CntIncrSt=>EscalateSt]	117	1			T45	1		T47	1		T48	1
arcs[CntProgSt=>EscalateSt]	2338	1			T12	16		T45	19		T49	39
arcs[TransCheckSt=>EscalateSt]	180	1			T12	2		T45	13		T49	1
arcs[TokenHashSt=>EscalateSt]	1226	1			T12	30		T7	3		T45	32
arcs[FlashRmaSt=>EscalateSt]	180	1			T12	2		T49	1		T47	4
arcs[TokenCheck0St=>EscalateSt]	72	1			T12	2		T49	1		T46	2
arcs[TokenCheck1St=>EscalateSt]	274	1			T12	4		T45	5		T49	5
arcs[TransProgSt=>EscalateSt]	1526	1			T12	24		T45	9		T49	21
arcs[PostTransSt=>EscalateSt]	10374	1			T12	3		T20	15		T7	33
arcs[InvalidSt=>EscalateSt]	29645	1			T4	69		T13	4		T15	50

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	15532370	1			T1	103		T2	110		T3	4861
auto[0]	auto[IdleSt]	44323709	1			T1	15853		T2	1125		T3	4674
auto[0]	auto[ClkMuxSt]	73210	1			T3	51		T5	56		T12	85
auto[0]	auto[CntIncrSt]	72679	1			T3	51		T5	56		T12	83
auto[0]	auto[CntProgSt]	3377644	1			T3	844		T5	1769		T12	315
auto[0]	auto[TransCheckSt]	56662	1			T3	51		T5	56		T12	67
auto[0]	auto[TokenHashSt]	84070672	1			T3	489		T5	5948		T12	15762
auto[0]	auto[FlashRmaSt]	58252	1			T3	14		T5	20		T12	85
auto[0]	auto[TokenCheck0St]	26207	1			T3	14		T5	20		T12	31
auto[0]	auto[TokenCheck1St]	19230	1			T3	5		T5	6		T12	28
auto[0]	auto[TransProgSt]	891757	1			T12	46		T13	2813		T14	10
auto[0]	auto[PostTransSt]	26658452	1			T3	7835		T5	8626		T12	7
auto[0]	auto[ScrapSt]	382789	1			T12	8		T7	2893		T21	20
auto[0]	auto[EscalateSt]	11460266	1			T4	5915		T12	6144		T13	819
auto[0]	auto[InvalidSt]	25769178	1			T4	9567		T13	578		T15	3626
auto[1]	auto[ResetSt]	376	1			T12	3		T45	6		T49	8
auto[1]	auto[IdleSt]	269	1			T47	8		T48	4		T50	11
auto[1]	auto[ClkMuxSt]	92	1			T12	2		T45	1		T46	1
auto[1]	auto[CntIncrSt]	69	1			T50	1		T258	1		T259	1
auto[1]	auto[CntProgSt]	1563	1			T12	14		T45	12		T49	27
auto[1]	auto[TransCheckSt]	105	1			T45	7		T49	1		T46	7
auto[1]	auto[TokenHashSt]	777	1			T12	14		T7	2		T45	19
auto[1]	auto[FlashRmaSt]	110	1			T12	2		T47	2		T46	2
auto[1]	auto[TokenCheck0St]	40	1			T12	2		T46	2		T50	1
auto[1]	auto[TokenCheck1St]	192	1			T12	3		T45	3		T49	1
auto[1]	auto[TransProgSt]	1004	1			T12	17		T45	5		T49	12
auto[1]	auto[PostTransSt]	5177	1			T12	1		T20	10		T7	19
auto[1]	auto[ScrapSt]	96	1			T12	4		T45	1		T49	1
auto[1]	auto[EscalateSt]	2844119	1			T4	3626		T12	9393		T13	196
auto[1]	auto[InvalidSt]	14854	1			T4	37		T13	2		T15	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	15532381	1			T1	103		T2	110		T3	4861
auto[0]	auto[IdleSt]	44323702	1			T1	15853		T2	1125		T3	4674
auto[0]	auto[ClkMuxSt]	73237	1			T3	51		T5	56		T12	85
auto[0]	auto[CntIncrSt]	72661	1			T3	51		T5	56		T12	83
auto[0]	auto[CntProgSt]	3377625	1			T3	844		T5	1769		T12	319
auto[0]	auto[TransCheckSt]	56629	1			T3	51		T5	56		T12	65
auto[0]	auto[TokenHashSt]	84070611	1			T3	489		T5	5948		T12	15754
auto[0]	auto[FlashRmaSt]	58240	1			T3	14		T5	20		T12	86
auto[0]	auto[TokenCheck0St]	26199	1			T3	14		T5	20		T12	32
auto[0]	auto[TokenCheck1St]	19243	1			T3	5		T5	6		T12	28
auto[0]	auto[TransProgSt]	891725	1			T12	45		T13	2813		T14	10
auto[0]	auto[PostTransSt]	26658311	1			T3	7835		T5	8626		T12	5
auto[0]	auto[ScrapSt]	382796	1			T12	11		T7	2893		T21	20
auto[0]	auto[EscalateSt]	11429563	1			T4	6405		T12	4421		T13	819
auto[0]	auto[InvalidSt]	25769241	1			T4	9572		T13	578		T15	3624
auto[1]	auto[ResetSt]	365	1			T12	5		T45	2		T49	6
auto[1]	auto[IdleSt]	276	1			T47	8		T48	4		T50	8
auto[1]	auto[ClkMuxSt]	65	1			T12	2		T258	1		T260	1
auto[1]	auto[CntIncrSt]	87	1			T45	1		T47	1		T48	1
auto[1]	auto[CntProgSt]	1582	1			T12	10		T45	13		T49	26
auto[1]	auto[TransCheckSt]	138	1			T12	2		T45	10		T46	7
auto[1]	auto[TokenHashSt]	838	1			T12	22		T7	1		T45	19
auto[1]	auto[FlashRmaSt]	122	1			T12	1		T49	1		T47	3
auto[1]	auto[TokenCheck0St]	48	1			T12	1		T49	1		T46	2
auto[1]	auto[TokenCheck1St]	179	1			T12	3		T45	4		T49	4
auto[1]	auto[TransProgSt]	1036	1			T12	18		T45	8		T49	17
auto[1]	auto[PostTransSt]	5318	1			T12	3		T20	5		T7	14
auto[1]	auto[ScrapSt]	89	1			T12	1		T45	2		T49	1
auto[1]	auto[EscalateSt]	2874822	1			T4	3136		T12	11116		T13	196
auto[1]	auto[InvalidSt]	14791	1			T4	32		T13	2		T15	26