Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195641774

1

T1

5643

T2

29095

T3

333679

auto[1]

2790315

1

T1

297

T2

990

T3

24324

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195651433

1

T1

5841

T2

28303

T3

333545

auto[1]

2780656

1

T1

99

T2

1782

T3

25666

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	14705812	1			T1	1151		T2	6633		T3	175957
auto[IdleSt]	41293469	1			T1	1307		T2	5342		T3	472787
auto[ClkMuxSt]	69264	1			T1	7		T2	39		T3	469
auto[CntIncrSt]	68689	1			T1	7		T2	39		T3	469
auto[CntProgSt]	3566986	1			T1	14		T2	66		T3	22754
auto[TransCheckSt]	54115	1			T1	7		T2	27		T3	347
auto[TokenHashSt]	74736633	1			T1	76		T2	4545		T3	173346
auto[FlashRmaSt]	55907	1			T1	11		T2	59		T3	494
auto[TokenCheck0St]	24672	1			T1	7		T2	23		T3	216
auto[TokenCheck1St]	18273	1			T1	7		T2	14		T3	179
auto[TransProgSt]	870661	1			T1	14		T2	26		T3	9155
auto[PostTransSt]	25760001	1			T1	1840		T2	6233		T3	334557
auto[ScrapSt]	206172	1			T3	1458		T10	3		T17	11755
auto[EscalateSt]	13616015	1			T1	941		T2	4043		T3	201809
auto[InvalidSt]	23381281	1			T1	550		T2	2996		T3	406942

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	4139	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	23381281	1			T1	550		T2	2996		T3	406942
EscalateSt	13616015	1			T1	941		T2	4043		T3	201809
ScrapSt	206172	1			T3	1458		T10	3		T17	11755
PostTransSt	25760001	1			T1	1840		T2	6233		T3	334557
TransProgSt	870661	1			T1	14		T2	26		T3	9155
TokenCheck1St	18273	1			T1	7		T2	14		T3	179
TokenCheck0St	24672	1			T1	7		T2	23		T3	216
FlashRmaSt	55907	1			T1	11		T2	59		T3	494
TokenHashSt	74736633	1			T1	76		T2	4545		T3	173346
TransCheckSt	54115	1			T1	7		T2	27		T3	347
CntProgSt	3566986	1			T1	14		T2	66		T3	22754
CntIncrSt	68689	1			T1	7		T2	39		T3	469
ClkMuxSt	69264	1			T1	7		T2	39		T3	469
IdleSt	41293469	1			T1	1307		T2	5342		T3	472787
ResetSt	14705812	1			T1	1151		T2	6633		T3	175957
arcs[ResetSt=>IdleSt]	107076	1			T1	13		T2	56		T3	984
arcs[IdleSt=>ScrapSt]	595	1			T3	4		T10	1		T17	6
arcs[IdleSt=>ClkMuxSt]	68795	1			T1	7		T2	39		T3	469
arcs[ClkMuxSt=>CntIncrSt]	68689	1			T1	7		T2	39		T3	469
arcs[CntIncrSt=>PostTransSt]	3233	1			T3	32		T14	17		T17	16
arcs[CntIncrSt=>CntProgSt]	65329	1			T1	7		T2	39		T3	437
arcs[CntProgSt=>PostTransSt]	9132	1			T2	12		T3	90		T14	56
arcs[CntProgSt=>TransCheckSt]	54115	1			T1	7		T2	27		T3	347
arcs[TransCheckSt=>PostTransSt]	7355	1			T3	36		T13	26		T14	20
arcs[TransCheckSt=>TokenHashSt]	46512	1			T1	7		T2	27		T3	311
arcs[TokenHashSt=>PostTransSt]	20324	1			T2	4		T3	95		T13	7
arcs[TokenHashSt=>FlashRmaSt]	24879	1			T1	7		T2	23		T3	216
arcs[FlashRmaSt=>TokenCheck0St]	24672	1			T1	7		T2	23		T3	216
arcs[TokenCheck0St=>PostTransSt]	6349	1			T2	9		T3	37		T13	15
arcs[TokenCheck0St=>TokenCheck1St]	18273	1			T1	7		T2	14		T3	179
arcs[TokenCheck1St=>PostTransSt]	1309	1			T2	1		T3	2		T13	5
arcs[TransProgSt=>PostTransSt]	15245	1			T1	7		T2	13		T3	177
arcs[IdleSt=>EscalateSt]	351	1			T10	9		T52	7		T53	9
arcs[ClkMuxSt=>EscalateSt]	106	1			T49	2		T50	4		T51	1
arcs[CntIncrSt=>EscalateSt]	127	1			T10	2		T52	1		T53	2
arcs[CntProgSt=>EscalateSt]	2082	1			T10	29		T52	14		T53	9
arcs[TransCheckSt=>EscalateSt]	248	1			T52	10		T53	11		T50	6
arcs[TokenHashSt=>EscalateSt]	1309	1			T10	6		T39	1		T40	1
arcs[FlashRmaSt=>EscalateSt]	207	1			T10	3		T52	2		T53	2
arcs[TokenCheck0St=>EscalateSt]	50	1			T10	1		T50	1		T51	2
arcs[TokenCheck1St=>EscalateSt]	318	1			T10	4		T52	3		T53	4
arcs[TransProgSt=>EscalateSt]	1401	1			T10	17		T52	16		T53	16
arcs[PostTransSt=>EscalateSt]	9657	1			T2	12		T3	90		T10	1
arcs[InvalidSt=>EscalateSt]	28885	1			T1	4		T2	16		T3	418

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14705436	1			T1	1151		T2	6633		T3	175957
auto[0]	auto[IdleSt]	41293232	1			T1	1307		T2	5342		T3	472787
auto[0]	auto[ClkMuxSt]	69201	1			T1	7		T2	39		T3	469
auto[0]	auto[CntIncrSt]	68602	1			T1	7		T2	39		T3	469
auto[0]	auto[CntProgSt]	3565585	1			T1	14		T2	66		T3	22754
auto[0]	auto[TransCheckSt]	53944	1			T1	7		T2	27		T3	347
auto[0]	auto[TokenHashSt]	74735786	1			T1	76		T2	4545		T3	173346
auto[0]	auto[FlashRmaSt]	55760	1			T1	11		T2	59		T3	494
auto[0]	auto[TokenCheck0St]	24636	1			T1	7		T2	23		T3	216
auto[0]	auto[TokenCheck1St]	18055	1			T1	7		T2	14		T3	179
auto[0]	auto[TransProgSt]	869698	1			T1	14		T2	26		T3	9155
auto[0]	auto[PostTransSt]	25754999	1			T1	1840		T2	6227		T3	334505
auto[0]	auto[ScrapSt]	206063	1			T3	1458		T10	2		T17	11755
auto[0]	auto[EscalateSt]	10849731	1			T1	647		T2	3063		T3	177732
auto[0]	auto[InvalidSt]	23366907	1			T1	547		T2	2992		T3	406747
auto[1]	auto[ResetSt]	376	1			T10	1		T52	4		T53	6
auto[1]	auto[IdleSt]	237	1			T10	6		T52	6		T53	6
auto[1]	auto[ClkMuxSt]	63	1			T49	2		T50	3		T51	1
auto[1]	auto[CntIncrSt]	87	1			T10	2		T52	1		T53	2
auto[1]	auto[CntProgSt]	1401	1			T10	22		T52	9		T53	5
auto[1]	auto[TransCheckSt]	171	1			T52	5		T53	6		T214	5
auto[1]	auto[TokenHashSt]	847	1			T10	3		T39	1		T52	20
auto[1]	auto[FlashRmaSt]	147	1			T10	2		T52	1		T53	1
auto[1]	auto[TokenCheck0St]	36	1			T50	1		T51	2		T214	1
auto[1]	auto[TokenCheck1St]	218	1			T10	3		T52	3		T53	2
auto[1]	auto[TransProgSt]	963	1			T10	7		T52	13		T53	10
auto[1]	auto[PostTransSt]	5002	1			T2	6		T3	52		T10	1
auto[1]	auto[ScrapSt]	109	1			T10	1		T53	1		T49	2
auto[1]	auto[EscalateSt]	2766284	1			T1	294		T2	980		T3	24077
auto[1]	auto[InvalidSt]	14374	1			T1	3		T2	4		T3	195

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14705427	1			T1	1151		T2	6633		T3	175957
auto[0]	auto[IdleSt]	41293234	1			T1	1307		T2	5342		T3	472787
auto[0]	auto[ClkMuxSt]	69184	1			T1	7		T2	39		T3	469
auto[0]	auto[CntIncrSt]	68593	1			T1	7		T2	39		T3	469
auto[0]	auto[CntProgSt]	3565582	1			T1	14		T2	66		T3	22754
auto[0]	auto[TransCheckSt]	53950	1			T1	7		T2	27		T3	347
auto[0]	auto[TokenHashSt]	74735773	1			T1	76		T2	4545		T3	173346
auto[0]	auto[FlashRmaSt]	55766	1			T1	11		T2	59		T3	494
auto[0]	auto[TokenCheck0St]	24633	1			T1	7		T2	23		T3	216
auto[0]	auto[TokenCheck1St]	18074	1			T1	7		T2	14		T3	179
auto[0]	auto[TransProgSt]	869755	1			T1	14		T2	26		T3	9155
auto[0]	auto[PostTransSt]	25755206	1			T1	1840		T2	6227		T3	334519
auto[0]	auto[ScrapSt]	206073	1			T3	1458		T10	3		T17	11755
auto[0]	auto[EscalateSt]	10859274	1			T1	843		T2	2279		T3	176404
auto[0]	auto[InvalidSt]	23366770	1			T1	549		T2	2984		T3	406719
auto[1]	auto[ResetSt]	385	1			T10	5		T52	2		T53	3
auto[1]	auto[IdleSt]	235	1			T10	7		T52	4		T53	7
auto[1]	auto[ClkMuxSt]	80	1			T49	1		T50	3		T215	2
auto[1]	auto[CntIncrSt]	96	1			T10	2		T52	1		T53	1
auto[1]	auto[CntProgSt]	1404	1			T10	15		T52	11		T53	6
auto[1]	auto[TransCheckSt]	165	1			T52	7		T53	7		T50	6
auto[1]	auto[TokenHashSt]	860	1			T10	6		T40	1		T52	18
auto[1]	auto[FlashRmaSt]	141	1			T10	1		T52	2		T53	2
auto[1]	auto[TokenCheck0St]	39	1			T10	1		T50	1		T51	1
auto[1]	auto[TokenCheck1St]	199	1			T10	2		T52	1		T53	2
auto[1]	auto[TransProgSt]	906	1			T10	15		T52	10		T53	8
auto[1]	auto[PostTransSt]	4795	1			T2	6		T3	38		T14	32
auto[1]	auto[ScrapSt]	99	1			T52	1		T49	2		T51	1
auto[1]	auto[EscalateSt]	2756741	1			T1	98		T2	1764		T3	25405
auto[1]	auto[InvalidSt]	14511	1			T1	1		T2	12		T3	223