Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104132006

1

T1

36524

T2

72158

T3

983

auto[1]

1567616

1

T1

294

T4

7399

T5

491

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104128987

1

T1

36622

T2

72158

T3

983

auto[1]

1570635

1

T1

196

T4

8260

T5

295

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7941054	1			T1	1188		T2	7809		T3	89
auto[IdleSt]	21088626	1			T1	9723		T2	7578		T3	52
auto[ClkMuxSt]	37425	1			T1	6		T2	87		T3	1
auto[CntIncrSt]	37137	1			T1	6		T2	87		T3	1
auto[CntProgSt]	1566100	1			T1	109		T2	39122		T3	2
auto[TransCheckSt]	28954	1			T1	6		T2	87		T3	1
auto[TokenHashSt]	41561269	1			T1	476		T2	3939		T3	241
auto[FlashRmaSt]	30300	1			T1	6		T2	35		T3	1
auto[TokenCheck0St]	13392	1			T1	6		T2	31		T3	1
auto[TokenCheck1St]	9924	1			T1	6		T2	6		T3	1
auto[TransProgSt]	428710	1			T1	118		T3	2		T4	1525
auto[PostTransSt]	12847461	1			T1	11459		T2	13377		T3	591
auto[ScrapSt]	149056	1			T4	1725		T12	3		T15	3
auto[EscalateSt]	7353796	1			T1	7017		T4	97883		T5	4877
auto[InvalidSt]	12604104	1			T1	6692		T4	235865		T29	1499

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2314	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12604104	1			T1	6692		T4	235865		T29	1499
EscalateSt	7353796	1			T1	7017		T4	97883		T5	4877
ScrapSt	149056	1			T4	1725		T12	3		T15	3
PostTransSt	12847461	1			T1	11459		T2	13377		T3	591
TransProgSt	428710	1			T1	118		T3	2		T4	1525
TokenCheck1St	9924	1			T1	6		T2	6		T3	1
TokenCheck0St	13392	1			T1	6		T2	31		T3	1
FlashRmaSt	30300	1			T1	6		T2	35		T3	1
TokenHashSt	41561269	1			T1	476		T2	3939		T3	241
TransCheckSt	28954	1			T1	6		T2	87		T3	1
CntProgSt	1566100	1			T1	109		T2	39122		T3	2
CntIncrSt	37137	1			T1	6		T2	87		T3	1
ClkMuxSt	37425	1			T1	6		T2	87		T3	1
IdleSt	21088626	1			T1	9723		T2	7578		T3	52
ResetSt	7941054	1			T1	1188		T2	7809		T3	89
arcs[ResetSt=>IdleSt]	59442	1			T1	13		T2	88		T3	1
arcs[IdleSt=>ScrapSt]	324	1			T4	2		T12	1		T15	1
arcs[IdleSt=>ClkMuxSt]	37186	1			T1	6		T2	87		T3	1
arcs[ClkMuxSt=>CntIncrSt]	37137	1			T1	6		T2	87		T3	1
arcs[CntIncrSt=>PostTransSt]	1764	1			T4	4		T16	5		T17	7
arcs[CntIncrSt=>CntProgSt]	35318	1			T1	6		T2	87		T3	1
arcs[CntProgSt=>PostTransSt]	5226	1			T4	31		T5	8		T14	13
arcs[CntProgSt=>TransCheckSt]	28954	1			T1	6		T2	87		T3	1
arcs[TransCheckSt=>PostTransSt]	3856	1			T2	41		T4	4		T13	43
arcs[TransCheckSt=>TokenHashSt]	24962	1			T1	6		T2	46		T3	1
arcs[TokenHashSt=>PostTransSt]	10753	1			T2	15		T4	9		T11	74
arcs[TokenHashSt=>FlashRmaSt]	13487	1			T1	6		T2	31		T3	1
arcs[FlashRmaSt=>TokenCheck0St]	13392	1			T1	6		T2	31		T3	1
arcs[TokenCheck0St=>PostTransSt]	3440	1			T2	25		T4	5		T13	14
arcs[TokenCheck0St=>TokenCheck1St]	9924	1			T1	6		T2	6		T3	1
arcs[TokenCheck1St=>PostTransSt]	676	1			T2	6		T4	1		T13	12
arcs[TransProgSt=>PostTransSt]	8394	1			T1	6		T3	1		T4	68
arcs[IdleSt=>EscalateSt]	219	1			T12	7		T15	9		T52	4
arcs[ClkMuxSt=>EscalateSt]	49	1			T12	3		T34	3		T52	1
arcs[CntIncrSt=>EscalateSt]	55	1			T12	3		T15	1		T53	2
arcs[CntProgSt=>EscalateSt]	1138	1			T12	26		T15	22		T34	9
arcs[TransCheckSt=>EscalateSt]	136	1			T34	5		T52	5		T56	6
arcs[TokenHashSt=>EscalateSt]	722	1			T12	7		T15	9		T30	1
arcs[FlashRmaSt=>EscalateSt]	95	1			T12	1		T15	2		T34	1
arcs[TokenCheck0St=>EscalateSt]	28	1			T12	1		T15	1		T53	2
arcs[TokenCheck1St=>EscalateSt]	144	1			T12	3		T15	4		T34	2
arcs[TransProgSt=>EscalateSt]	710	1			T12	21		T15	12		T34	9
arcs[PostTransSt=>EscalateSt]	5518	1			T4	31		T5	8		T12	1
arcs[InvalidSt=>EscalateSt]	16788	1			T1	5		T4	128		T29	20

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7940878	1			T1	1188		T2	7809		T3	89
auto[0]	auto[IdleSt]	21088480	1			T1	9723		T2	7578		T3	52
auto[0]	auto[ClkMuxSt]	37392	1			T1	6		T2	87		T3	1
auto[0]	auto[CntIncrSt]	37100	1			T1	6		T2	87		T3	1
auto[0]	auto[CntProgSt]	1565324	1			T1	109		T2	39122		T3	2
auto[0]	auto[TransCheckSt]	28863	1			T1	6		T2	87		T3	1
auto[0]	auto[TokenHashSt]	41560788	1			T1	476		T2	3939		T3	241
auto[0]	auto[FlashRmaSt]	30243	1			T1	6		T2	35		T3	1
auto[0]	auto[TokenCheck0St]	13373	1			T1	6		T2	31		T3	1
auto[0]	auto[TokenCheck1St]	9835	1			T1	6		T2	6		T3	1
auto[0]	auto[TransProgSt]	428225	1			T1	118		T3	2		T4	1525
auto[0]	auto[PostTransSt]	12844650	1			T1	11459		T2	13377		T3	591
auto[0]	auto[ScrapSt]	149011	1			T4	1725		T12	2		T15	2
auto[0]	auto[EscalateSt]	5799798	1			T1	6726		T4	90559		T5	4391
auto[0]	auto[InvalidSt]	12595732	1			T1	6689		T4	235804		T29	1494
auto[1]	auto[ResetSt]	176	1			T12	7		T15	2		T34	4
auto[1]	auto[IdleSt]	146	1			T12	5		T15	5		T52	3
auto[1]	auto[ClkMuxSt]	33	1			T12	3		T34	2		T52	1
auto[1]	auto[CntIncrSt]	37	1			T12	3		T15	1		T53	1
auto[1]	auto[CntProgSt]	776	1			T12	20		T15	14		T34	7
auto[1]	auto[TransCheckSt]	91	1			T34	3		T52	2		T56	3
auto[1]	auto[TokenHashSt]	481	1			T12	5		T15	6		T34	22
auto[1]	auto[FlashRmaSt]	57	1			T12	1		T15	2		T53	2
auto[1]	auto[TokenCheck0St]	19	1			T12	1		T53	2		T232	2
auto[1]	auto[TokenCheck1St]	89	1			T12	3		T15	3		T34	1
auto[1]	auto[TransProgSt]	485	1			T12	14		T15	10		T34	5
auto[1]	auto[PostTransSt]	2811	1			T4	14		T5	5		T12	1
auto[1]	auto[ScrapSt]	45	1			T12	1		T15	1		T34	1
auto[1]	auto[EscalateSt]	1553998	1			T1	291		T4	7324		T5	486
auto[1]	auto[InvalidSt]	8372	1			T1	3		T4	61		T29	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7940869	1			T1	1188		T2	7809		T3	89
auto[0]	auto[IdleSt]	21088476	1			T1	9723		T2	7578		T3	52
auto[0]	auto[ClkMuxSt]	37392	1			T1	6		T2	87		T3	1
auto[0]	auto[CntIncrSt]	37103	1			T1	6		T2	87		T3	1
auto[0]	auto[CntProgSt]	1565352	1			T1	109		T2	39122		T3	2
auto[0]	auto[TransCheckSt]	28860	1			T1	6		T2	87		T3	1
auto[0]	auto[TokenHashSt]	41560787	1			T1	476		T2	3939		T3	241
auto[0]	auto[FlashRmaSt]	30238	1			T1	6		T2	35		T3	1
auto[0]	auto[TokenCheck0St]	13372	1			T1	6		T2	31		T3	1
auto[0]	auto[TokenCheck1St]	9819	1			T1	6		T2	6		T3	1
auto[0]	auto[TransProgSt]	428235	1			T1	118		T3	2		T4	1525
auto[0]	auto[PostTransSt]	12844669	1			T1	11459		T2	13377		T3	591
auto[0]	auto[ScrapSt]	149015	1			T4	1725		T12	3		T15	3
auto[0]	auto[EscalateSt]	5796798	1			T1	6823		T4	89707		T5	4585
auto[0]	auto[InvalidSt]	12595688	1			T1	6690		T4	235798		T29	1484
auto[1]	auto[ResetSt]	185	1			T12	7		T15	3		T34	2
auto[1]	auto[IdleSt]	150	1			T12	2		T15	7		T52	3
auto[1]	auto[ClkMuxSt]	33	1			T12	2		T34	3		T52	1
auto[1]	auto[CntIncrSt]	34	1			T12	1		T53	1		T193	1
auto[1]	auto[CntProgSt]	748	1			T12	17		T15	16		T34	5
auto[1]	auto[TransCheckSt]	94	1			T34	3		T52	3		T56	6
auto[1]	auto[TokenHashSt]	482	1			T12	5		T15	6		T30	1
auto[1]	auto[FlashRmaSt]	62	1			T34	1		T53	2		T82	1
auto[1]	auto[TokenCheck0St]	20	1			T12	1		T15	1		T53	2
auto[1]	auto[TokenCheck1St]	105	1			T12	3		T15	3		T34	2
auto[1]	auto[TransProgSt]	475	1			T12	17		T15	8		T34	6
auto[1]	auto[PostTransSt]	2792	1			T4	17		T5	3		T12	1
auto[1]	auto[ScrapSt]	41	1			T34	1		T53	1		T52	4
auto[1]	auto[EscalateSt]	1556998	1			T1	194		T4	8176		T5	292
auto[1]	auto[InvalidSt]	8416	1			T1	2		T4	67		T29	15