| T808 |
/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.359653091 |
|
|
Mar 14 01:39:57 PM PDT 24 |
Mar 14 01:40:05 PM PDT 24 |
1802182819 ps |
| T809 |
/workspace/coverage/default/15.lc_ctrl_smoke.601284544 |
|
|
Mar 14 01:39:42 PM PDT 24 |
Mar 14 01:39:45 PM PDT 24 |
45379844 ps |
| T810 |
/workspace/coverage/default/5.lc_ctrl_sec_mubi.419896311 |
|
|
Mar 14 01:38:52 PM PDT 24 |
Mar 14 01:39:14 PM PDT 24 |
928390733 ps |
| T811 |
/workspace/coverage/default/16.lc_ctrl_sec_token_mux.1272722335 |
|
|
Mar 14 01:39:58 PM PDT 24 |
Mar 14 01:40:08 PM PDT 24 |
513311724 ps |
| T812 |
/workspace/coverage/default/40.lc_ctrl_state_failure.3633592024 |
|
|
Mar 14 01:40:54 PM PDT 24 |
Mar 14 01:41:17 PM PDT 24 |
236857930 ps |
| T813 |
/workspace/coverage/default/29.lc_ctrl_alert_test.3812293536 |
|
|
Mar 14 01:40:29 PM PDT 24 |
Mar 14 01:40:31 PM PDT 24 |
18041883 ps |
| T814 |
/workspace/coverage/default/48.lc_ctrl_state_failure.2696821801 |
|
|
Mar 14 01:41:14 PM PDT 24 |
Mar 14 01:41:34 PM PDT 24 |
264840508 ps |
| T815 |
/workspace/coverage/default/3.lc_ctrl_errors.2884379347 |
|
|
Mar 14 01:38:39 PM PDT 24 |
Mar 14 01:38:52 PM PDT 24 |
234889553 ps |
| T816 |
/workspace/coverage/default/31.lc_ctrl_errors.4132387479 |
|
|
Mar 14 01:40:44 PM PDT 24 |
Mar 14 01:41:01 PM PDT 24 |
10512880105 ps |
| T817 |
/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.851636482 |
|
|
Mar 14 01:40:26 PM PDT 24 |
Mar 14 01:40:27 PM PDT 24 |
17232234 ps |
| T818 |
/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.210776103 |
|
|
Mar 14 01:40:26 PM PDT 24 |
Mar 14 01:40:28 PM PDT 24 |
32900483 ps |
| T819 |
/workspace/coverage/default/49.lc_ctrl_errors.1622856923 |
|
|
Mar 14 01:41:15 PM PDT 24 |
Mar 14 01:41:26 PM PDT 24 |
2327154392 ps |
| T820 |
/workspace/coverage/default/12.lc_ctrl_prog_failure.661787456 |
|
|
Mar 14 01:39:36 PM PDT 24 |
Mar 14 01:39:39 PM PDT 24 |
209319992 ps |
| T821 |
/workspace/coverage/default/38.lc_ctrl_prog_failure.3916997195 |
|
|
Mar 14 01:40:49 PM PDT 24 |
Mar 14 01:40:52 PM PDT 24 |
100301741 ps |
| T822 |
/workspace/coverage/default/6.lc_ctrl_jtag_priority.2903067943 |
|
|
Mar 14 01:39:03 PM PDT 24 |
Mar 14 01:39:06 PM PDT 24 |
239312454 ps |
| T823 |
/workspace/coverage/default/35.lc_ctrl_sec_token_digest.1316220690 |
|
|
Mar 14 01:40:49 PM PDT 24 |
Mar 14 01:41:11 PM PDT 24 |
2610238281 ps |
| T824 |
/workspace/coverage/default/2.lc_ctrl_smoke.3582710209 |
|
|
Mar 14 01:38:43 PM PDT 24 |
Mar 14 01:38:45 PM PDT 24 |
34944586 ps |
| T825 |
/workspace/coverage/default/46.lc_ctrl_jtag_access.3132517289 |
|
|
Mar 14 01:41:16 PM PDT 24 |
Mar 14 01:41:18 PM PDT 24 |
207881045 ps |
| T826 |
/workspace/coverage/default/46.lc_ctrl_errors.3157738148 |
|
|
Mar 14 01:41:05 PM PDT 24 |
Mar 14 01:41:14 PM PDT 24 |
495110270 ps |
| T827 |
/workspace/coverage/default/25.lc_ctrl_alert_test.1559921357 |
|
|
Mar 14 01:40:10 PM PDT 24 |
Mar 14 01:40:11 PM PDT 24 |
20753177 ps |
| T828 |
/workspace/coverage/default/37.lc_ctrl_state_post_trans.3885136648 |
|
|
Mar 14 01:40:54 PM PDT 24 |
Mar 14 01:41:04 PM PDT 24 |
112080148 ps |
| T829 |
/workspace/coverage/default/5.lc_ctrl_claim_transition_if.3800777927 |
|
|
Mar 14 01:39:05 PM PDT 24 |
Mar 14 01:39:07 PM PDT 24 |
10528242 ps |
| T830 |
/workspace/coverage/default/15.lc_ctrl_sec_token_digest.3371429421 |
|
|
Mar 14 01:39:55 PM PDT 24 |
Mar 14 01:40:10 PM PDT 24 |
522835078 ps |
| T831 |
/workspace/coverage/default/33.lc_ctrl_security_escalation.1692766550 |
|
|
Mar 14 01:40:43 PM PDT 24 |
Mar 14 01:40:50 PM PDT 24 |
178921451 ps |
| T832 |
/workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4154948593 |
|
|
Mar 14 01:41:13 PM PDT 24 |
Mar 14 02:09:16 PM PDT 24 |
57630461646 ps |
| T833 |
/workspace/coverage/default/37.lc_ctrl_sec_token_digest.1322272982 |
|
|
Mar 14 01:40:55 PM PDT 24 |
Mar 14 01:41:04 PM PDT 24 |
283700328 ps |
| T81 |
/workspace/coverage/default/27.lc_ctrl_smoke.2931087202 |
|
|
Mar 14 01:40:28 PM PDT 24 |
Mar 14 01:40:32 PM PDT 24 |
82661875 ps |
| T834 |
/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2980248775 |
|
|
Mar 14 01:40:00 PM PDT 24 |
Mar 14 01:40:31 PM PDT 24 |
2345001954 ps |
| T835 |
/workspace/coverage/default/24.lc_ctrl_state_post_trans.1415832822 |
|
|
Mar 14 01:40:10 PM PDT 24 |
Mar 14 01:40:20 PM PDT 24 |
654652570 ps |
| T836 |
/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3847065757 |
|
|
Mar 14 01:39:35 PM PDT 24 |
Mar 14 01:40:42 PM PDT 24 |
8499298702 ps |
| T837 |
/workspace/coverage/default/20.lc_ctrl_alert_test.2222320742 |
|
|
Mar 14 01:40:11 PM PDT 24 |
Mar 14 01:40:13 PM PDT 24 |
98678185 ps |
| T838 |
/workspace/coverage/default/32.lc_ctrl_sec_token_mux.1776314161 |
|
|
Mar 14 01:40:40 PM PDT 24 |
Mar 14 01:40:49 PM PDT 24 |
171008001 ps |
| T839 |
/workspace/coverage/default/43.lc_ctrl_sec_token_mux.3930701464 |
|
|
Mar 14 01:41:06 PM PDT 24 |
Mar 14 01:41:12 PM PDT 24 |
626022628 ps |
| T840 |
/workspace/coverage/default/9.lc_ctrl_regwen_during_op.2770165552 |
|
|
Mar 14 01:39:22 PM PDT 24 |
Mar 14 01:39:36 PM PDT 24 |
767000837 ps |
| T841 |
/workspace/coverage/default/5.lc_ctrl_jtag_smoke.1580142537 |
|
|
Mar 14 01:39:07 PM PDT 24 |
Mar 14 01:39:21 PM PDT 24 |
2019391766 ps |
| T842 |
/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1601369809 |
|
|
Mar 14 01:39:23 PM PDT 24 |
Mar 14 01:39:58 PM PDT 24 |
3222985980 ps |
| T843 |
/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3226546242 |
|
|
Mar 14 01:38:26 PM PDT 24 |
Mar 14 01:38:38 PM PDT 24 |
347500337 ps |
| T844 |
/workspace/coverage/default/42.lc_ctrl_sec_token_digest.4239767400 |
|
|
Mar 14 01:41:05 PM PDT 24 |
Mar 14 01:41:19 PM PDT 24 |
1729713001 ps |
| T845 |
/workspace/coverage/default/46.lc_ctrl_state_failure.1741710524 |
|
|
Mar 14 01:41:15 PM PDT 24 |
Mar 14 01:41:43 PM PDT 24 |
2735695292 ps |
| T846 |
/workspace/coverage/default/10.lc_ctrl_sec_token_digest.3377119347 |
|
|
Mar 14 01:39:23 PM PDT 24 |
Mar 14 01:39:34 PM PDT 24 |
2032283653 ps |
| T847 |
/workspace/coverage/default/35.lc_ctrl_state_failure.1034176894 |
|
|
Mar 14 01:40:45 PM PDT 24 |
Mar 14 01:41:11 PM PDT 24 |
1140851849 ps |
| T848 |
/workspace/coverage/default/19.lc_ctrl_jtag_access.2389856364 |
|
|
Mar 14 01:40:09 PM PDT 24 |
Mar 14 01:40:16 PM PDT 24 |
576224076 ps |
| T849 |
/workspace/coverage/default/47.lc_ctrl_sec_token_digest.2405715612 |
|
|
Mar 14 01:41:16 PM PDT 24 |
Mar 14 01:41:32 PM PDT 24 |
3934737327 ps |
| T850 |
/workspace/coverage/default/46.lc_ctrl_sec_mubi.334950870 |
|
|
Mar 14 01:41:11 PM PDT 24 |
Mar 14 01:41:22 PM PDT 24 |
1153298150 ps |
| T851 |
/workspace/coverage/default/18.lc_ctrl_prog_failure.1689297598 |
|
|
Mar 14 01:39:59 PM PDT 24 |
Mar 14 01:40:02 PM PDT 24 |
28614697 ps |
| T852 |
/workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.596405116 |
|
|
Mar 14 01:38:38 PM PDT 24 |
Mar 14 01:56:16 PM PDT 24 |
23315955894 ps |
| T853 |
/workspace/coverage/default/19.lc_ctrl_prog_failure.1463917707 |
|
|
Mar 14 01:40:10 PM PDT 24 |
Mar 14 01:40:13 PM PDT 24 |
47539413 ps |
| T854 |
/workspace/coverage/default/40.lc_ctrl_state_post_trans.3321376615 |
|
|
Mar 14 01:40:57 PM PDT 24 |
Mar 14 01:41:05 PM PDT 24 |
44641964 ps |
| T855 |
/workspace/coverage/default/39.lc_ctrl_sec_token_digest.3683214138 |
|
|
Mar 14 01:40:53 PM PDT 24 |
Mar 14 01:41:04 PM PDT 24 |
268715243 ps |
| T856 |
/workspace/coverage/default/19.lc_ctrl_stress_all.2435021147 |
|
|
Mar 14 01:40:10 PM PDT 24 |
Mar 14 01:40:34 PM PDT 24 |
3633179646 ps |
| T857 |
/workspace/coverage/default/30.lc_ctrl_jtag_access.869259653 |
|
|
Mar 14 01:40:40 PM PDT 24 |
Mar 14 01:40:45 PM PDT 24 |
268741646 ps |
| T858 |
/workspace/coverage/default/40.lc_ctrl_alert_test.1835791291 |
|
|
Mar 14 01:41:04 PM PDT 24 |
Mar 14 01:41:05 PM PDT 24 |
42542237 ps |
| T859 |
/workspace/coverage/default/38.lc_ctrl_state_post_trans.2410700419 |
|
|
Mar 14 01:40:54 PM PDT 24 |
Mar 14 01:41:01 PM PDT 24 |
81870155 ps |
| T860 |
/workspace/coverage/default/28.lc_ctrl_alert_test.1143446560 |
|
|
Mar 14 01:40:28 PM PDT 24 |
Mar 14 01:40:31 PM PDT 24 |
50129750 ps |
| T861 |
/workspace/coverage/default/41.lc_ctrl_sec_mubi.704016532 |
|
|
Mar 14 01:41:03 PM PDT 24 |
Mar 14 01:41:18 PM PDT 24 |
282017779 ps |
| T862 |
/workspace/coverage/default/17.lc_ctrl_jtag_access.675596254 |
|
|
Mar 14 01:39:59 PM PDT 24 |
Mar 14 01:40:04 PM PDT 24 |
713104527 ps |
| T863 |
/workspace/coverage/default/31.lc_ctrl_prog_failure.1441006627 |
|
|
Mar 14 01:40:44 PM PDT 24 |
Mar 14 01:40:48 PM PDT 24 |
1333955970 ps |
| T864 |
/workspace/coverage/default/26.lc_ctrl_stress_all.2950950740 |
|
|
Mar 14 01:40:32 PM PDT 24 |
Mar 14 01:41:19 PM PDT 24 |
2086767932 ps |
| T865 |
/workspace/coverage/default/31.lc_ctrl_state_failure.1587662232 |
|
|
Mar 14 01:40:42 PM PDT 24 |
Mar 14 01:41:11 PM PDT 24 |
903886980 ps |
| T866 |
/workspace/coverage/default/25.lc_ctrl_sec_mubi.1522065365 |
|
|
Mar 14 01:40:14 PM PDT 24 |
Mar 14 01:40:28 PM PDT 24 |
1256950084 ps |
| T867 |
/workspace/coverage/default/17.lc_ctrl_sec_token_mux.727677315 |
|
|
Mar 14 01:39:57 PM PDT 24 |
Mar 14 01:40:06 PM PDT 24 |
1211170273 ps |
| T868 |
/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1158293816 |
|
|
Mar 14 01:39:33 PM PDT 24 |
Mar 14 01:39:34 PM PDT 24 |
49480593 ps |
| T869 |
/workspace/coverage/default/41.lc_ctrl_errors.3990892649 |
|
|
Mar 14 01:41:07 PM PDT 24 |
Mar 14 01:41:25 PM PDT 24 |
432133233 ps |
| T870 |
/workspace/coverage/default/27.lc_ctrl_security_escalation.3535915887 |
|
|
Mar 14 01:40:32 PM PDT 24 |
Mar 14 01:40:43 PM PDT 24 |
1020520754 ps |
| T871 |
/workspace/coverage/default/5.lc_ctrl_smoke.1642414806 |
|
|
Mar 14 01:38:53 PM PDT 24 |
Mar 14 01:39:00 PM PDT 24 |
202838891 ps |
| T872 |
/workspace/coverage/default/10.lc_ctrl_prog_failure.3449800547 |
|
|
Mar 14 01:39:28 PM PDT 24 |
Mar 14 01:39:33 PM PDT 24 |
69484129 ps |
| T873 |
/workspace/coverage/default/4.lc_ctrl_stress_all.2305269498 |
|
|
Mar 14 01:38:57 PM PDT 24 |
Mar 14 01:43:43 PM PDT 24 |
9639288218 ps |
| T874 |
/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.481589048 |
|
|
Mar 14 01:40:00 PM PDT 24 |
Mar 14 01:40:19 PM PDT 24 |
6913204118 ps |
| T875 |
/workspace/coverage/default/16.lc_ctrl_state_failure.1143235666 |
|
|
Mar 14 01:39:52 PM PDT 24 |
Mar 14 01:40:23 PM PDT 24 |
919766459 ps |
| T876 |
/workspace/coverage/default/43.lc_ctrl_sec_token_digest.157812896 |
|
|
Mar 14 01:41:08 PM PDT 24 |
Mar 14 01:41:22 PM PDT 24 |
768924200 ps |
| T877 |
/workspace/coverage/default/1.lc_ctrl_security_escalation.736808579 |
|
|
Mar 14 01:38:28 PM PDT 24 |
Mar 14 01:38:39 PM PDT 24 |
1386163639 ps |
| T133 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3136853707 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:14:59 PM PDT 24 |
59785743 ps |
| T134 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2957443987 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
80720054 ps |
| T129 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2437098365 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
179843248 ps |
| T130 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.937651325 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
21364147 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3115744184 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
74432579 ps |
| T123 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3213783126 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
137755737 ps |
| T204 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.660708909 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:00 PM PDT 24 |
12036493 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.214685781 |
|
|
Mar 14 01:14:31 PM PDT 24 |
Mar 14 01:14:33 PM PDT 24 |
108894227 ps |
| T152 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2078020192 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
59919008 ps |
| T217 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.491213352 |
|
|
Mar 14 01:14:51 PM PDT 24 |
Mar 14 01:14:53 PM PDT 24 |
55638287 ps |
| T218 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1069651484 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
14973927 ps |
| T126 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.425719159 |
|
|
Mar 14 01:14:53 PM PDT 24 |
Mar 14 01:14:57 PM PDT 24 |
50526516 ps |
| T225 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.39682609 |
|
|
Mar 14 01:14:41 PM PDT 24 |
Mar 14 01:14:54 PM PDT 24 |
2967754109 ps |
| T150 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.4266337766 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
75296906 ps |
| T132 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3660680176 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:02 PM PDT 24 |
561720059 ps |
| T219 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3271610138 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
11055810 ps |
| T127 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1421050956 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
413258028 ps |
| T163 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.424343167 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:36 PM PDT 24 |
34162341 ps |
| T159 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2733798173 |
|
|
Mar 14 01:14:32 PM PDT 24 |
Mar 14 01:14:34 PM PDT 24 |
399360308 ps |
| T878 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4293898352 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:43 PM PDT 24 |
473014564 ps |
| T164 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2230882574 |
|
|
Mar 14 01:14:33 PM PDT 24 |
Mar 14 01:14:34 PM PDT 24 |
291973443 ps |
| T220 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3554401340 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
16104039 ps |
| T221 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2609037973 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
27165686 ps |
| T222 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2994065379 |
|
|
Mar 14 01:14:47 PM PDT 24 |
Mar 14 01:14:48 PM PDT 24 |
100057927 ps |
| T879 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.108974803 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:45 PM PDT 24 |
496421965 ps |
| T223 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.567710263 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
68913162 ps |
| T128 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.274312776 |
|
|
Mar 14 01:14:49 PM PDT 24 |
Mar 14 01:14:52 PM PDT 24 |
153015965 ps |
| T151 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2445157335 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:42 PM PDT 24 |
451885778 ps |
| T880 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1256384021 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
410791920 ps |
| T160 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1658796220 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
79482243 ps |
| T139 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1739428588 |
|
|
Mar 14 01:14:51 PM PDT 24 |
Mar 14 01:14:53 PM PDT 24 |
24137704 ps |
| T881 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1538592429 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:46 PM PDT 24 |
130645606 ps |
| T161 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1151340000 |
|
|
Mar 14 01:14:15 PM PDT 24 |
Mar 14 01:14:16 PM PDT 24 |
131457786 ps |
| T882 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1080216534 |
|
|
Mar 14 01:14:53 PM PDT 24 |
Mar 14 01:14:55 PM PDT 24 |
96455582 ps |
| T205 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3925922266 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
16639076 ps |
| T883 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.202106807 |
|
|
Mar 14 01:14:49 PM PDT 24 |
Mar 14 01:14:50 PM PDT 24 |
29453942 ps |
| T884 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1443152379 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:00 PM PDT 24 |
25234492 ps |
| T885 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2781624754 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:15:30 PM PDT 24 |
49219033238 ps |
| T886 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2869862250 |
|
|
Mar 14 01:14:13 PM PDT 24 |
Mar 14 01:14:14 PM PDT 24 |
53678571 ps |
| T206 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4008018856 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
33232257 ps |
| T887 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1797744150 |
|
|
Mar 14 01:14:55 PM PDT 24 |
Mar 14 01:14:57 PM PDT 24 |
139784612 ps |
| T141 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2435370251 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:01 PM PDT 24 |
629153275 ps |
| T888 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3946086505 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
52559230 ps |
| T889 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3663713160 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:01 PM PDT 24 |
63214122 ps |
| T890 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2239809670 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
43092779 ps |
| T142 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1090954095 |
|
|
Mar 14 01:14:55 PM PDT 24 |
Mar 14 01:14:57 PM PDT 24 |
313316396 ps |
| T891 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.769387643 |
|
|
Mar 14 01:14:55 PM PDT 24 |
Mar 14 01:14:56 PM PDT 24 |
81251423 ps |
| T892 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2861143707 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
30692888 ps |
| T893 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2019473588 |
|
|
Mar 14 01:14:42 PM PDT 24 |
Mar 14 01:14:44 PM PDT 24 |
45867386 ps |
| T894 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1420543974 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
76090740 ps |
| T207 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1889761184 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:36 PM PDT 24 |
76921141 ps |
| T895 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4065730377 |
|
|
Mar 14 01:14:33 PM PDT 24 |
Mar 14 01:14:36 PM PDT 24 |
80219066 ps |
| T896 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2570821891 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:43 PM PDT 24 |
434508792 ps |
| T208 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4093674988 |
|
|
Mar 14 01:14:32 PM PDT 24 |
Mar 14 01:14:33 PM PDT 24 |
51057324 ps |
| T897 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3979762738 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
128982299 ps |
| T209 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2514065632 |
|
|
Mar 14 01:14:48 PM PDT 24 |
Mar 14 01:14:49 PM PDT 24 |
71090836 ps |
| T898 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4259702202 |
|
|
Mar 14 01:14:41 PM PDT 24 |
Mar 14 01:14:43 PM PDT 24 |
397284536 ps |
| T899 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2278521104 |
|
|
Mar 14 01:14:54 PM PDT 24 |
Mar 14 01:14:56 PM PDT 24 |
39406412 ps |
| T900 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2900831777 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
389573082 ps |
| T901 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1002591114 |
|
|
Mar 14 01:14:48 PM PDT 24 |
Mar 14 01:14:51 PM PDT 24 |
990603443 ps |
| T135 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2304216399 |
|
|
Mar 14 01:14:15 PM PDT 24 |
Mar 14 01:14:18 PM PDT 24 |
233544530 ps |
| T138 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3257776625 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:42 PM PDT 24 |
426448926 ps |
| T902 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1882688114 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:48 PM PDT 24 |
1490714492 ps |
| T903 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3742463839 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
73044507 ps |
| T904 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1306244305 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:59 PM PDT 24 |
981919019 ps |
| T905 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.18640036 |
|
|
Mar 14 01:14:42 PM PDT 24 |
Mar 14 01:14:44 PM PDT 24 |
76559539 ps |
| T906 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2525900586 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
201431365 ps |
| T210 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3809281279 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:36 PM PDT 24 |
20304935 ps |
| T907 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3863329935 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:54 PM PDT 24 |
3022507951 ps |
| T136 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3366276522 |
|
|
Mar 14 01:14:51 PM PDT 24 |
Mar 14 01:14:58 PM PDT 24 |
236851644 ps |
| T908 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2845404731 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
247440363 ps |
| T909 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1722585686 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
270790712 ps |
| T910 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2040090888 |
|
|
Mar 14 01:14:50 PM PDT 24 |
Mar 14 01:14:52 PM PDT 24 |
31779440 ps |
| T911 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1081574294 |
|
|
Mar 14 01:14:48 PM PDT 24 |
Mar 14 01:14:50 PM PDT 24 |
15964135 ps |
| T912 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.184849735 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:00 PM PDT 24 |
23932835 ps |
| T913 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3214048538 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:42 PM PDT 24 |
60469541 ps |
| T914 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2257050576 |
|
|
Mar 14 01:14:54 PM PDT 24 |
Mar 14 01:14:56 PM PDT 24 |
71403653 ps |
| T915 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.76482627 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
47828578 ps |
| T916 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2558398209 |
|
|
Mar 14 01:14:33 PM PDT 24 |
Mar 14 01:14:35 PM PDT 24 |
33911534 ps |
| T917 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.229657288 |
|
|
Mar 14 01:14:16 PM PDT 24 |
Mar 14 01:14:17 PM PDT 24 |
47106229 ps |
| T147 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.756669137 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
86788744 ps |
| T918 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2284939810 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:01 PM PDT 24 |
184799169 ps |
| T919 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3839491284 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:14:59 PM PDT 24 |
20345287 ps |
| T920 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1650203283 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:35 PM PDT 24 |
40476396 ps |
| T921 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1868575211 |
|
|
Mar 14 01:14:41 PM PDT 24 |
Mar 14 01:14:45 PM PDT 24 |
99192804 ps |
| T922 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2591562613 |
|
|
Mar 14 01:14:15 PM PDT 24 |
Mar 14 01:14:18 PM PDT 24 |
777838328 ps |
| T923 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1804279844 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
31770038 ps |
| T924 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.775701719 |
|
|
Mar 14 01:14:54 PM PDT 24 |
Mar 14 01:14:55 PM PDT 24 |
22956606 ps |
| T925 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1723155988 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:53 PM PDT 24 |
3246653646 ps |
| T926 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3909887331 |
|
|
Mar 14 01:14:45 PM PDT 24 |
Mar 14 01:14:46 PM PDT 24 |
37819566 ps |
| T927 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1949733890 |
|
|
Mar 14 01:14:42 PM PDT 24 |
Mar 14 01:14:44 PM PDT 24 |
32174837 ps |
| T928 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3275482366 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
28697605 ps |
| T212 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3634138053 |
|
|
Mar 14 01:14:51 PM PDT 24 |
Mar 14 01:14:52 PM PDT 24 |
13967194 ps |
| T929 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2265577792 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
64916180 ps |
| T930 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2083778786 |
|
|
Mar 14 01:14:41 PM PDT 24 |
Mar 14 01:14:43 PM PDT 24 |
27570256 ps |
| T931 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1144723509 |
|
|
Mar 14 01:14:45 PM PDT 24 |
Mar 14 01:14:46 PM PDT 24 |
62145892 ps |
| T932 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2303386159 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
83021805 ps |
| T933 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1172917983 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
65230550 ps |
| T211 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3167979533 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
14431962 ps |
| T934 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4098719526 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:51 PM PDT 24 |
675227518 ps |
| T935 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2944642644 |
|
|
Mar 14 01:14:49 PM PDT 24 |
Mar 14 01:14:54 PM PDT 24 |
251442772 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.85301718 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
87896229 ps |
| T937 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2198202729 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
182084360 ps |
| T148 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3851758366 |
|
|
Mar 14 01:14:47 PM PDT 24 |
Mar 14 01:14:50 PM PDT 24 |
124729128 ps |
| T140 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2527161961 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:43 PM PDT 24 |
88455940 ps |
| T938 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3743710149 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:36 PM PDT 24 |
158283584 ps |
| T213 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2732497598 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
94562269 ps |
| T143 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3786526862 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
117659213 ps |
| T939 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4160463050 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
45613696 ps |
| T940 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1809937352 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:47 PM PDT 24 |
495760571 ps |
| T941 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3761293066 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
147123432 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2410554284 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:52 PM PDT 24 |
572485622 ps |
| T943 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.177520986 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
128848027 ps |
| T944 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2144605791 |
|
|
Mar 14 01:14:18 PM PDT 24 |
Mar 14 01:14:19 PM PDT 24 |
1450559660 ps |
| T945 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3888007123 |
|
|
Mar 14 01:14:48 PM PDT 24 |
Mar 14 01:14:52 PM PDT 24 |
175000727 ps |
| T946 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1349177492 |
|
|
Mar 14 01:14:16 PM PDT 24 |
Mar 14 01:14:20 PM PDT 24 |
567556509 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3388296409 |
|
|
Mar 14 01:14:39 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
527437405 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3853436300 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
429349143 ps |
| T137 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2616583714 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
118179318 ps |
| T949 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1982561453 |
|
|
Mar 14 01:14:48 PM PDT 24 |
Mar 14 01:14:50 PM PDT 24 |
21558799 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1065045621 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
220568696 ps |
| T149 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.109961953 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
557988893 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1839547422 |
|
|
Mar 14 01:14:32 PM PDT 24 |
Mar 14 01:14:34 PM PDT 24 |
155218090 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2711182558 |
|
|
Mar 14 01:14:43 PM PDT 24 |
Mar 14 01:14:45 PM PDT 24 |
392494300 ps |
| T953 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.303750373 |
|
|
Mar 14 01:14:53 PM PDT 24 |
Mar 14 01:14:54 PM PDT 24 |
14718331 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1377946613 |
|
|
Mar 14 01:14:17 PM PDT 24 |
Mar 14 01:14:19 PM PDT 24 |
48446103 ps |
| T955 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1181349881 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
17404970 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3626240586 |
|
|
Mar 14 01:14:32 PM PDT 24 |
Mar 14 01:14:33 PM PDT 24 |
32774038 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3868603109 |
|
|
Mar 14 01:14:34 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
69540802 ps |
| T145 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.943955404 |
|
|
Mar 14 01:14:47 PM PDT 24 |
Mar 14 01:14:50 PM PDT 24 |
411254380 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2791817455 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:15:00 PM PDT 24 |
6571351954 ps |
| T959 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4064401146 |
|
|
Mar 14 01:14:41 PM PDT 24 |
Mar 14 01:14:45 PM PDT 24 |
243740860 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2947671606 |
|
|
Mar 14 01:14:40 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
84130469 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1882119942 |
|
|
Mar 14 01:14:41 PM PDT 24 |
Mar 14 01:14:51 PM PDT 24 |
359406457 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2133290003 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
155818376 ps |
| T216 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.583458029 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
18770969 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3130127271 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
57926249 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1321763925 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:00 PM PDT 24 |
16500452 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1579801468 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
77184341 ps |
| T214 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.729813227 |
|
|
Mar 14 01:14:18 PM PDT 24 |
Mar 14 01:14:19 PM PDT 24 |
18162198 ps |
| T966 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1632235184 |
|
|
Mar 14 01:14:54 PM PDT 24 |
Mar 14 01:14:56 PM PDT 24 |
29082518 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.755818156 |
|
|
Mar 14 01:14:10 PM PDT 24 |
Mar 14 01:14:26 PM PDT 24 |
688883044 ps |
| T968 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1421086210 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
73970437 ps |
| T131 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1008747560 |
|
|
Mar 14 01:14:52 PM PDT 24 |
Mar 14 01:14:56 PM PDT 24 |
79684139 ps |
| T969 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2740601828 |
|
|
Mar 14 01:14:44 PM PDT 24 |
Mar 14 01:14:47 PM PDT 24 |
400815096 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1410698133 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
18638715 ps |
| T971 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1190958078 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
84997082 ps |
| T972 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4083989282 |
|
|
Mar 14 01:14:47 PM PDT 24 |
Mar 14 01:14:48 PM PDT 24 |
64781666 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2003572469 |
|
|
Mar 14 01:14:16 PM PDT 24 |
Mar 14 01:14:18 PM PDT 24 |
66322934 ps |
| T974 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3291478612 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
12462996 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3608359755 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
67753139 ps |
| T215 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3778935498 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
70171564 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2413983198 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
146838381 ps |
| T977 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4007295643 |
|
|
Mar 14 01:14:55 PM PDT 24 |
Mar 14 01:14:57 PM PDT 24 |
143448050 ps |
| T978 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4160169415 |
|
|
Mar 14 01:14:49 PM PDT 24 |
Mar 14 01:14:50 PM PDT 24 |
33622452 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3342318180 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
11588386 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2590390465 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
65631229 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2607520634 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:01 PM PDT 24 |
50947767 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2798978241 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:40 PM PDT 24 |
219638003 ps |
| T983 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.62094849 |
|
|
Mar 14 01:14:38 PM PDT 24 |
Mar 14 01:14:41 PM PDT 24 |
152574191 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.264975071 |
|
|
Mar 14 01:14:55 PM PDT 24 |
Mar 14 01:14:57 PM PDT 24 |
42645137 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2719238389 |
|
|
Mar 14 01:14:37 PM PDT 24 |
Mar 14 01:14:46 PM PDT 24 |
677543553 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.320150356 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:37 PM PDT 24 |
55247706 ps |
| T987 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2470651386 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
94069078 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3014134710 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
34677824 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3602912923 |
|
|
Mar 14 01:14:43 PM PDT 24 |
Mar 14 01:15:03 PM PDT 24 |
935818802 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.100144203 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
263127478 ps |
| T991 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3869493293 |
|
|
Mar 14 01:14:55 PM PDT 24 |
Mar 14 01:14:57 PM PDT 24 |
47988259 ps |
| T146 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1261491481 |
|
|
Mar 14 01:14:35 PM PDT 24 |
Mar 14 01:14:38 PM PDT 24 |
61291182 ps |
| T992 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3510824442 |
|
|
Mar 14 01:14:49 PM PDT 24 |
Mar 14 01:14:51 PM PDT 24 |
50651890 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1512205467 |
|
|
Mar 14 01:14:54 PM PDT 24 |
Mar 14 01:14:56 PM PDT 24 |
238543642 ps |
| T994 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3903453468 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:00 PM PDT 24 |
21404728 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2288917488 |
|
|
Mar 14 01:14:16 PM PDT 24 |
Mar 14 01:14:17 PM PDT 24 |
349457187 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1934505347 |
|
|
Mar 14 01:14:36 PM PDT 24 |
Mar 14 01:14:39 PM PDT 24 |
69748992 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3243405246 |
|
|
Mar 14 01:14:54 PM PDT 24 |
Mar 14 01:14:55 PM PDT 24 |
18330015 ps |
| T998 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2982328952 |
|
|
Mar 14 01:14:51 PM PDT 24 |
Mar 14 01:14:52 PM PDT 24 |
41954353 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4293130498 |
|
|
Mar 14 01:14:15 PM PDT 24 |
Mar 14 01:14:20 PM PDT 24 |
611473897 ps |
| T1000 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1064208881 |
|
|
Mar 14 01:14:58 PM PDT 24 |
Mar 14 01:15:00 PM PDT 24 |
40907699 ps |
| T1001 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.349135157 |
|
|
Mar 14 01:14:45 PM PDT 24 |
Mar 14 01:14:46 PM PDT 24 |
20552041 ps |