Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105686665

1

T1

757

T2

22036

T3

336613

auto[1]

1419903

1

T2

3366

T3

594

T10

8999

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105675797

1

T1

757

T2

21640

T3

336514

auto[1]

1430771

1

T2

3762

T3

693

T10

7664

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7158924	1			T1	103		T2	9279		T3	8125
auto[IdleSt]	23766197	1			T1	654		T2	1546		T3	179589
auto[ClkMuxSt]	36521	1			T3	90		T4	92		T10	68
auto[CntIncrSt]	36203	1			T3	90		T4	92		T10	66
auto[CntProgSt]	1485532	1			T3	1444		T4	184		T10	195
auto[TransCheckSt]	28354	1			T3	69		T4	92		T10	48
auto[TokenHashSt]	43322257	1			T3	1675		T4	7660		T10	297
auto[FlashRmaSt]	29465	1			T3	61		T10	28		T12	64
auto[TokenCheck0St]	13066	1			T3	22		T10	13		T12	25
auto[TokenCheck1St]	9600	1			T3	16		T10	13		T12	13
auto[TransProgSt]	406968	1			T3	197		T10	26		T12	2316
auto[PostTransSt]	13522979	1			T3	136296		T4	17866		T10	9
auto[ScrapSt]	331029	1			T10	6		T15	9		T20	3
auto[EscalateSt]	6577789	1			T2	9363		T3	9533		T10	12549
auto[InvalidSt]	10379686	1			T2	5202		T13	523		T22	1070

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1998	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10379686	1			T2	5202		T13	523		T22	1070
EscalateSt	6577789	1			T2	9363		T3	9533		T10	12549
ScrapSt	331029	1			T10	6		T15	9		T20	3
PostTransSt	13522979	1			T3	136296		T4	17866		T10	9
TransProgSt	406968	1			T3	197		T10	26		T12	2316
TokenCheck1St	9600	1			T3	16		T10	13		T12	13
TokenCheck0St	13066	1			T3	22		T10	13		T12	25
FlashRmaSt	29465	1			T3	61		T10	28		T12	64
TokenHashSt	43322257	1			T3	1675		T4	7660		T10	297
TransCheckSt	28354	1			T3	69		T4	92		T10	48
CntProgSt	1485532	1			T3	1444		T4	184		T10	195
CntIncrSt	36203	1			T3	90		T4	92		T10	66
ClkMuxSt	36521	1			T3	90		T4	92		T10	68
IdleSt	23766197	1			T1	654		T2	1546		T3	179589
ResetSt	7158924	1			T1	103		T2	9279		T3	8125
arcs[ResetSt=>IdleSt]	56088	1			T1	1		T2	87		T3	91
arcs[IdleSt=>ScrapSt]	335	1			T10	2		T15	3		T20	1
arcs[IdleSt=>ClkMuxSt]	36276	1			T3	90		T4	92		T10	68
arcs[ClkMuxSt=>CntIncrSt]	36203	1			T3	90		T4	92		T10	66
arcs[CntIncrSt=>PostTransSt]	1767	1			T3	8		T12	9		T14	15
arcs[CntIncrSt=>CntProgSt]	34381	1			T3	82		T4	92		T10	65
arcs[CntProgSt=>PostTransSt]	4930	1			T3	13		T11	6		T12	11
arcs[CntProgSt=>TransCheckSt]	28354	1			T3	69		T4	92		T10	48
arcs[TransCheckSt=>PostTransSt]	3890	1			T3	11		T12	8		T14	17
arcs[TransCheckSt=>TokenHashSt]	24347	1			T3	58		T4	92		T10	45
arcs[TokenHashSt=>PostTransSt]	10453	1			T3	36		T4	92		T12	45
arcs[TokenHashSt=>FlashRmaSt]	13172	1			T3	22		T10	16		T12	25
arcs[FlashRmaSt=>TokenCheck0St]	13066	1			T3	22		T10	13		T12	25
arcs[TokenCheck0St=>PostTransSt]	3434	1			T3	6		T12	12		T14	8
arcs[TokenCheck0St=>TokenCheck1St]	9600	1			T3	16		T10	13		T12	13
arcs[TokenCheck1St=>PostTransSt]	639	1			T21	1		T49	1		T26	1
arcs[TransProgSt=>PostTransSt]	8055	1			T3	16		T10	4		T12	13
arcs[IdleSt=>EscalateSt]	154	1			T44	8		T45	10		T46	1
arcs[ClkMuxSt=>EscalateSt]	73	1			T10	2		T20	1		T42	2
arcs[CntIncrSt=>EscalateSt]	55	1			T10	1		T20	2		T43	3
arcs[CntProgSt=>EscalateSt]	1097	1			T10	17		T15	6		T20	8
arcs[TransCheckSt=>EscalateSt]	117	1			T10	3		T15	7		T20	3
arcs[TokenHashSt=>EscalateSt]	722	1			T10	29		T15	16		T20	19
arcs[FlashRmaSt=>EscalateSt]	106	1			T10	3		T15	2		T20	3
arcs[TokenCheck0St=>EscalateSt]	32	1			T15	1		T20	1		T45	1
arcs[TokenCheck1St=>EscalateSt]	158	1			T10	1		T15	2		T20	3
arcs[TransProgSt=>EscalateSt]	748	1			T10	8		T15	5		T20	6
arcs[PostTransSt=>EscalateSt]	5153	1			T3	13		T10	4		T11	6
arcs[InvalidSt=>EscalateSt]	14447	1			T2	72		T13	4		T22	14

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7158740	1			T1	103		T2	9279		T3	8125
auto[0]	auto[IdleSt]	23766081	1			T1	654		T2	1546		T3	179589
auto[0]	auto[ClkMuxSt]	36473	1			T3	90		T4	92		T10	66
auto[0]	auto[CntIncrSt]	36168	1			T3	90		T4	92		T10	65
auto[0]	auto[CntProgSt]	1484815	1			T3	1444		T4	184		T10	184
auto[0]	auto[TransCheckSt]	28273	1			T3	69		T4	92		T10	45
auto[0]	auto[TokenHashSt]	43321784	1			T3	1675		T4	7660		T10	279
auto[0]	auto[FlashRmaSt]	29392	1			T3	61		T10	25		T12	64
auto[0]	auto[TokenCheck0St]	13048	1			T3	22		T10	13		T12	25
auto[0]	auto[TokenCheck1St]	9499	1			T3	16		T10	12		T12	13
auto[0]	auto[TransProgSt]	406470	1			T3	197		T10	22		T12	2316
auto[0]	auto[PostTransSt]	13520391	1			T3	136290		T4	17866		T10	5
auto[0]	auto[ScrapSt]	330981	1			T10	6		T15	7		T20	2
auto[0]	auto[EscalateSt]	5170087	1			T2	6031		T3	8945		T10	3603
auto[0]	auto[InvalidSt]	10372465	1			T2	5168		T13	521		T22	1062
auto[1]	auto[ResetSt]	184	1			T10	6		T15	2		T20	2
auto[1]	auto[IdleSt]	116	1			T44	7		T45	8		T46	1
auto[1]	auto[ClkMuxSt]	48	1			T10	2		T20	1		T42	1
auto[1]	auto[CntIncrSt]	35	1			T10	1		T43	2		T44	1
auto[1]	auto[CntProgSt]	717	1			T10	11		T15	5		T20	4
auto[1]	auto[TransCheckSt]	81	1			T10	3		T15	4		T20	2
auto[1]	auto[TokenHashSt]	473	1			T10	18		T15	13		T20	15
auto[1]	auto[FlashRmaSt]	73	1			T10	3		T15	2		T20	3
auto[1]	auto[TokenCheck0St]	18	1			T20	1		T45	1		T252	1
auto[1]	auto[TokenCheck1St]	101	1			T10	1		T15	1		T20	3
auto[1]	auto[TransProgSt]	498	1			T10	4		T15	3		T20	5
auto[1]	auto[PostTransSt]	2588	1			T3	6		T10	4		T11	3
auto[1]	auto[ScrapSt]	48	1			T15	2		T20	1		T43	2
auto[1]	auto[EscalateSt]	1407702	1			T2	3332		T3	588		T10	8946
auto[1]	auto[InvalidSt]	7221	1			T2	34		T13	2		T22	8

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7158748	1			T1	103		T2	9279		T3	8125
auto[0]	auto[IdleSt]	23766099	1			T1	654		T2	1546		T3	179589
auto[0]	auto[ClkMuxSt]	36476	1			T3	90		T4	92		T10	68
auto[0]	auto[CntIncrSt]	36161	1			T3	90		T4	92		T10	65
auto[0]	auto[CntProgSt]	1484794	1			T3	1444		T4	184		T10	184
auto[0]	auto[TransCheckSt]	28280	1			T3	69		T4	92		T10	46
auto[0]	auto[TokenHashSt]	43321770	1			T3	1675		T4	7660		T10	278
auto[0]	auto[FlashRmaSt]	29393	1			T3	61		T10	26		T12	64
auto[0]	auto[TokenCheck0St]	13043	1			T3	22		T10	13		T12	25
auto[0]	auto[TokenCheck1St]	9484	1			T3	16		T10	13		T12	13
auto[0]	auto[TransProgSt]	406461	1			T3	197		T10	20		T12	2316
auto[0]	auto[PostTransSt]	13520338	1			T3	136289		T4	17866		T10	7
auto[0]	auto[ScrapSt]	330989	1			T10	4		T15	6		T20	3
auto[0]	auto[EscalateSt]	5159303	1			T2	5639		T3	8847		T10	4933
auto[0]	auto[InvalidSt]	10372460	1			T2	5164		T13	521		T22	1064
auto[1]	auto[ResetSt]	176	1			T10	3		T15	2		T20	2
auto[1]	auto[IdleSt]	98	1			T44	4		T45	4		T91	2
auto[1]	auto[ClkMuxSt]	45	1			T42	1		T252	1		T91	2
auto[1]	auto[CntIncrSt]	42	1			T10	1		T20	2		T43	3
auto[1]	auto[CntProgSt]	738	1			T10	11		T15	3		T20	5
auto[1]	auto[TransCheckSt]	74	1			T10	2		T15	6		T20	3
auto[1]	auto[TokenHashSt]	487	1			T10	19		T15	8		T20	9
auto[1]	auto[FlashRmaSt]	72	1			T10	2		T43	1		T44	1
auto[1]	auto[TokenCheck0St]	23	1			T15	1		T20	1		T45	1
auto[1]	auto[TokenCheck1St]	116	1			T15	2		T20	3		T43	3
auto[1]	auto[TransProgSt]	507	1			T10	6		T15	3		T20	2
auto[1]	auto[PostTransSt]	2641	1			T3	7		T10	2		T11	3
auto[1]	auto[ScrapSt]	40	1			T10	2		T15	3		T84	1
auto[1]	auto[EscalateSt]	1418486	1			T2	3724		T3	686		T10	7616
auto[1]	auto[InvalidSt]	7226	1			T2	38		T13	2		T22	6