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LINE 58
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T118,T119 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 70
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T82,T47,T85 |
| 1 | 0 | Covered | T117,T121,T122 |
LINE 77
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T82,T47,T85 |
| 0 | 1 | 0 | Covered | T117,T121,T122 |
| 1 | 0 | 0 | Covered | T82,T47,T85 |
LINE 119
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T117,T121,T122 |
| 0 | 1 | 0 | Covered | T120,T118,T119 |
| 1 | 0 | 0 | Covered | T118,T119,T123 |
LINE 499
EXPRESSION (claim_transition_if_we & claim_transition_if_regwen_qs)
-----------1---------- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T124,T125 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 538
EXPRESSION (transition_cmd_we & transition_regwen_qs)
--------1-------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T2,T10,T13 |
| 1 | 1 | Covered | T3,T4,T10 |
LINE 561
EXPRESSION (transition_ctrl_we & transition_regwen_qs)
---------1-------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T5,T7,T26 |
| 1 | 1 | Covered | T5,T81,T71 |
LINE 602
EXPRESSION (transition_token_0_we & transition_regwen_qs)
----------1---------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T3,T5 |
LINE 626
EXPRESSION (transition_token_1_we & transition_regwen_qs)
----------1---------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T3,T5 |
LINE 650
EXPRESSION (transition_token_2_we & transition_regwen_qs)
----------1---------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T3,T5,T4 |
LINE 674
EXPRESSION (transition_token_3_we & transition_regwen_qs)
----------1---------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T3,T5,T4 |
LINE 697
EXPRESSION (transition_target_we & transition_regwen_qs)
----------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T3,T5 |
LINE 720
EXPRESSION (otp_vendor_test_ctrl_we & transition_regwen_qs)
-----------1----------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T3,T5,T4 |
LINE 1141
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_ALERT_TEST_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T9,T10 |
LINE 1142
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_STATUS_OFFSET)
--------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1143
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_CLAIM_TRANSITION_IF_REGWEN_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T10,T12 |
LINE 1144
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_CLAIM_TRANSITION_IF_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1145
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_REGWEN_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T10 |
LINE 1146
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_CMD_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1147
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_CTRL_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T10 |
LINE 1148
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T5 |
LINE 1149
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T5 |
LINE 1150
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_2_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T5 |
LINE 1151
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_3_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T5 |
LINE 1152
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TARGET_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1153
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_OTP_VENDOR_TEST_CTRL_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T5 |
LINE 1154
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_OTP_VENDOR_TEST_STATUS_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1155
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_STATE_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1156
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_TRANSITION_CNT_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1157
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_ID_STATE_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T10,T12 |
LINE 1158
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_HW_REVISION0_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1159
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_HW_REVISION1_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1160
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_0_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1161
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_1_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1162
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_2_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1163
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_3_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1164
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_4_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1165
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_5_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1166
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_6_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1167
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_7_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1168
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_0_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1169
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_1_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1170
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_2_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1171
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_3_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1172
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_4_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1173
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_5_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1174
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_6_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1175
EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_7_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 1178
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1178
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 1182
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T120,T117,T118 |
LINE 1182
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b1111 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|
| ALL ZEROS | Covered | T1,T2,T3 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T2,T3,T10 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T2,T3,T10 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T10,T12,T13 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T10,T11,T12 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T3,T10,T11 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T3,T10,T11 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T3,T10,T12 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T3,T10,T12 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T2,T4,T10 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T2,T10,T11 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T10,T12,T14 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T2,T3,T4 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T2,T3,T4 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T2,T3,T10 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T2,T10,T11 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T2,T3,T10 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T2,T3,T4 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T2,T4,T10 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T3,T10,T12 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T2,T3,T4 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T2,T3,T4 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T1,T2,T4 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T3,T5,T10 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T1,T5,T10 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T3,T5,T10 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T5,T10,T12 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T3,T5,T10 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T5,T10,T12 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T5,T10,T12 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T3,T10,T12 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T5,T10,T12 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T1,T2,T5 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T3,T10,T12 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T2,T4,T10 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T3,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T9,T10 |
| 1 | 1 | Covered | T3,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T4,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T10,T12 |
| 1 | 1 | Covered | T3,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T5 |
LINE 1182
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T5,T10 |
| 1 | 1 | Covered | T5,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T3,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T5,T10 |
| 1 | 1 | Covered | T5,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T5,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T3,T5,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T5,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T3,T5,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T1,T5,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T3,T5,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 1182
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 1182
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 1182
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T12,T14 |
| 1 | 1 | Covered | T3,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T10,T12 |
| 1 | 1 | Covered | T2,T4,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T10,T11 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 1182
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T10 |
| 1 | 1 | Covered | T2,T3,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T10 |
| 1 | 1 | Covered | T2,T10,T11 |
LINE 1182
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T10 |
| 1 | 1 | Covered | T2,T3,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T11,T12 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 1182
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T10,T11 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 1182
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T10,T12,T14 |
LINE 1182
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T10 |
| 1 | 1 | Covered | T2,T10,T11 |
LINE 1182
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T10,T11 |
| 1 | 1 | Covered | T2,T4,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T3,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T3,T10,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T3,T10,T11 |
LINE 1182
SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T3,T10,T11 |
LINE 1182
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T10,T11,T12 |
LINE 1182
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T10,T12,T13 |
LINE 1182
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T10 |
| 1 | 1 | Covered | T2,T3,T10 |
LINE 1182
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T10 |
| 1 | 1 | Covered | T2,T3,T10 |
LINE 1221
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T9,T10 |
| 1 | 1 | 0 | Covered | T118,T119,T123 |
| 1 | 1 | 1 | Covered | T9,T34,T86 |
LINE 1228
EXPRESSION (addr_hit[1] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T126 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1229
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T10,T12 |
| 1 | 1 | 0 | Covered | T118,T119,T127 |
| 1 | 1 | 1 | Covered | T120,T117,T128 |
LINE 1232
EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T129,T130,T131 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1233
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T118,T119,T132 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1236
EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T5,T10 |
| 1 | 1 | 0 | Covered | T121,T133,T134 |
| 1 | 1 | 1 | Covered | T1,T5,T7 |
LINE 1237
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T118,T127,T135 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1240
EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T5,T10 |
| 1 | 1 | 0 | Covered | T117,T122,T126 |
| 1 | 1 | 1 | Covered | T5,T81,T7 |
LINE 1241
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T5,T10 |
| 1 | 1 | 0 | Covered | T118,T119,T127 |
| 1 | 1 | 1 | Covered | T5,T81,T71 |
LINE 1246
EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T136 |
| 1 | 1 | 1 | Covered | T5,T7,T26 |
LINE 1247
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T118,T119,T127 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 1250
EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T134,T137,T138 |
| 1 | 1 | 1 | Covered | T5,T7,T26 |
LINE 1251
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T118,T119,T127 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 1254
EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T117,T129,T134 |
| 1 | 1 | 1 | Covered | T5,T7,T26 |
LINE 1255
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T118,T119,T132 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 1258
EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T121,T139 |
| 1 | 1 | 1 | Covered | T5,T7,T26 |
LINE 1259
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T118,T119,T127 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 1262
EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T5,T7,T26 |
LINE 1263
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T120,T118,T123 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 1266
EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T140 |
| 1 | 1 | 1 | Covered | T5,T7,T26 |
LINE 1267
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T5 |
| 1 | 1 | 0 | Covered | T118,T127,T141 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 1270
EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T134 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1271
EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T117,T142,T131 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1272
EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T143,T133,T137 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1273
EXPRESSION (addr_hit[16] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T10,T12 |
| 1 | 1 | 0 | Covered | T144,T145,T146 |
| 1 | 1 | 1 | Not Covered | |
LINE 1274
EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T147,T148,T149 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1275
EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T130,T150 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1276
EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T122,T151,T147 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1277
EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T142,T152 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1278
EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T136,T131 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1279
EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T145,T146,T153 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1280
EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T117,T154,T155 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1281
EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T145,T155,T156 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1282
EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T149,T156,T157 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1283
EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T158,T143,T130 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1284
EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T154 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1285
EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T140,T129,T137 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1286
EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T140,T152 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1287
EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T117,T159,T148 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1288
EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T158,T133,T138 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 1289
EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T139,T156,T138 |
| 1 | 1 | 1 | Covered | T2,T3,T4 |