Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

192606840

1

T1

7451

T2

8627

T3

16293

auto[1]

2702298

1

T1

693

T2

99

T4

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

192619867

1

T1

7451

T2

8429

T3

16293

auto[1]

2689271

1

T1

693

T2

297

T4

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	13905591	1			T1	2045		T2	1856		T3	70
auto[IdleSt]	42235668	1			T1	2588		T2	1703		T3	16223
auto[ClkMuxSt]	68787	1			T1	14		T2	9		T4	74
auto[CntIncrSt]	68233	1			T1	14		T2	9		T4	74
auto[CntProgSt]	3249948	1			T1	461		T2	18		T4	425
auto[TransCheckSt]	53630	1			T2	9		T4	57		T5	7
auto[TokenHashSt]	74637904	1			T2	410		T4	2706		T5	77978
auto[FlashRmaSt]	55578	1			T2	9		T4	29		T5	7
auto[TokenCheck0St]	24431	1			T2	9		T4	19		T5	7
auto[TokenCheck1St]	17990	1			T2	9		T4	10		T5	7
auto[TransProgSt]	835115	1			T2	18		T4	66		T5	14
auto[PostTransSt]	25600880	1			T1	1157		T2	2728		T4	69578
auto[ScrapSt]	427943	1			T5	3515		T11	3		T20	889
auto[EscalateSt]	12925045	1			T1	1865		T2	1115		T4	3752
auto[InvalidSt]	21198611	1			T2	824		T14	73492		T15	647574

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3784	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	21198611	1			T2	824		T14	73492		T15	647574
EscalateSt	12925045	1			T1	1865		T2	1115		T4	3752
ScrapSt	427943	1			T5	3515		T11	3		T20	889
PostTransSt	25600880	1			T1	1157		T2	2728		T4	69578
TransProgSt	835115	1			T2	18		T4	66		T5	14
TokenCheck1St	17990	1			T2	9		T4	10		T5	7
TokenCheck0St	24431	1			T2	9		T4	19		T5	7
FlashRmaSt	55578	1			T2	9		T4	29		T5	7
TokenHashSt	74637904	1			T2	410		T4	2706		T5	77978
TransCheckSt	53630	1			T2	9		T4	57		T5	7
CntProgSt	3249948	1			T1	461		T2	18		T4	425
CntIncrSt	68233	1			T1	14		T2	9		T4	74
ClkMuxSt	68787	1			T1	14		T2	9		T4	74
IdleSt	42235668	1			T1	2588		T2	1703		T3	16223
ResetSt	13905591	1			T1	2045		T2	1856		T3	70
arcs[ResetSt=>IdleSt]	104425	1			T1	15		T2	14		T3	1
arcs[IdleSt=>ScrapSt]	546	1			T5	1		T11	1		T20	1
arcs[IdleSt=>ClkMuxSt]	68357	1			T1	14		T2	9		T4	74
arcs[ClkMuxSt=>CntIncrSt]	68233	1			T1	14		T2	9		T4	74
arcs[CntIncrSt=>PostTransSt]	3120	1			T4	9		T13	4		T14	7
arcs[CntIncrSt=>CntProgSt]	64989	1			T1	14		T2	9		T4	65
arcs[CntProgSt=>PostTransSt]	9405	1			T1	14		T4	8		T9	7
arcs[CntProgSt=>TransCheckSt]	53630	1			T2	9		T4	57		T5	7
arcs[TransCheckSt=>PostTransSt]	7199	1			T4	10		T19	38		T13	9
arcs[TransCheckSt=>TokenHashSt]	46163	1			T2	9		T4	47		T5	7
arcs[TokenHashSt=>PostTransSt]	20157	1			T4	28		T10	1		T19	12
arcs[TokenHashSt=>FlashRmaSt]	24638	1			T2	9		T4	19		T5	7
arcs[FlashRmaSt=>TokenCheck0St]	24431	1			T2	9		T4	19		T5	7
arcs[TokenCheck0St=>PostTransSt]	6391	1			T4	9		T19	24		T13	8
arcs[TokenCheck0St=>TokenCheck1St]	17990	1			T2	9		T4	10		T5	7
arcs[TokenCheck1St=>PostTransSt]	1273	1			T19	9		T15	3		T25	2
arcs[TransProgSt=>PostTransSt]	15037	1			T2	9		T4	10		T5	7
arcs[IdleSt=>EscalateSt]	407	1			T11	11		T45	9		T46	4
arcs[ClkMuxSt=>EscalateSt]	124	1			T45	1		T46	3		T47	2
arcs[CntIncrSt=>EscalateSt]	124	1			T11	1		T24	1		T47	1
arcs[CntProgSt=>EscalateSt]	1954	1			T11	11		T24	30		T45	21
arcs[TransCheckSt=>EscalateSt]	268	1			T11	5		T46	7		T47	1
arcs[TokenHashSt=>EscalateSt]	1368	1			T11	18		T24	10		T39	3
arcs[FlashRmaSt=>EscalateSt]	207	1			T11	5		T24	2		T45	2
arcs[TokenCheck0St=>EscalateSt]	50	1			T45	1		T47	2		T51	1
arcs[TokenCheck1St=>EscalateSt]	300	1			T11	2		T24	1		T45	3
arcs[TransProgSt=>EscalateSt]	1380	1			T11	11		T24	15		T45	8
arcs[PostTransSt=>EscalateSt]	9912	1			T1	14		T4	8		T9	7
arcs[InvalidSt=>EscalateSt]	26931	1			T2	4		T14	76		T15	333

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13905283	1			T1	2045		T2	1856		T3	70
auto[0]	auto[IdleSt]	42235408	1			T1	2588		T2	1703		T3	16223
auto[0]	auto[ClkMuxSt]	68698	1			T1	14		T2	9		T4	74
auto[0]	auto[CntIncrSt]	68161	1			T1	14		T2	9		T4	74
auto[0]	auto[CntProgSt]	3248646	1			T1	461		T2	18		T4	425
auto[0]	auto[TransCheckSt]	53445	1			T2	9		T4	57		T5	7
auto[0]	auto[TokenHashSt]	74637009	1			T2	410		T4	2706		T5	77978
auto[0]	auto[FlashRmaSt]	55427	1			T2	9		T4	29		T5	7
auto[0]	auto[TokenCheck0St]	24400	1			T2	9		T4	19		T5	7
auto[0]	auto[TokenCheck1St]	17801	1			T2	9		T4	10		T5	7
auto[0]	auto[TransProgSt]	834212	1			T2	18		T4	66		T5	14
auto[0]	auto[PostTransSt]	25595819	1			T1	1150		T2	2728		T4	69574
auto[0]	auto[ScrapSt]	427857	1			T5	3515		T11	3		T20	889
auto[0]	auto[EscalateSt]	10245852	1			T1	1179		T2	1017		T4	3360
auto[0]	auto[InvalidSt]	21185038	1			T2	823		T14	73446		T15	647398
auto[1]	auto[ResetSt]	308	1			T11	5		T24	6		T45	4
auto[1]	auto[IdleSt]	260	1			T11	8		T45	6		T46	3
auto[1]	auto[ClkMuxSt]	89	1			T45	1		T46	2		T47	1
auto[1]	auto[CntIncrSt]	72	1			T24	1		T47	1		T245	1
auto[1]	auto[CntProgSt]	1302	1			T11	4		T24	20		T45	14
auto[1]	auto[TransCheckSt]	185	1			T11	3		T46	4		T47	1
auto[1]	auto[TokenHashSt]	895	1			T11	9		T24	6		T39	1
auto[1]	auto[FlashRmaSt]	151	1			T11	3		T24	2		T45	2
auto[1]	auto[TokenCheck0St]	31	1			T47	1		T51	1		T246	1
auto[1]	auto[TokenCheck1St]	189	1			T11	1		T45	2		T46	5
auto[1]	auto[TransProgSt]	903	1			T11	7		T24	13		T45	3
auto[1]	auto[PostTransSt]	5061	1			T1	7		T4	4		T9	4
auto[1]	auto[ScrapSt]	86	1			T46	1		T47	1		T179	2
auto[1]	auto[EscalateSt]	2679193	1			T1	686		T2	98		T4	392
auto[1]	auto[InvalidSt]	13573	1			T2	1		T14	46		T15	176

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13905271	1			T1	2045		T2	1856		T3	70
auto[0]	auto[IdleSt]	42235397	1			T1	2588		T2	1703		T3	16223
auto[0]	auto[ClkMuxSt]	68704	1			T1	14		T2	9		T4	74
auto[0]	auto[CntIncrSt]	68149	1			T1	14		T2	9		T4	74
auto[0]	auto[CntProgSt]	3248626	1			T1	461		T2	18		T4	425
auto[0]	auto[TransCheckSt]	53445	1			T2	9		T4	57		T5	7
auto[0]	auto[TokenHashSt]	74636983	1			T2	410		T4	2706		T5	77978
auto[0]	auto[FlashRmaSt]	55453	1			T2	9		T4	29		T5	7
auto[0]	auto[TokenCheck0St]	24401	1			T2	9		T4	19		T5	7
auto[0]	auto[TokenCheck1St]	17791	1			T2	9		T4	10		T5	7
auto[0]	auto[TransProgSt]	834203	1			T2	18		T4	66		T5	14
auto[0]	auto[PostTransSt]	25595857	1			T1	1150		T2	2728		T4	69574
auto[0]	auto[ScrapSt]	427877	1			T5	3515		T11	2		T20	889
auto[0]	auto[EscalateSt]	10258673	1			T1	1179		T2	821		T4	3360
auto[0]	auto[InvalidSt]	21185253	1			T2	821		T14	73462		T15	647417
auto[1]	auto[ResetSt]	320	1			T11	1		T24	7		T45	3
auto[1]	auto[IdleSt]	271	1			T11	7		T45	6		T46	3
auto[1]	auto[ClkMuxSt]	83	1			T45	1		T46	2		T47	1
auto[1]	auto[CntIncrSt]	84	1			T11	1		T247	1		T248	2
auto[1]	auto[CntProgSt]	1322	1			T11	9		T24	18		T45	16
auto[1]	auto[TransCheckSt]	185	1			T11	2		T46	3		T47	1
auto[1]	auto[TokenHashSt]	921	1			T11	13		T24	8		T39	2
auto[1]	auto[FlashRmaSt]	125	1			T11	3		T24	1		T45	2
auto[1]	auto[TokenCheck0St]	30	1			T45	1		T47	1		T249	1
auto[1]	auto[TokenCheck1St]	199	1			T11	2		T24	1		T45	1
auto[1]	auto[TransProgSt]	912	1			T11	6		T24	8		T45	7
auto[1]	auto[PostTransSt]	5023	1			T1	7		T4	4		T9	3
auto[1]	auto[ScrapSt]	66	1			T11	1		T46	1		T47	1
auto[1]	auto[EscalateSt]	2666372	1			T1	686		T2	294		T4	392
auto[1]	auto[InvalidSt]	13358	1			T2	3		T14	30		T15	157