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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 97.82 96.21 93.31 100.00 98.52 98.76 96.43


Total test records in report: 1994
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T1780 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2255252348 Mar 19 02:48:21 PM PDT 24 Mar 19 02:48:23 PM PDT 24 88055529 ps
T1781 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1545644725 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:43 PM PDT 24 23833476 ps
T1782 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1527083761 Mar 19 03:13:57 PM PDT 24 Mar 19 03:14:05 PM PDT 24 1836935534 ps
T1783 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2395930709 Mar 19 03:13:49 PM PDT 24 Mar 19 03:13:54 PM PDT 24 286431060 ps
T1784 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1696812245 Mar 19 02:48:14 PM PDT 24 Mar 19 02:48:35 PM PDT 24 2404278151 ps
T159 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1758345230 Mar 19 02:48:58 PM PDT 24 Mar 19 02:49:01 PM PDT 24 364626509 ps
T1785 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1754864007 Mar 19 03:14:27 PM PDT 24 Mar 19 03:14:28 PM PDT 24 197179264 ps
T1786 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.176030566 Mar 19 02:48:27 PM PDT 24 Mar 19 02:48:30 PM PDT 24 79270029 ps
T1787 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3173013717 Mar 19 03:14:38 PM PDT 24 Mar 19 03:14:39 PM PDT 24 22383352 ps
T1788 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2682558134 Mar 19 03:13:57 PM PDT 24 Mar 19 03:13:59 PM PDT 24 36972761 ps
T1789 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2493021531 Mar 19 03:14:31 PM PDT 24 Mar 19 03:14:34 PM PDT 24 384244653 ps
T1790 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.539683602 Mar 19 03:14:13 PM PDT 24 Mar 19 03:14:14 PM PDT 24 38799690 ps
T1791 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1021415150 Mar 19 02:48:18 PM PDT 24 Mar 19 02:48:23 PM PDT 24 311893010 ps
T1792 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1624063957 Mar 19 02:48:30 PM PDT 24 Mar 19 02:48:35 PM PDT 24 501914529 ps
T1793 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.525534134 Mar 19 03:13:56 PM PDT 24 Mar 19 03:13:58 PM PDT 24 41330849 ps
T1794 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4077952414 Mar 19 02:48:32 PM PDT 24 Mar 19 02:48:33 PM PDT 24 92538050 ps
T1795 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2070594480 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:27 PM PDT 24 380277523 ps
T1796 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.308070376 Mar 19 02:48:16 PM PDT 24 Mar 19 02:48:18 PM PDT 24 148454657 ps
T1797 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1942849495 Mar 19 02:48:24 PM PDT 24 Mar 19 02:48:26 PM PDT 24 182703606 ps
T1798 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.184958271 Mar 19 03:14:01 PM PDT 24 Mar 19 03:14:03 PM PDT 24 30451090 ps
T1799 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2479572976 Mar 19 03:13:59 PM PDT 24 Mar 19 03:14:01 PM PDT 24 347281409 ps
T1800 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1832541689 Mar 19 02:48:31 PM PDT 24 Mar 19 02:48:32 PM PDT 24 24862250 ps
T1801 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1835802324 Mar 19 03:14:11 PM PDT 24 Mar 19 03:14:13 PM PDT 24 534544931 ps
T1802 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2841802489 Mar 19 03:13:47 PM PDT 24 Mar 19 03:14:08 PM PDT 24 3730004692 ps
T1803 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.740534248 Mar 19 03:14:09 PM PDT 24 Mar 19 03:14:10 PM PDT 24 143447433 ps
T1804 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1252247342 Mar 19 02:48:20 PM PDT 24 Mar 19 02:48:22 PM PDT 24 68105884 ps
T1805 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3498671396 Mar 19 02:48:46 PM PDT 24 Mar 19 02:48:47 PM PDT 24 24382893 ps
T1806 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2641456616 Mar 19 02:48:24 PM PDT 24 Mar 19 02:48:27 PM PDT 24 790604811 ps
T1807 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2050922594 Mar 19 03:14:20 PM PDT 24 Mar 19 03:14:22 PM PDT 24 67601642 ps
T146 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2299281759 Mar 19 02:48:33 PM PDT 24 Mar 19 02:48:36 PM PDT 24 310741667 ps
T154 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2844557011 Mar 19 03:13:57 PM PDT 24 Mar 19 03:14:00 PM PDT 24 106645794 ps
T1808 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2275371298 Mar 19 03:14:19 PM PDT 24 Mar 19 03:14:21 PM PDT 24 309543736 ps
T1809 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1527317903 Mar 19 03:14:21 PM PDT 24 Mar 19 03:14:24 PM PDT 24 104346400 ps
T132 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3414839666 Mar 19 02:48:33 PM PDT 24 Mar 19 02:48:36 PM PDT 24 291958135 ps
T1810 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1417267403 Mar 19 03:14:10 PM PDT 24 Mar 19 03:14:12 PM PDT 24 92356178 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1409116549 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:29 PM PDT 24 104518866 ps
T216 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4073003959 Mar 19 03:14:38 PM PDT 24 Mar 19 03:14:39 PM PDT 24 41126181 ps
T1811 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3830881244 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:33 PM PDT 24 270368601 ps
T217 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1425825352 Mar 19 02:48:14 PM PDT 24 Mar 19 02:48:16 PM PDT 24 103277578 ps
T1812 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2900370719 Mar 19 02:48:36 PM PDT 24 Mar 19 02:48:37 PM PDT 24 320228779 ps
T1813 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.284234705 Mar 19 03:14:39 PM PDT 24 Mar 19 03:14:40 PM PDT 24 25682582 ps
T1814 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.854662745 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:43 PM PDT 24 144084161 ps
T1815 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2927099802 Mar 19 02:48:24 PM PDT 24 Mar 19 02:48:25 PM PDT 24 338650729 ps
T1816 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2093290917 Mar 19 02:48:32 PM PDT 24 Mar 19 02:48:33 PM PDT 24 73394439 ps
T1817 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.671176624 Mar 19 02:48:30 PM PDT 24 Mar 19 02:48:31 PM PDT 24 88672199 ps
T1818 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4225292204 Mar 19 03:14:39 PM PDT 24 Mar 19 03:14:40 PM PDT 24 50162447 ps
T219 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.778270417 Mar 19 02:48:33 PM PDT 24 Mar 19 02:48:39 PM PDT 24 17876833 ps
T1819 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4011655095 Mar 19 03:13:57 PM PDT 24 Mar 19 03:13:58 PM PDT 24 26712998 ps
T1820 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2642397706 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:26 PM PDT 24 136328412 ps
T1821 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4066103714 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:28 PM PDT 24 546365532 ps
T1822 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.696467691 Mar 19 02:48:38 PM PDT 24 Mar 19 02:48:39 PM PDT 24 55186391 ps
T141 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4170355787 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:32 PM PDT 24 484296475 ps
T1823 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.569283500 Mar 19 03:14:31 PM PDT 24 Mar 19 03:14:32 PM PDT 24 37242018 ps
T1824 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1594259704 Mar 19 02:48:21 PM PDT 24 Mar 19 02:48:23 PM PDT 24 23840437 ps
T218 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.786101500 Mar 19 03:14:42 PM PDT 24 Mar 19 03:14:43 PM PDT 24 13152629 ps
T1825 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3205735446 Mar 19 03:14:31 PM PDT 24 Mar 19 03:14:32 PM PDT 24 77705522 ps
T1826 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1262987492 Mar 19 03:14:40 PM PDT 24 Mar 19 03:14:43 PM PDT 24 39550080 ps
T1827 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.29112223 Mar 19 03:14:28 PM PDT 24 Mar 19 03:14:30 PM PDT 24 59581820 ps
T1828 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.210887064 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:36 PM PDT 24 274382536 ps
T1829 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2539891398 Mar 19 02:48:21 PM PDT 24 Mar 19 02:48:22 PM PDT 24 40455563 ps
T1830 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.437173451 Mar 19 02:48:42 PM PDT 24 Mar 19 02:48:43 PM PDT 24 225679092 ps
T1831 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2040938197 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:42 PM PDT 24 73324448 ps
T1832 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3197147017 Mar 19 03:14:09 PM PDT 24 Mar 19 03:14:11 PM PDT 24 1053063142 ps
T1833 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3453090208 Mar 19 03:14:17 PM PDT 24 Mar 19 03:14:20 PM PDT 24 49771234 ps
T1834 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.530973328 Mar 19 03:13:47 PM PDT 24 Mar 19 03:13:49 PM PDT 24 175468573 ps
T1835 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3973347359 Mar 19 03:14:30 PM PDT 24 Mar 19 03:14:42 PM PDT 24 430575875 ps
T1836 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.68986148 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:31 PM PDT 24 102880801 ps
T1837 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.68423483 Mar 19 02:48:38 PM PDT 24 Mar 19 02:48:40 PM PDT 24 23030569 ps
T1838 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1581453910 Mar 19 02:48:20 PM PDT 24 Mar 19 02:48:23 PM PDT 24 497627105 ps
T1839 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.147334932 Mar 19 03:14:09 PM PDT 24 Mar 19 03:14:11 PM PDT 24 46960688 ps
T1840 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3517088765 Mar 19 02:48:23 PM PDT 24 Mar 19 02:48:24 PM PDT 24 40206417 ps
T152 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1547664236 Mar 19 03:14:40 PM PDT 24 Mar 19 03:14:43 PM PDT 24 286533781 ps
T1841 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.132778963 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:44 PM PDT 24 34884163 ps
T138 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2857622229 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:28 PM PDT 24 68882554 ps
T1842 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2506656658 Mar 19 02:48:54 PM PDT 24 Mar 19 02:48:55 PM PDT 24 19487872 ps
T1843 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2146311230 Mar 19 02:48:31 PM PDT 24 Mar 19 02:48:32 PM PDT 24 17583300 ps
T1844 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3999382083 Mar 19 02:48:26 PM PDT 24 Mar 19 02:48:28 PM PDT 24 96042652 ps
T149 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.221267900 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:48 PM PDT 24 1098621486 ps
T1845 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1540056575 Mar 19 02:48:18 PM PDT 24 Mar 19 02:48:20 PM PDT 24 45573884 ps
T137 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1214542599 Mar 19 03:14:40 PM PDT 24 Mar 19 03:14:43 PM PDT 24 235388091 ps
T1846 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2567633959 Mar 19 03:14:20 PM PDT 24 Mar 19 03:14:21 PM PDT 24 87339815 ps
T1847 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3456091893 Mar 19 03:14:08 PM PDT 24 Mar 19 03:14:09 PM PDT 24 13742973 ps
T1848 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.520818619 Mar 19 02:48:18 PM PDT 24 Mar 19 02:48:21 PM PDT 24 123594854 ps
T1849 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2663586421 Mar 19 02:48:33 PM PDT 24 Mar 19 02:48:34 PM PDT 24 46595812 ps
T1850 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3869831024 Mar 19 03:14:24 PM PDT 24 Mar 19 03:14:32 PM PDT 24 684324837 ps
T1851 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.720603867 Mar 19 03:14:19 PM PDT 24 Mar 19 03:14:24 PM PDT 24 554038832 ps
T1852 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.52672799 Mar 19 03:14:12 PM PDT 24 Mar 19 03:14:13 PM PDT 24 94986120 ps
T1853 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1514667719 Mar 19 02:48:30 PM PDT 24 Mar 19 02:48:34 PM PDT 24 227051885 ps
T1854 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.431790620 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:27 PM PDT 24 768072631 ps
T1855 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4262063971 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:42 PM PDT 24 24138309 ps
T1856 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1680538732 Mar 19 02:48:30 PM PDT 24 Mar 19 02:48:33 PM PDT 24 200603701 ps
T1857 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2506639945 Mar 19 03:13:48 PM PDT 24 Mar 19 03:14:03 PM PDT 24 643717720 ps
T1858 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.204645796 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:33 PM PDT 24 806437767 ps
T1859 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1937117668 Mar 19 02:48:17 PM PDT 24 Mar 19 02:48:20 PM PDT 24 203764218 ps
T1860 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4000502572 Mar 19 03:14:23 PM PDT 24 Mar 19 03:14:26 PM PDT 24 1881341616 ps
T220 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3102151146 Mar 19 03:13:56 PM PDT 24 Mar 19 03:13:57 PM PDT 24 83450490 ps
T1861 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2167588990 Mar 19 02:48:32 PM PDT 24 Mar 19 02:48:33 PM PDT 24 20358513 ps
T1862 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2177952549 Mar 19 03:14:19 PM PDT 24 Mar 19 03:14:21 PM PDT 24 31828605 ps
T1863 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2853205091 Mar 19 02:48:30 PM PDT 24 Mar 19 02:48:34 PM PDT 24 102194291 ps
T1864 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.485515851 Mar 19 02:48:48 PM PDT 24 Mar 19 02:48:50 PM PDT 24 67082590 ps
T1865 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.232154328 Mar 19 02:48:28 PM PDT 24 Mar 19 02:48:30 PM PDT 24 52453588 ps
T1866 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3570298465 Mar 19 03:13:45 PM PDT 24 Mar 19 03:13:50 PM PDT 24 3598118816 ps
T1867 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2018716571 Mar 19 02:48:50 PM PDT 24 Mar 19 02:48:52 PM PDT 24 98564637 ps
T1868 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2119304198 Mar 19 03:13:56 PM PDT 24 Mar 19 03:13:58 PM PDT 24 146156331 ps
T1869 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3380515501 Mar 19 02:48:27 PM PDT 24 Mar 19 02:48:29 PM PDT 24 14794644 ps
T1870 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2994112122 Mar 19 02:48:22 PM PDT 24 Mar 19 02:48:23 PM PDT 24 24868783 ps
T1871 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3525038778 Mar 19 03:14:11 PM PDT 24 Mar 19 03:14:12 PM PDT 24 33111913 ps
T1872 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3513669813 Mar 19 02:48:48 PM PDT 24 Mar 19 02:48:50 PM PDT 24 207628030 ps
T1873 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3360695245 Mar 19 02:48:16 PM PDT 24 Mar 19 02:48:17 PM PDT 24 79098920 ps
T1874 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1166301030 Mar 19 02:48:28 PM PDT 24 Mar 19 02:48:29 PM PDT 24 44699288 ps
T1875 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3232395089 Mar 19 03:13:58 PM PDT 24 Mar 19 03:14:01 PM PDT 24 365237786 ps
T1876 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2407683445 Mar 19 02:48:32 PM PDT 24 Mar 19 02:48:35 PM PDT 24 34286308 ps
T1877 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2375372059 Mar 19 03:14:28 PM PDT 24 Mar 19 03:14:35 PM PDT 24 1349530550 ps
T1878 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2378782645 Mar 19 03:14:17 PM PDT 24 Mar 19 03:14:19 PM PDT 24 190129950 ps
T162 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2650777170 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:28 PM PDT 24 140762689 ps
T1879 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2790413663 Mar 19 02:48:17 PM PDT 24 Mar 19 02:48:18 PM PDT 24 20320226 ps
T1880 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.648784894 Mar 19 03:13:48 PM PDT 24 Mar 19 03:13:49 PM PDT 24 78777019 ps
T1881 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2886271934 Mar 19 02:48:26 PM PDT 24 Mar 19 02:48:32 PM PDT 24 12199285 ps
T1882 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3358996836 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:30 PM PDT 24 48191789 ps
T1883 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1241274082 Mar 19 03:13:45 PM PDT 24 Mar 19 03:13:47 PM PDT 24 257765059 ps
T1884 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2686287465 Mar 19 02:48:20 PM PDT 24 Mar 19 02:48:21 PM PDT 24 38242768 ps
T144 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.59320572 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:34 PM PDT 24 222643655 ps
T1885 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.802013540 Mar 19 03:13:45 PM PDT 24 Mar 19 03:13:49 PM PDT 24 1426348886 ps
T147 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3584089307 Mar 19 02:48:44 PM PDT 24 Mar 19 02:48:47 PM PDT 24 114810141 ps
T1886 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2641122318 Mar 19 02:48:38 PM PDT 24 Mar 19 02:48:39 PM PDT 24 48633692 ps
T1887 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3683507970 Mar 19 02:48:29 PM PDT 24 Mar 19 02:48:38 PM PDT 24 844023175 ps
T1888 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3864721173 Mar 19 03:14:39 PM PDT 24 Mar 19 03:14:40 PM PDT 24 26552296 ps
T1889 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2549237210 Mar 19 03:14:19 PM PDT 24 Mar 19 03:14:25 PM PDT 24 1303704851 ps
T139 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3118039175 Mar 19 03:14:27 PM PDT 24 Mar 19 03:14:29 PM PDT 24 54826231 ps
T1890 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2904129078 Mar 19 02:48:22 PM PDT 24 Mar 19 02:48:33 PM PDT 24 1635162324 ps
T1891 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1917413741 Mar 19 02:48:19 PM PDT 24 Mar 19 02:48:21 PM PDT 24 1223871981 ps
T1892 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3868210786 Mar 19 02:48:29 PM PDT 24 Mar 19 02:48:31 PM PDT 24 372151133 ps
T135 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.427513688 Mar 19 02:48:26 PM PDT 24 Mar 19 02:48:30 PM PDT 24 110292753 ps
T1893 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.684343723 Mar 19 03:13:55 PM PDT 24 Mar 19 03:13:57 PM PDT 24 107625092 ps
T1894 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1648673231 Mar 19 03:14:40 PM PDT 24 Mar 19 03:14:42 PM PDT 24 115032590 ps
T1895 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3407100246 Mar 19 03:14:10 PM PDT 24 Mar 19 03:14:14 PM PDT 24 961837051 ps
T1896 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.528240650 Mar 19 03:13:48 PM PDT 24 Mar 19 03:13:49 PM PDT 24 37453385 ps
T1897 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1523132931 Mar 19 02:48:24 PM PDT 24 Mar 19 02:48:25 PM PDT 24 52255364 ps
T1898 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1178917541 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:31 PM PDT 24 317133258 ps
T1899 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3047425157 Mar 19 03:14:10 PM PDT 24 Mar 19 03:14:18 PM PDT 24 352628665 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.694263460 Mar 19 03:14:08 PM PDT 24 Mar 19 03:14:10 PM PDT 24 60920766 ps
T1900 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1489033586 Mar 19 03:14:09 PM PDT 24 Mar 19 03:14:10 PM PDT 24 36314084 ps
T1901 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2604970171 Mar 19 02:48:18 PM PDT 24 Mar 19 02:48:21 PM PDT 24 42241135 ps
T1902 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2023044946 Mar 19 03:14:09 PM PDT 24 Mar 19 03:14:11 PM PDT 24 115310542 ps
T1903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.201904353 Mar 19 02:48:17 PM PDT 24 Mar 19 02:48:22 PM PDT 24 433347705 ps
T1904 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4185092437 Mar 19 02:48:26 PM PDT 24 Mar 19 02:48:28 PM PDT 24 441042526 ps
T1905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2007642386 Mar 19 02:48:20 PM PDT 24 Mar 19 02:48:22 PM PDT 24 36782554 ps
T1906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1180591090 Mar 19 02:48:15 PM PDT 24 Mar 19 02:48:19 PM PDT 24 677140819 ps
T1907 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.207233442 Mar 19 03:14:08 PM PDT 24 Mar 19 03:14:09 PM PDT 24 21096250 ps
T1908 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1358208401 Mar 19 02:48:21 PM PDT 24 Mar 19 02:48:29 PM PDT 24 674871823 ps
T1909 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2555102347 Mar 19 02:48:23 PM PDT 24 Mar 19 02:48:25 PM PDT 24 12737869 ps
T1910 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1240283657 Mar 19 02:48:15 PM PDT 24 Mar 19 02:48:16 PM PDT 24 46827667 ps
T1911 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1418544866 Mar 19 03:14:12 PM PDT 24 Mar 19 03:14:13 PM PDT 24 49443655 ps
T1912 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1671842460 Mar 19 02:48:24 PM PDT 24 Mar 19 02:48:26 PM PDT 24 29560017 ps
T1913 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3329334676 Mar 19 03:14:08 PM PDT 24 Mar 19 03:14:10 PM PDT 24 17005956 ps
T1914 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4086495781 Mar 19 02:48:17 PM PDT 24 Mar 19 02:48:18 PM PDT 24 33633790 ps
T1915 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2486368253 Mar 19 02:48:32 PM PDT 24 Mar 19 02:48:34 PM PDT 24 179026801 ps
T1916 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1382854611 Mar 19 02:48:29 PM PDT 24 Mar 19 02:48:30 PM PDT 24 36252665 ps
T1917 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3382668488 Mar 19 02:48:30 PM PDT 24 Mar 19 02:48:32 PM PDT 24 12827785 ps
T1918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2042116242 Mar 19 03:13:49 PM PDT 24 Mar 19 03:13:51 PM PDT 24 312631776 ps
T1919 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2416516870 Mar 19 03:14:18 PM PDT 24 Mar 19 03:14:20 PM PDT 24 55962886 ps
T1920 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1017370659 Mar 19 02:48:16 PM PDT 24 Mar 19 02:48:21 PM PDT 24 785293224 ps
T1921 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4242108858 Mar 19 03:14:11 PM PDT 24 Mar 19 03:14:12 PM PDT 24 19409189 ps
T1922 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3568420960 Mar 19 03:13:56 PM PDT 24 Mar 19 03:13:57 PM PDT 24 91187646 ps
T1923 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.652966261 Mar 19 02:48:19 PM PDT 24 Mar 19 02:48:20 PM PDT 24 24913160 ps
T1924 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3053230768 Mar 19 02:48:36 PM PDT 24 Mar 19 02:48:37 PM PDT 24 116886962 ps
T1925 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.191149586 Mar 19 02:48:19 PM PDT 24 Mar 19 02:48:22 PM PDT 24 179336060 ps
T1926 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3442362204 Mar 19 03:14:40 PM PDT 24 Mar 19 03:14:43 PM PDT 24 42778613 ps
T1927 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.244580081 Mar 19 03:13:49 PM PDT 24 Mar 19 03:13:54 PM PDT 24 2469804782 ps
T1928 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2193703209 Mar 19 03:14:09 PM PDT 24 Mar 19 03:14:12 PM PDT 24 416143974 ps
T1929 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.860428563 Mar 19 03:14:19 PM PDT 24 Mar 19 03:14:21 PM PDT 24 94930207 ps
T1930 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3820623037 Mar 19 02:48:21 PM PDT 24 Mar 19 02:48:36 PM PDT 24 611293557 ps
T1931 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2100925582 Mar 19 02:48:20 PM PDT 24 Mar 19 02:48:37 PM PDT 24 1967887091 ps
T1932 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3408797168 Mar 19 02:48:26 PM PDT 24 Mar 19 02:48:27 PM PDT 24 28164314 ps
T1933 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3879138506 Mar 19 03:13:57 PM PDT 24 Mar 19 03:14:00 PM PDT 24 358443946 ps
T1934 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1708020545 Mar 19 02:48:17 PM PDT 24 Mar 19 02:48:19 PM PDT 24 24028283 ps
T1935 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.795543421 Mar 19 02:48:33 PM PDT 24 Mar 19 02:48:34 PM PDT 24 64736328 ps
T1936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2990861738 Mar 19 03:13:55 PM PDT 24 Mar 19 03:13:58 PM PDT 24 333293180 ps
T1937 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.625941273 Mar 19 02:48:27 PM PDT 24 Mar 19 02:48:29 PM PDT 24 56907603 ps
T142 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3750252678 Mar 19 03:14:19 PM PDT 24 Mar 19 03:14:22 PM PDT 24 71518314 ps
T1938 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3793287699 Mar 19 02:48:27 PM PDT 24 Mar 19 02:48:29 PM PDT 24 131675806 ps
T164 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.759862605 Mar 19 02:48:38 PM PDT 24 Mar 19 02:48:41 PM PDT 24 234203289 ps
T1939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3170102631 Mar 19 03:14:08 PM PDT 24 Mar 19 03:14:17 PM PDT 24 347634415 ps
T1940 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2045468134 Mar 19 03:14:19 PM PDT 24 Mar 19 03:14:33 PM PDT 24 2439127010 ps
T1941 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2743748461 Mar 19 03:14:26 PM PDT 24 Mar 19 03:14:30 PM PDT 24 107045261 ps
T1942 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2820342082 Mar 19 02:48:20 PM PDT 24 Mar 19 02:48:23 PM PDT 24 40342409 ps
T1943 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2818102680 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:44 PM PDT 24 230983770 ps
T1944 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.223562079 Mar 19 02:48:27 PM PDT 24 Mar 19 02:48:28 PM PDT 24 55981057 ps
T1945 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2115518612 Mar 19 02:48:26 PM PDT 24 Mar 19 02:48:27 PM PDT 24 56586995 ps
T150 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1396079142 Mar 19 03:14:27 PM PDT 24 Mar 19 03:14:29 PM PDT 24 61746212 ps
T1946 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3534530650 Mar 19 02:48:27 PM PDT 24 Mar 19 02:48:28 PM PDT 24 69016159 ps
T1947 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1673469187 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:27 PM PDT 24 222949534 ps
T1948 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3834269382 Mar 19 03:14:39 PM PDT 24 Mar 19 03:14:40 PM PDT 24 27209009 ps
T1949 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2594415919 Mar 19 02:48:29 PM PDT 24 Mar 19 02:48:31 PM PDT 24 25329713 ps
T1950 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2192287416 Mar 19 02:48:17 PM PDT 24 Mar 19 02:48:19 PM PDT 24 21628223 ps
T155 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3998673927 Mar 19 03:14:35 PM PDT 24 Mar 19 03:14:38 PM PDT 24 435385814 ps
T1951 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.665612200 Mar 19 02:48:42 PM PDT 24 Mar 19 02:48:45 PM PDT 24 424456836 ps
T1952 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3757110472 Mar 19 03:14:01 PM PDT 24 Mar 19 03:14:05 PM PDT 24 94364476 ps
T1953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2190134250 Mar 19 02:48:34 PM PDT 24 Mar 19 02:48:41 PM PDT 24 741234770 ps
T1954 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1987476416 Mar 19 03:14:30 PM PDT 24 Mar 19 03:14:32 PM PDT 24 77317879 ps
T1955 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.309002665 Mar 19 03:14:27 PM PDT 24 Mar 19 03:14:29 PM PDT 24 13758484 ps
T1956 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1638785950 Mar 19 02:48:47 PM PDT 24 Mar 19 02:48:49 PM PDT 24 137415032 ps
T1957 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.256424064 Mar 19 03:14:21 PM PDT 24 Mar 19 03:14:22 PM PDT 24 45272067 ps
T1958 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.37513419 Mar 19 02:48:34 PM PDT 24 Mar 19 02:48:36 PM PDT 24 34667408 ps
T1959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1072253359 Mar 19 03:14:16 PM PDT 24 Mar 19 03:14:18 PM PDT 24 238556545 ps
T1960 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.762546127 Mar 19 03:14:18 PM PDT 24 Mar 19 03:14:22 PM PDT 24 188778077 ps
T1961 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1796553976 Mar 19 02:48:18 PM PDT 24 Mar 19 02:48:26 PM PDT 24 608036081 ps
T1962 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2913925820 Mar 19 03:13:46 PM PDT 24 Mar 19 03:13:49 PM PDT 24 167274311 ps
T1963 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2824613664 Mar 19 02:48:33 PM PDT 24 Mar 19 02:48:34 PM PDT 24 46304599 ps
T1964 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3972841347 Mar 19 02:48:20 PM PDT 24 Mar 19 02:48:21 PM PDT 24 28088599 ps
T1965 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3102624685 Mar 19 03:14:16 PM PDT 24 Mar 19 03:14:20 PM PDT 24 189668003 ps
T1966 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2635497956 Mar 19 03:14:46 PM PDT 24 Mar 19 03:14:48 PM PDT 24 16326794 ps
T1967 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1737748183 Mar 19 02:48:32 PM PDT 24 Mar 19 02:48:33 PM PDT 24 53521672 ps
T1968 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.175001196 Mar 19 03:14:10 PM PDT 24 Mar 19 03:14:11 PM PDT 24 141478063 ps
T1969 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4225734180 Mar 19 02:48:34 PM PDT 24 Mar 19 02:48:35 PM PDT 24 41270009 ps
T1970 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3847282647 Mar 19 03:14:39 PM PDT 24 Mar 19 03:14:42 PM PDT 24 111076726 ps
T1971 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.911502029 Mar 19 03:14:16 PM PDT 24 Mar 19 03:14:18 PM PDT 24 60592189 ps
T1972 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1223791169 Mar 19 02:48:31 PM PDT 24 Mar 19 02:48:33 PM PDT 24 23440189 ps
T1973 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2968615320 Mar 19 03:14:39 PM PDT 24 Mar 19 03:14:41 PM PDT 24 108188135 ps
T1974 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1301891942 Mar 19 02:48:31 PM PDT 24 Mar 19 02:48:41 PM PDT 24 2615936467 ps
T1975 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2561009365 Mar 19 02:48:15 PM PDT 24 Mar 19 02:48:17 PM PDT 24 50928537 ps
T1976 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.935625621 Mar 19 03:14:08 PM PDT 24 Mar 19 03:14:25 PM PDT 24 2674612814 ps
T1977 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1827569861 Mar 19 03:14:28 PM PDT 24 Mar 19 03:14:29 PM PDT 24 34965379 ps
T1978 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2794128487 Mar 19 03:14:28 PM PDT 24 Mar 19 03:14:30 PM PDT 24 119810278 ps
T1979 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.384595480 Mar 19 03:14:11 PM PDT 24 Mar 19 03:14:13 PM PDT 24 104185544 ps
T156 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.456208385 Mar 19 03:14:39 PM PDT 24 Mar 19 03:14:42 PM PDT 24 70852102 ps
T1980 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2083679164 Mar 19 03:14:11 PM PDT 24 Mar 19 03:14:12 PM PDT 24 20109184 ps
T1981 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1016127204 Mar 19 02:48:22 PM PDT 24 Mar 19 02:48:24 PM PDT 24 26007660 ps
T1982 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1529878055 Mar 19 03:14:29 PM PDT 24 Mar 19 03:14:31 PM PDT 24 30661316 ps
T1983 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2247124398 Mar 19 03:14:40 PM PDT 24 Mar 19 03:14:41 PM PDT 24 15587863 ps
T1984 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.421038550 Mar 19 02:48:52 PM PDT 24 Mar 19 02:48:54 PM PDT 24 31702894 ps
T1985 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1094433363 Mar 19 03:14:28 PM PDT 24 Mar 19 03:14:35 PM PDT 24 1061347905 ps
T1986 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3369179361 Mar 19 02:48:23 PM PDT 24 Mar 19 02:48:26 PM PDT 24 64377835 ps
T1987 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2336273050 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:58 PM PDT 24 678916388 ps
T148 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.622385705 Mar 19 03:13:45 PM PDT 24 Mar 19 03:13:49 PM PDT 24 328238746 ps
T151 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1821358157 Mar 19 02:48:18 PM PDT 24 Mar 19 02:48:34 PM PDT 24 3731765532 ps
T1988 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.131753415 Mar 19 03:14:41 PM PDT 24 Mar 19 03:14:43 PM PDT 24 67318356 ps
T160 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.369011510 Mar 19 02:48:27 PM PDT 24 Mar 19 02:48:41 PM PDT 24 707073944 ps
T1989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3566929414 Mar 19 02:48:29 PM PDT 24 Mar 19 02:48:42 PM PDT 24 1055862924 ps
T1990 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.283608634 Mar 19 02:48:30 PM PDT 24 Mar 19 02:48:33 PM PDT 24 178132035 ps
T1991 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.286809094 Mar 19 02:48:37 PM PDT 24 Mar 19 02:48:40 PM PDT 24 89374816 ps
T1992 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1594427398 Mar 19 03:14:37 PM PDT 24 Mar 19 03:14:38 PM PDT 24 42712213 ps
T1993 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1613352609 Mar 19 02:48:24 PM PDT 24 Mar 19 02:48:35 PM PDT 24 1213260136 ps
T1994 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3423247957 Mar 19 02:48:33 PM PDT 24 Mar 19 02:48:35 PM PDT 24 102103062 ps

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1613776766
Short name T11
Test name
Test status
Simulation time 320567420 ps
CPU time 11.36 seconds
Started Mar 19 03:20:38 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 225440 kb
Host smart-f49ee17d-4fe4-4019-9beb-04408b841566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613776766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1613776766
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.1241198932
Short name T15
Test name
Test status
Simulation time 122338335995 ps
CPU time 894.66 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:35:07 PM PDT 24
Peak memory 529708 kb
Host smart-17c51cd0-c607-4a04-a468-5e07dceb2321
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1241198932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.1241198932
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.420625897
Short name T53
Test name
Test status
Simulation time 360465624 ps
CPU time 15.38 seconds
Started Mar 19 03:20:17 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 226080 kb
Host smart-f1f7e258-fae4-4a13-b7ed-af1e4ff3cd65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420625897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.420625897
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2996246575
Short name T7
Test name
Test status
Simulation time 906676696 ps
CPU time 3.36 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:10 PM PDT 24
Peak memory 216860 kb
Host smart-65b07c6e-c1ab-4c05-bdae-92576a958528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996246575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2996246575
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2658755829
Short name T117
Test name
Test status
Simulation time 68973841 ps
CPU time 1.35 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:28 PM PDT 24
Peak memory 217820 kb
Host smart-115eb8b2-d283-42c8-9163-0058ab88cb65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658755829 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2658755829
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.176139349
Short name T47
Test name
Test status
Simulation time 635964988 ps
CPU time 11.14 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:12 PM PDT 24
Peak memory 224596 kb
Host smart-34e84ba5-30cb-40d9-a0dc-f1f4298a7f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176139349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.176139349
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4232566943
Short name T50
Test name
Test status
Simulation time 912315970 ps
CPU time 39.75 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 270056 kb
Host smart-bc3bdfc0-62f1-43ea-acec-b0a0276a1121
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232566943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4232566943
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.4004433632
Short name T19
Test name
Test status
Simulation time 358919267 ps
CPU time 12.36 seconds
Started Mar 19 03:15:47 PM PDT 24
Finished Mar 19 03:16:00 PM PDT 24
Peak memory 217884 kb
Host smart-a4461198-e924-47c7-b65a-5168bdc27b7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004433632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.4
004433632
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2780282405
Short name T115
Test name
Test status
Simulation time 74469080 ps
CPU time 2.96 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 221964 kb
Host smart-c3c6ccba-072b-4474-85bf-04db667e9fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780282405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2780282405
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3979873309
Short name T39
Test name
Test status
Simulation time 16077878796 ps
CPU time 277.81 seconds
Started Mar 19 03:19:39 PM PDT 24
Finished Mar 19 03:24:17 PM PDT 24
Peak memory 221740 kb
Host smart-a832f837-18c5-4c8a-95f7-f0b197f41616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979873309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3979873309
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.656646207
Short name T55
Test name
Test status
Simulation time 36352188812 ps
CPU time 1371.9 seconds
Started Mar 19 03:21:08 PM PDT 24
Finished Mar 19 03:44:00 PM PDT 24
Peak memory 513244 kb
Host smart-6a811d44-bda6-4005-a84c-72f52140d8cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=656646207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.656646207
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3629699731
Short name T179
Test name
Test status
Simulation time 770389271 ps
CPU time 9.47 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:45 PM PDT 24
Peak memory 225140 kb
Host smart-74a43ad4-5394-4501-aa96-68a8c68b4707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629699731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3629699731
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2570884708
Short name T129
Test name
Test status
Simulation time 101220347 ps
CPU time 1.5 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 217816 kb
Host smart-0c5a2ca3-0c0d-4e68-93a6-c60ecb300df4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257088
4708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2570884708
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.194232439
Short name T12
Test name
Test status
Simulation time 12301170 ps
CPU time 0.97 seconds
Started Mar 19 03:16:04 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 209604 kb
Host smart-622311b2-0462-4d46-8210-e47a79a1f217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194232439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.194232439
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3040621027
Short name T207
Test name
Test status
Simulation time 104558068 ps
CPU time 0.96 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 209388 kb
Host smart-2be0e0e0-3038-40ea-9db8-6cd3213e9354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040621027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3040621027
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2727772481
Short name T4
Test name
Test status
Simulation time 6953161007 ps
CPU time 29.13 seconds
Started Mar 19 03:18:55 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 219040 kb
Host smart-6347c5f4-bfce-4118-87e9-f4d16dbfabdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727772481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2727772481
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2299281759
Short name T146
Test name
Test status
Simulation time 310741667 ps
CPU time 3.57 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:36 PM PDT 24
Peak memory 222380 kb
Host smart-c22e4052-43b8-421d-a9fd-b076c3ea75f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299281759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2299281759
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.304140701
Short name T58
Test name
Test status
Simulation time 354808351 ps
CPU time 14.47 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:19:04 PM PDT 24
Peak memory 214336 kb
Host smart-e98a94b6-d82c-4f05-b72f-4b1df1999f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304140701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.304140701
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3248163603
Short name T170
Test name
Test status
Simulation time 47579289551 ps
CPU time 2023.49 seconds
Started Mar 19 03:16:06 PM PDT 24
Finished Mar 19 03:49:50 PM PDT 24
Peak memory 709904 kb
Host smart-c9dabd9e-278f-47c7-9580-14fbce0e6b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3248163603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3248163603
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.438618053
Short name T43
Test name
Test status
Simulation time 335920288 ps
CPU time 14.6 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:19:07 PM PDT 24
Peak memory 217960 kb
Host smart-69ac566f-84ca-4904-8ed2-5946eeadc6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438618053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.438618053
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3136466284
Short name T131
Test name
Test status
Simulation time 116682022 ps
CPU time 4.46 seconds
Started Mar 19 02:48:34 PM PDT 24
Finished Mar 19 02:48:39 PM PDT 24
Peak memory 217608 kb
Host smart-4be50418-11dc-4636-9799-5598849cfa50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136466284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3136466284
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1727556489
Short name T87
Test name
Test status
Simulation time 100515844322 ps
CPU time 925.84 seconds
Started Mar 19 03:15:20 PM PDT 24
Finished Mar 19 03:30:46 PM PDT 24
Peak memory 496432 kb
Host smart-832a0402-9f45-4454-a979-d1388aaa1f38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1727556489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.1727556489
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.622385705
Short name T148
Test name
Test status
Simulation time 328238746 ps
CPU time 2.7 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:13:49 PM PDT 24
Peak memory 222308 kb
Host smart-5a042a9d-c861-423c-93ad-6b796877316d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622385705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.622385705
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.59320572
Short name T144
Test name
Test status
Simulation time 222643655 ps
CPU time 4.27 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:34 PM PDT 24
Peak memory 217660 kb
Host smart-17a96a09-1232-499d-86b7-88d407c1c15c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59320572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_e
rr.59320572
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1860452830
Short name T89
Test name
Test status
Simulation time 11166982881 ps
CPU time 232.46 seconds
Started Mar 19 03:20:25 PM PDT 24
Finished Mar 19 03:24:18 PM PDT 24
Peak memory 268568 kb
Host smart-f8d4a594-782b-404e-954c-6ebcc7f69989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1860452830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1860452830
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3418162864
Short name T22
Test name
Test status
Simulation time 14487757 ps
CPU time 0.96 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 212704 kb
Host smart-4918a7f9-1b20-4181-924e-c184a10b2e20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418162864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3418162864
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1214542599
Short name T137
Test name
Test status
Simulation time 235388091 ps
CPU time 2.53 seconds
Started Mar 19 03:14:40 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 217652 kb
Host smart-d4764f0e-3508-4bdb-890b-7aa6414213a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214542599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1214542599
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2857622229
Short name T138
Test name
Test status
Simulation time 68882554 ps
CPU time 2.65 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 217656 kb
Host smart-57ca68b3-c893-4b6e-9582-4416514c9fed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857622229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2857622229
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2878483685
Short name T239
Test name
Test status
Simulation time 15189445 ps
CPU time 0.79 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:22 PM PDT 24
Peak memory 209372 kb
Host smart-38cdceac-a463-48b7-9ed8-6e77a2a122ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878483685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2878483685
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.4134531895
Short name T236
Test name
Test status
Simulation time 52089866 ps
CPU time 0.78 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:18:54 PM PDT 24
Peak memory 209372 kb
Host smart-01e961a6-e52c-419e-92b5-00bcf35d6d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134531895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4134531895
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3118993668
Short name T240
Test name
Test status
Simulation time 19736965 ps
CPU time 0.92 seconds
Started Mar 19 03:15:30 PM PDT 24
Finished Mar 19 03:15:31 PM PDT 24
Peak memory 209476 kb
Host smart-717b321b-7789-47b1-a787-336ba7eefff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118993668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3118993668
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1164845808
Short name T241
Test name
Test status
Simulation time 23936094 ps
CPU time 0.85 seconds
Started Mar 19 03:15:36 PM PDT 24
Finished Mar 19 03:15:37 PM PDT 24
Peak memory 209340 kb
Host smart-15a8a4e7-79a0-4f18-8aa9-5ec09d96c170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164845808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1164845808
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3496658947
Short name T233
Test name
Test status
Simulation time 13206109 ps
CPU time 0.82 seconds
Started Mar 19 03:15:58 PM PDT 24
Finished Mar 19 03:15:59 PM PDT 24
Peak memory 209384 kb
Host smart-de0867a1-25c3-4a99-8f23-ead63be7d6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496658947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3496658947
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3970912781
Short name T81
Test name
Test status
Simulation time 42764932 ps
CPU time 6.02 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:37 PM PDT 24
Peak memory 246500 kb
Host smart-a5268bb0-b84e-4c7a-8b41-05009a08bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970912781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3970912781
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2495911342
Short name T1758
Test name
Test status
Simulation time 41388774 ps
CPU time 2.32 seconds
Started Mar 19 03:13:50 PM PDT 24
Finished Mar 19 03:13:52 PM PDT 24
Peak memory 218840 kb
Host smart-7f690484-09e1-4c04-aaed-22762a38aaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495911342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2495911342
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1821358157
Short name T151
Test name
Test status
Simulation time 3731765532 ps
CPU time 15.2 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 217676 kb
Host smart-bbb08f22-2475-445e-955a-9dd2baeabb90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821358157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1821358157
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1396079142
Short name T150
Test name
Test status
Simulation time 61746212 ps
CPU time 2.59 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 217632 kb
Host smart-5184987e-13b1-4838-8809-8f9f917ae24f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396079142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1396079142
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.221267900
Short name T149
Test name
Test status
Simulation time 1098621486 ps
CPU time 7.16 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:48 PM PDT 24
Peak memory 217552 kb
Host smart-a78f46dc-48cc-4bc0-89c0-45005756d63a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221267900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.221267900
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.456208385
Short name T156
Test name
Test status
Simulation time 70852102 ps
CPU time 2.87 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 217644 kb
Host smart-57f91c71-2123-44f4-a576-d49282ef53d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456208385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.456208385
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1745830191
Short name T134
Test name
Test status
Simulation time 166088437 ps
CPU time 2.72 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:48:57 PM PDT 24
Peak memory 222180 kb
Host smart-be0bf59d-3730-4bb8-ac6f-a0d72c73ab35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745830191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1745830191
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.694263460
Short name T128
Test name
Test status
Simulation time 60920766 ps
CPU time 1.94 seconds
Started Mar 19 03:14:08 PM PDT 24
Finished Mar 19 03:14:10 PM PDT 24
Peak memory 222120 kb
Host smart-ea5a3895-9aba-4994-aecc-d6d160c54f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694263460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.694263460
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.369011510
Short name T160
Test name
Test status
Simulation time 707073944 ps
CPU time 3.45 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:41 PM PDT 24
Peak memory 217616 kb
Host smart-c18c9421-65a7-4c8a-81b9-bb19fb5a298a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369011510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.369011510
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.831506938
Short name T14
Test name
Test status
Simulation time 23639918652 ps
CPU time 207.64 seconds
Started Mar 19 03:20:14 PM PDT 24
Finished Mar 19 03:23:42 PM PDT 24
Peak memory 278216 kb
Host smart-09405eaf-1d10-4356-92fa-7b3fd0ed7741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831506938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.831506938
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2682602249
Short name T20
Test name
Test status
Simulation time 46485563 ps
CPU time 1.52 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:19:47 PM PDT 24
Peak memory 213444 kb
Host smart-f938d6ac-dbed-44e5-be88-3b720b0c224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682602249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2682602249
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3360695245
Short name T1873
Test name
Test status
Simulation time 79098920 ps
CPU time 1.08 seconds
Started Mar 19 02:48:16 PM PDT 24
Finished Mar 19 02:48:17 PM PDT 24
Peak memory 209376 kb
Host smart-7988876c-d773-4846-9c86-a65e2cc6e25f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360695245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3360695245
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.648784894
Short name T1880
Test name
Test status
Simulation time 78777019 ps
CPU time 1.37 seconds
Started Mar 19 03:13:48 PM PDT 24
Finished Mar 19 03:13:49 PM PDT 24
Peak memory 209368 kb
Host smart-03b43ba5-c768-4c7b-a0a9-0ca27e9ee10c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648784894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.648784894
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1671842460
Short name T1912
Test name
Test status
Simulation time 29560017 ps
CPU time 1.94 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 209320 kb
Host smart-a2e7b026-e093-4ff8-99b5-647141fe2b6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671842460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1671842460
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.530973328
Short name T1834
Test name
Test status
Simulation time 175468573 ps
CPU time 1.91 seconds
Started Mar 19 03:13:47 PM PDT 24
Finished Mar 19 03:13:49 PM PDT 24
Peak memory 208556 kb
Host smart-cd5d0c49-cc61-484c-807b-74a374e00ac2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530973328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.530973328
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1669180311
Short name T205
Test name
Test status
Simulation time 34570931 ps
CPU time 1.02 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 210516 kb
Host smart-bd50e3b7-4852-4366-a5e5-611fa230022c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669180311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1669180311
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2886271934
Short name T1881
Test name
Test status
Simulation time 12199285 ps
CPU time 0.94 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 209684 kb
Host smart-2750f2c2-2f49-4e9c-b75d-21fde17f18d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886271934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2886271934
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1241274082
Short name T1883
Test name
Test status
Simulation time 257765059 ps
CPU time 1.95 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 217716 kb
Host smart-05b7d2e5-53f7-493a-94ed-9d650b743e2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241274082 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1241274082
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3999382083
Short name T1844
Test name
Test status
Simulation time 96042652 ps
CPU time 1.35 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 219324 kb
Host smart-b71bfe20-e070-4eff-8c1d-6a272f5fb150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999382083 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3999382083
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1559729841
Short name T212
Test name
Test status
Simulation time 12910011 ps
CPU time 0.87 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:15 PM PDT 24
Peak memory 209196 kb
Host smart-543f6efa-5ade-4a34-b752-c372ecceb436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559729841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1559729841
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1919463978
Short name T1779
Test name
Test status
Simulation time 170415864 ps
CPU time 2.47 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 209352 kb
Host smart-f3579955-6251-4cac-b4cc-98f58b9566f3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919463978 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1919463978
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4073040709
Short name T1719
Test name
Test status
Simulation time 105405046 ps
CPU time 1.64 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 209296 kb
Host smart-515e120d-9bbc-4fe4-bf77-45f5b60e3120
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073040709 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4073040709
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.244580081
Short name T1927
Test name
Test status
Simulation time 2469804782 ps
CPU time 5.3 seconds
Started Mar 19 03:13:49 PM PDT 24
Finished Mar 19 03:13:54 PM PDT 24
Peak memory 209444 kb
Host smart-9c6d749b-6467-4765-ada9-d36784c7ac41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244580081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.244580081
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2904129078
Short name T1890
Test name
Test status
Simulation time 1635162324 ps
CPU time 10.86 seconds
Started Mar 19 02:48:22 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 209136 kb
Host smart-8c714b9a-6554-4503-8513-7df82d8e6d69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904129078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2904129078
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2841802489
Short name T1802
Test name
Test status
Simulation time 3730004692 ps
CPU time 21.56 seconds
Started Mar 19 03:13:47 PM PDT 24
Finished Mar 19 03:14:08 PM PDT 24
Peak memory 208484 kb
Host smart-ba868309-a4c7-4336-86b5-2d3e5ef53a28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841802489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2841802489
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4256170171
Short name T230
Test name
Test status
Simulation time 1430442441 ps
CPU time 9.42 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:38 PM PDT 24
Peak memory 208544 kb
Host smart-b0077203-6bfc-488e-a9ab-29277ec7e0e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256170171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4256170171
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1021415150
Short name T1791
Test name
Test status
Simulation time 311893010 ps
CPU time 4.4 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 210976 kb
Host smart-3dc679cd-4d82-4cf6-8a5f-296dce961e23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021415150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1021415150
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2913925820
Short name T1962
Test name
Test status
Simulation time 167274311 ps
CPU time 2.64 seconds
Started Mar 19 03:13:46 PM PDT 24
Finished Mar 19 03:13:49 PM PDT 24
Peak memory 210892 kb
Host smart-bb46d849-8f07-496f-8e23-b288e0cc61f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913925820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2913925820
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2042991599
Short name T1773
Test name
Test status
Simulation time 50019335 ps
CPU time 2.23 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 218132 kb
Host smart-46907d14-c77b-40ef-93a9-4c8a30d93a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204299
1599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2042991599
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2395930709
Short name T1783
Test name
Test status
Simulation time 286431060 ps
CPU time 4.66 seconds
Started Mar 19 03:13:49 PM PDT 24
Finished Mar 19 03:13:54 PM PDT 24
Peak memory 219176 kb
Host smart-3acdf2cc-e92f-4249-85b0-91d82b99733e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239593
0709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2395930709
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3726118304
Short name T1772
Test name
Test status
Simulation time 123001812 ps
CPU time 2.92 seconds
Started Mar 19 03:13:48 PM PDT 24
Finished Mar 19 03:13:51 PM PDT 24
Peak memory 209372 kb
Host smart-4f8b5fdb-7c60-4dc5-97e8-de9d8ea79526
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726118304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3726118304
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4267025106
Short name T1734
Test name
Test status
Simulation time 279665141 ps
CPU time 3.86 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 209396 kb
Host smart-b648a4e7-4dcb-4aa0-80a3-5b3361ba365b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267025106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.4267025106
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1240283657
Short name T1910
Test name
Test status
Simulation time 46827667 ps
CPU time 1.43 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 211440 kb
Host smart-c88917f7-9a1e-4381-9565-ab0d7f9aacf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240283657 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1240283657
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1683209692
Short name T1767
Test name
Test status
Simulation time 25063865 ps
CPU time 1.1 seconds
Started Mar 19 03:13:46 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 209416 kb
Host smart-9dcccf17-1764-4b9b-b033-5666a0d1bab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683209692 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1683209692
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.308070376
Short name T1796
Test name
Test status
Simulation time 148454657 ps
CPU time 1.4 seconds
Started Mar 19 02:48:16 PM PDT 24
Finished Mar 19 02:48:18 PM PDT 24
Peak memory 211380 kb
Host smart-998b1144-689d-4938-b633-04c7ccb773e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308070376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.308070376
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.528240650
Short name T1896
Test name
Test status
Simulation time 37453385 ps
CPU time 1.44 seconds
Started Mar 19 03:13:48 PM PDT 24
Finished Mar 19 03:13:49 PM PDT 24
Peak memory 217716 kb
Host smart-947ead50-6125-4dde-af4e-0e252d326205
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528240650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.528240650
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.176030566
Short name T1786
Test name
Test status
Simulation time 79270029 ps
CPU time 2.73 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 217748 kb
Host smart-3afc229d-dd57-4951-9848-cc8ab7fad270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176030566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.176030566
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4124726665
Short name T206
Test name
Test status
Simulation time 56383209 ps
CPU time 1.2 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:19 PM PDT 24
Peak memory 217608 kb
Host smart-e8afdc69-5129-4d76-89b5-63f8c880b33a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124726665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4124726665
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.684343723
Short name T1893
Test name
Test status
Simulation time 107625092 ps
CPU time 1.06 seconds
Started Mar 19 03:13:55 PM PDT 24
Finished Mar 19 03:13:57 PM PDT 24
Peak memory 208604 kb
Host smart-79d6eba4-e600-4de7-9e9d-7f0f25433eb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684343723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.684343723
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2686287465
Short name T1884
Test name
Test status
Simulation time 38242768 ps
CPU time 1.4 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 208524 kb
Host smart-dcf354da-fdfd-4c93-9d52-fea22275e2b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686287465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2686287465
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3568420960
Short name T1922
Test name
Test status
Simulation time 91187646 ps
CPU time 1.45 seconds
Started Mar 19 03:13:56 PM PDT 24
Finished Mar 19 03:13:57 PM PDT 24
Peak memory 209060 kb
Host smart-de862dd2-04a4-4b66-92f2-7f60b34334fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568420960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3568420960
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2790413663
Short name T1879
Test name
Test status
Simulation time 20320226 ps
CPU time 1.19 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:18 PM PDT 24
Peak memory 211276 kb
Host smart-45b73309-207f-4148-b8b0-c0c1fcbc7123
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790413663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2790413663
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3102151146
Short name T220
Test name
Test status
Simulation time 83450490 ps
CPU time 0.96 seconds
Started Mar 19 03:13:56 PM PDT 24
Finished Mar 19 03:13:57 PM PDT 24
Peak memory 209696 kb
Host smart-0e8e3cd6-0a22-416e-9b64-b74d47e2eb10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102151146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3102151146
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2122917149
Short name T1728
Test name
Test status
Simulation time 53839741 ps
CPU time 1.57 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 217736 kb
Host smart-e2cb91a8-de9d-4476-b762-c58c2252bb5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122917149 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2122917149
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3456091893
Short name T1847
Test name
Test status
Simulation time 13742973 ps
CPU time 1 seconds
Started Mar 19 03:14:08 PM PDT 24
Finished Mar 19 03:14:09 PM PDT 24
Peak memory 217752 kb
Host smart-3f14778d-21fb-444a-a15f-7de0a3e8ba1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456091893 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3456091893
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.232154328
Short name T1865
Test name
Test status
Simulation time 52453588 ps
CPU time 0.86 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 209224 kb
Host smart-212cfece-945d-48dd-a129-36a3153894b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232154328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.232154328
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4011655095
Short name T1819
Test name
Test status
Simulation time 26712998 ps
CPU time 0.88 seconds
Started Mar 19 03:13:57 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 209368 kb
Host smart-6c14ce79-edaa-4bad-92f4-d254dfcd3742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011655095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.4011655095
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1841109977
Short name T1751
Test name
Test status
Simulation time 69415358 ps
CPU time 1.02 seconds
Started Mar 19 03:14:07 PM PDT 24
Finished Mar 19 03:14:08 PM PDT 24
Peak memory 209312 kb
Host smart-f2162a8d-9fc1-4121-8876-44adb9a2a7a2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841109977 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1841109977
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.223562079
Short name T1944
Test name
Test status
Simulation time 55981057 ps
CPU time 1.16 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 209344 kb
Host smart-90106465-3027-46d9-8f1a-776db6f58844
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223562079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.223562079
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.137935640
Short name T1704
Test name
Test status
Simulation time 568729756 ps
CPU time 14.15 seconds
Started Mar 19 02:48:16 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 208524 kb
Host smart-8a93ff1b-ec3f-46eb-a044-fb12c2f24df1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137935640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.137935640
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2506639945
Short name T1857
Test name
Test status
Simulation time 643717720 ps
CPU time 14.77 seconds
Started Mar 19 03:13:48 PM PDT 24
Finished Mar 19 03:14:03 PM PDT 24
Peak memory 209084 kb
Host smart-0c841ebb-40e9-4d5c-a9b8-042cee190bff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506639945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2506639945
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1696812245
Short name T1784
Test name
Test status
Simulation time 2404278151 ps
CPU time 19.96 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 209328 kb
Host smart-b487fe20-3eaa-4b05-8609-fac5bb60e2db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696812245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1696812245
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3570298465
Short name T1866
Test name
Test status
Simulation time 3598118816 ps
CPU time 4.55 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:13:50 PM PDT 24
Peak memory 209436 kb
Host smart-64d6485f-d787-405a-91ef-b9a89f68fa8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570298465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3570298465
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2042116242
Short name T1918
Test name
Test status
Simulation time 312631776 ps
CPU time 1.75 seconds
Started Mar 19 03:13:49 PM PDT 24
Finished Mar 19 03:13:51 PM PDT 24
Peak memory 211020 kb
Host smart-61edfc14-0310-4cbd-9c22-ca1e1b5c7d9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042116242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2042116242
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.622585440
Short name T1739
Test name
Test status
Simulation time 409980122 ps
CPU time 1.26 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 209296 kb
Host smart-892fc6a8-35fd-4c10-8f8e-67adff1c7552
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622585440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.622585440
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1017370659
Short name T1920
Test name
Test status
Simulation time 785293224 ps
CPU time 4.2 seconds
Started Mar 19 02:48:16 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 218096 kb
Host smart-70c89b62-32c9-4a69-8337-f30d07b9a9f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101737
0659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1017370659
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3879138506
Short name T1933
Test name
Test status
Simulation time 358443946 ps
CPU time 2.52 seconds
Started Mar 19 03:13:57 PM PDT 24
Finished Mar 19 03:14:00 PM PDT 24
Peak memory 223348 kb
Host smart-ab429f85-7adf-4b4a-849c-cb889e6b2c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387913
8506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3879138506
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1687683608
Short name T166
Test name
Test status
Simulation time 97748934 ps
CPU time 1.22 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 209348 kb
Host smart-8a25d155-483a-4cd2-946a-08bf24ff6cd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687683608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1687683608
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.802013540
Short name T1885
Test name
Test status
Simulation time 1426348886 ps
CPU time 3.05 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:13:49 PM PDT 24
Peak memory 209380 kb
Host smart-03667127-c54e-4213-a60b-aa96d7ec04b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802013540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.802013540
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1992697951
Short name T224
Test name
Test status
Simulation time 45341722 ps
CPU time 0.99 seconds
Started Mar 19 03:13:57 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 209516 kb
Host smart-824c9db2-a5a2-4952-bbd1-e6f07863b4c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992697951 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1992697951
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2192287416
Short name T1950
Test name
Test status
Simulation time 21628223 ps
CPU time 1.2 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:19 PM PDT 24
Peak memory 209448 kb
Host smart-93c4739a-d9a2-4e78-886c-269d24b7d0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192287416 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2192287416
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2682558134
Short name T1788
Test name
Test status
Simulation time 36972761 ps
CPU time 1.74 seconds
Started Mar 19 03:13:57 PM PDT 24
Finished Mar 19 03:13:59 PM PDT 24
Peak memory 211328 kb
Host smart-7d7e6de2-9e41-4e69-86c8-fd3942f94b7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682558134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2682558134
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3534530650
Short name T1946
Test name
Test status
Simulation time 69016159 ps
CPU time 1.13 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 209452 kb
Host smart-21be9f67-ed79-4dca-ab9f-2c4e6ac72466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534530650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3534530650
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3232395089
Short name T1875
Test name
Test status
Simulation time 365237786 ps
CPU time 3.31 seconds
Started Mar 19 03:13:58 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 219084 kb
Host smart-ce93f17e-d841-4f89-bb3d-b142caccf8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232395089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3232395089
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4040916559
Short name T1748
Test name
Test status
Simulation time 151418830 ps
CPU time 2.65 seconds
Started Mar 19 02:48:16 PM PDT 24
Finished Mar 19 02:48:19 PM PDT 24
Peak memory 217764 kb
Host smart-de200b4b-e4a3-43c9-ae5d-e34ba047b18a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040916559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4040916559
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.972942573
Short name T244
Test name
Test status
Simulation time 52391397 ps
CPU time 2.41 seconds
Started Mar 19 03:13:55 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 222024 kb
Host smart-14660953-0ed9-4827-bb2d-ee0a29e750c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972942573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.972942573
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3423247957
Short name T1994
Test name
Test status
Simulation time 102103062 ps
CPU time 1.79 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 219808 kb
Host smart-c46c1922-b8a3-4e30-84b0-1c18b9931334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423247957 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3423247957
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1082077395
Short name T211
Test name
Test status
Simulation time 23644661 ps
CPU time 0.88 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 209388 kb
Host smart-b4540e17-de2b-45ff-93ef-df2d257dbd6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082077395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1082077395
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2279040693
Short name T1768
Test name
Test status
Simulation time 14887229 ps
CPU time 0.87 seconds
Started Mar 19 03:14:25 PM PDT 24
Finished Mar 19 03:14:26 PM PDT 24
Peak memory 209412 kb
Host smart-f0901de8-378c-4ab8-8284-13dc9aacb75e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279040693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2279040693
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2093290917
Short name T1816
Test name
Test status
Simulation time 73394439 ps
CPU time 1.18 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 209536 kb
Host smart-15dff1ef-3d33-4b53-ae0b-a8d50225efe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093290917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2093290917
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2185889875
Short name T1717
Test name
Test status
Simulation time 93589875 ps
CPU time 1.05 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 209400 kb
Host smart-ca19a2a2-8078-41e7-b899-38e7388cb0d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185889875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2185889875
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1680538732
Short name T1856
Test name
Test status
Simulation time 200603701 ps
CPU time 2.77 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 218728 kb
Host smart-7e5687a4-483b-4cc5-ae7d-44f771f5431d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680538732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1680538732
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1987476416
Short name T1954
Test name
Test status
Simulation time 77317879 ps
CPU time 2.38 seconds
Started Mar 19 03:14:30 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 217752 kb
Host smart-6620376f-854a-4286-b4f9-033e7262b3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987476416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1987476416
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3462135654
Short name T143
Test name
Test status
Simulation time 243718586 ps
CPU time 2.72 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 217632 kb
Host smart-285887fb-39b8-4714-94ba-abc3e3f65f23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462135654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3462135654
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.224896562
Short name T1705
Test name
Test status
Simulation time 18938364 ps
CPU time 1.29 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 217708 kb
Host smart-352e2198-b746-46e3-8b66-84c08aec95f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224896562 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.224896562
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.485515851
Short name T1864
Test name
Test status
Simulation time 67082590 ps
CPU time 1.36 seconds
Started Mar 19 02:48:48 PM PDT 24
Finished Mar 19 02:48:50 PM PDT 24
Peak memory 219472 kb
Host smart-88820c9a-9fba-4fba-9051-d1208b1507c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485515851 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.485515851
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2247124398
Short name T1983
Test name
Test status
Simulation time 15587863 ps
CPU time 0.92 seconds
Started Mar 19 03:14:40 PM PDT 24
Finished Mar 19 03:14:41 PM PDT 24
Peak memory 209016 kb
Host smart-5ef4e02c-c852-452e-a357-a20292f30b2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247124398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2247124398
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3771272648
Short name T1761
Test name
Test status
Simulation time 27546138 ps
CPU time 0.89 seconds
Started Mar 19 02:48:34 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 209204 kb
Host smart-d234f9f4-12b6-4200-bb16-bf8af88229c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771272648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3771272648
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2794128487
Short name T1978
Test name
Test status
Simulation time 119810278 ps
CPU time 1.05 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 209440 kb
Host smart-0dd7fe10-b935-4532-b520-317706f83465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794128487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2794128487
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.437173451
Short name T1830
Test name
Test status
Simulation time 225679092 ps
CPU time 1.47 seconds
Started Mar 19 02:48:42 PM PDT 24
Finished Mar 19 02:48:43 PM PDT 24
Peak memory 209452 kb
Host smart-7237608d-830f-4d7f-a4f2-07a6e3974dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437173451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.437173451
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2407683445
Short name T1876
Test name
Test status
Simulation time 34286308 ps
CPU time 2.48 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 217768 kb
Host smart-81765881-df1a-45da-888b-e04a08a7da1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407683445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2407683445
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2493021531
Short name T1789
Test name
Test status
Simulation time 384244653 ps
CPU time 3.53 seconds
Started Mar 19 03:14:31 PM PDT 24
Finished Mar 19 03:14:34 PM PDT 24
Peak memory 217744 kb
Host smart-6d785b79-44d9-4276-a743-7081eb99d603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493021531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2493021531
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3414839666
Short name T132
Test name
Test status
Simulation time 291958135 ps
CPU time 2.78 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:36 PM PDT 24
Peak memory 222124 kb
Host smart-147dd4fb-65a0-494d-b096-208a8ff7dfb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414839666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3414839666
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.4250354102
Short name T157
Test name
Test status
Simulation time 214982236 ps
CPU time 1.97 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 221552 kb
Host smart-b19f2ef0-eee5-4d99-baa4-d0844b86e0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250354102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.4250354102
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.132778963
Short name T1841
Test name
Test status
Simulation time 34884163 ps
CPU time 2.69 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:44 PM PDT 24
Peak memory 217740 kb
Host smart-0b7843ed-3edb-4bbd-84b7-daa72a6b74ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132778963 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.132778963
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.696467691
Short name T1822
Test name
Test status
Simulation time 55186391 ps
CPU time 1.23 seconds
Started Mar 19 02:48:38 PM PDT 24
Finished Mar 19 02:48:39 PM PDT 24
Peak memory 218808 kb
Host smart-92a157ad-1bc1-47b9-949e-c79383915e13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696467691 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.696467691
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3358996836
Short name T1882
Test name
Test status
Simulation time 48191789 ps
CPU time 1.03 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 209108 kb
Host smart-86018052-e43b-4d34-8b79-aa9b09aa20e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358996836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3358996836
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.778270417
Short name T219
Test name
Test status
Simulation time 17876833 ps
CPU time 0.9 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:39 PM PDT 24
Peak memory 209388 kb
Host smart-d56f00fa-5c08-48e8-afef-2207e52761a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778270417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.778270417
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1529878055
Short name T1982
Test name
Test status
Simulation time 30661316 ps
CPU time 1.25 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 209424 kb
Host smart-bb142615-638f-41ab-9f7c-09c9c23a1aa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529878055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1529878055
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1576232035
Short name T1732
Test name
Test status
Simulation time 60763231 ps
CPU time 1.2 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 209560 kb
Host smart-3a7ea86b-fd7c-4768-b2b6-c2c1c22ac395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576232035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1576232035
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.622953681
Short name T121
Test name
Test status
Simulation time 266909756 ps
CPU time 2.7 seconds
Started Mar 19 03:14:26 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 217832 kb
Host smart-362c3e39-4ead-4e14-bb70-d4aa8a7b4015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622953681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.622953681
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.795543421
Short name T1935
Test name
Test status
Simulation time 64736328 ps
CPU time 1.87 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 217760 kb
Host smart-785a6f71-d0b9-4f63-a35c-1a277cae6ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795543421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.795543421
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.588761564
Short name T161
Test name
Test status
Simulation time 46373979 ps
CPU time 1.83 seconds
Started Mar 19 03:14:30 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 212832 kb
Host smart-6b3a7c38-088b-42e8-acef-6babd62f22ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588761564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.588761564
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.759862605
Short name T164
Test name
Test status
Simulation time 234203289 ps
CPU time 2.55 seconds
Started Mar 19 02:48:38 PM PDT 24
Finished Mar 19 02:48:41 PM PDT 24
Peak memory 217624 kb
Host smart-dfd78a94-3119-4348-803a-c7d281927a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759862605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.759862605
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1381864782
Short name T1746
Test name
Test status
Simulation time 23659187 ps
CPU time 1.49 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 217692 kb
Host smart-7d35a148-20db-42b8-ac97-c4d3ac96a003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381864782 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1381864782
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1545644725
Short name T1781
Test name
Test status
Simulation time 23833476 ps
CPU time 1.24 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 218736 kb
Host smart-200dcdb0-f70c-4854-b9aa-924d562e74a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545644725 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1545644725
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3053230768
Short name T1924
Test name
Test status
Simulation time 116886962 ps
CPU time 0.9 seconds
Started Mar 19 02:48:36 PM PDT 24
Finished Mar 19 02:48:37 PM PDT 24
Peak memory 209356 kb
Host smart-c9b9fc68-3774-4cd3-baa3-b481d4bccffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053230768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3053230768
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3920180232
Short name T1755
Test name
Test status
Simulation time 18431621 ps
CPU time 0.9 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:40 PM PDT 24
Peak memory 209096 kb
Host smart-2ca0b5d9-33ae-4217-890e-df48d1ea31cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920180232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3920180232
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.414150770
Short name T225
Test name
Test status
Simulation time 45018981 ps
CPU time 1.98 seconds
Started Mar 19 03:14:42 PM PDT 24
Finished Mar 19 03:14:44 PM PDT 24
Peak memory 211296 kb
Host smart-d3630a9d-2568-49b6-a8e3-2962e5d6ff3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414150770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.414150770
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.68423483
Short name T1837
Test name
Test status
Simulation time 23030569 ps
CPU time 1.25 seconds
Started Mar 19 02:48:38 PM PDT 24
Finished Mar 19 02:48:40 PM PDT 24
Peak memory 209540 kb
Host smart-57e1fdc2-9053-45f7-83a7-1fef871f7f57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68423483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
same_csr_outstanding.68423483
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1632380514
Short name T1713
Test name
Test status
Simulation time 40646693 ps
CPU time 2.87 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 217800 kb
Host smart-4bc45c49-7e7c-42ae-9845-d2df5bbdd926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632380514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1632380514
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.286809094
Short name T1991
Test name
Test status
Simulation time 89374816 ps
CPU time 2.72 seconds
Started Mar 19 02:48:37 PM PDT 24
Finished Mar 19 02:48:40 PM PDT 24
Peak memory 217780 kb
Host smart-12ac8f62-797d-400a-adfa-cf4085766530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286809094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.286809094
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.37513419
Short name T1958
Test name
Test status
Simulation time 34667408 ps
CPU time 1.08 seconds
Started Mar 19 02:48:34 PM PDT 24
Finished Mar 19 02:48:36 PM PDT 24
Peak memory 217756 kb
Host smart-09acc08b-94d4-4623-b48d-fcb394377578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37513419 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.37513419
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4225292204
Short name T1818
Test name
Test status
Simulation time 50162447 ps
CPU time 1.64 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:40 PM PDT 24
Peak memory 219756 kb
Host smart-71b6a84c-bcca-43ef-82f6-6b6baa0e6b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225292204 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4225292204
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1667222739
Short name T208
Test name
Test status
Simulation time 50677904 ps
CPU time 0.99 seconds
Started Mar 19 03:14:38 PM PDT 24
Finished Mar 19 03:14:40 PM PDT 24
Peak memory 209304 kb
Host smart-802948c9-b2f6-4266-a1f2-dce2be3f65bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667222739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1667222739
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3918887009
Short name T215
Test name
Test status
Simulation time 117356197 ps
CPU time 0.84 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 209212 kb
Host smart-98903de8-e20c-49e5-ab29-466c9cac23ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918887009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3918887009
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2167588990
Short name T1861
Test name
Test status
Simulation time 20358513 ps
CPU time 1.27 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 217628 kb
Host smart-f6a166cd-5a85-48f8-89bd-ea214a7b1255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167588990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2167588990
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3834269382
Short name T1948
Test name
Test status
Simulation time 27209009 ps
CPU time 1.22 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:40 PM PDT 24
Peak memory 209440 kb
Host smart-f1ae50ef-f301-41cf-aabd-2cba86715814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834269382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3834269382
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2018716571
Short name T1867
Test name
Test status
Simulation time 98564637 ps
CPU time 2.15 seconds
Started Mar 19 02:48:50 PM PDT 24
Finished Mar 19 02:48:52 PM PDT 24
Peak memory 217848 kb
Host smart-dc15bc19-6e68-4e1b-bac3-e0d9648890cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018716571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2018716571
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2968615320
Short name T1973
Test name
Test status
Simulation time 108188135 ps
CPU time 1.99 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:41 PM PDT 24
Peak memory 217780 kb
Host smart-db79e6db-6ea8-49a9-aea9-6e71cee6f7db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968615320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2968615320
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1223791169
Short name T1972
Test name
Test status
Simulation time 23440189 ps
CPU time 1.67 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 217748 kb
Host smart-b1f30a1f-328b-4003-ae1a-75f215967b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223791169 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1223791169
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.612906014
Short name T1771
Test name
Test status
Simulation time 28307554 ps
CPU time 1.14 seconds
Started Mar 19 03:14:46 PM PDT 24
Finished Mar 19 03:14:48 PM PDT 24
Peak memory 219600 kb
Host smart-78b7b744-4fe4-4d43-a303-9fede7de9759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612906014 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.612906014
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1737748183
Short name T1967
Test name
Test status
Simulation time 53521672 ps
CPU time 0.84 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 209244 kb
Host smart-81c841c5-0102-4f7c-8ef5-89d5ef5b1cb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737748183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1737748183
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3173013717
Short name T1787
Test name
Test status
Simulation time 22383352 ps
CPU time 0.86 seconds
Started Mar 19 03:14:38 PM PDT 24
Finished Mar 19 03:14:39 PM PDT 24
Peak memory 208604 kb
Host smart-98178af7-ef13-4d25-850c-d8fd66742ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173013717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3173013717
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2550058202
Short name T223
Test name
Test status
Simulation time 90680265 ps
CPU time 1.07 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 209024 kb
Host smart-edd68be3-bc42-47e4-9eaf-cba5226c7360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550058202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2550058202
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3829493855
Short name T228
Test name
Test status
Simulation time 62502245 ps
CPU time 1.19 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 217644 kb
Host smart-165be2d7-ff62-4c0a-a4fa-e3c3f37acf2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829493855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3829493855
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1262987492
Short name T1826
Test name
Test status
Simulation time 39550080 ps
CPU time 2.91 seconds
Started Mar 19 03:14:40 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 217792 kb
Host smart-87b699ba-b651-4dd6-98b9-1482dad5b3db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262987492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1262987492
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2853205091
Short name T1863
Test name
Test status
Simulation time 102194291 ps
CPU time 3.51 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 217856 kb
Host smart-e9e32255-a8a8-4760-8f4c-f0f99f69daca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853205091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2853205091
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1547664236
Short name T152
Test name
Test status
Simulation time 286533781 ps
CPU time 2.81 seconds
Started Mar 19 03:14:40 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 221904 kb
Host smart-7ad18afe-b8e9-4ea6-b595-73c0af5797a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547664236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1547664236
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2009102012
Short name T243
Test name
Test status
Simulation time 47063019 ps
CPU time 1.77 seconds
Started Mar 19 02:48:37 PM PDT 24
Finished Mar 19 02:48:39 PM PDT 24
Peak memory 222028 kb
Host smart-5dd41e0b-7a61-4386-901a-b3dd6ef677ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009102012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2009102012
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1727312806
Short name T1710
Test name
Test status
Simulation time 34243612 ps
CPU time 1.16 seconds
Started Mar 19 03:14:38 PM PDT 24
Finished Mar 19 03:14:40 PM PDT 24
Peak memory 217824 kb
Host smart-93390e70-d155-4424-833e-1199274286cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727312806 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1727312806
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.421038550
Short name T1984
Test name
Test status
Simulation time 31702894 ps
CPU time 1.22 seconds
Started Mar 19 02:48:52 PM PDT 24
Finished Mar 19 02:48:54 PM PDT 24
Peak memory 218880 kb
Host smart-4bf56603-076e-4572-a812-9e1a478712b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421038550 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.421038550
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1594427398
Short name T1992
Test name
Test status
Simulation time 42712213 ps
CPU time 0.77 seconds
Started Mar 19 03:14:37 PM PDT 24
Finished Mar 19 03:14:38 PM PDT 24
Peak memory 209216 kb
Host smart-6fc8bd83-ecf7-4961-9608-feaf999fb6ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594427398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1594427398
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2146311230
Short name T1843
Test name
Test status
Simulation time 17583300 ps
CPU time 0.98 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 208888 kb
Host smart-3ccf9a4b-91df-4265-a7bf-75d428f66257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146311230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2146311230
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3513669813
Short name T1872
Test name
Test status
Simulation time 207628030 ps
CPU time 1.55 seconds
Started Mar 19 02:48:48 PM PDT 24
Finished Mar 19 02:48:50 PM PDT 24
Peak memory 209516 kb
Host smart-49cb2f29-e74b-4851-bf44-8ab61cf23c16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513669813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3513669813
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3864721173
Short name T1888
Test name
Test status
Simulation time 26552296 ps
CPU time 0.98 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:40 PM PDT 24
Peak memory 209412 kb
Host smart-d99a3334-4566-477d-b460-668103eb3438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864721173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3864721173
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1648673231
Short name T1894
Test name
Test status
Simulation time 115032590 ps
CPU time 2 seconds
Started Mar 19 03:14:40 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 217792 kb
Host smart-b9a49d35-f7be-4ce0-9107-bd9f754b0bc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648673231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1648673231
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3488847294
Short name T1723
Test name
Test status
Simulation time 45959362 ps
CPU time 1.64 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 217752 kb
Host smart-289c4d4e-6d20-49ca-99b6-7124afa6f785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488847294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3488847294
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1758345230
Short name T159
Test name
Test status
Simulation time 364626509 ps
CPU time 2.68 seconds
Started Mar 19 02:48:58 PM PDT 24
Finished Mar 19 02:49:01 PM PDT 24
Peak memory 217660 kb
Host smart-bf3561ce-b73b-4dac-9c6a-b3a11b0c300b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758345230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1758345230
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2506656658
Short name T1842
Test name
Test status
Simulation time 19487872 ps
CPU time 1.31 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:48:55 PM PDT 24
Peak memory 217684 kb
Host smart-e86389e1-ee3b-4be8-85f2-580bfb66b4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506656658 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2506656658
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2635497956
Short name T1966
Test name
Test status
Simulation time 16326794 ps
CPU time 1.33 seconds
Started Mar 19 03:14:46 PM PDT 24
Finished Mar 19 03:14:48 PM PDT 24
Peak memory 219440 kb
Host smart-1e6f9c2c-8bee-4434-a1b1-accc55adfa45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635497956 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2635497956
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2641122318
Short name T1886
Test name
Test status
Simulation time 48633692 ps
CPU time 0.93 seconds
Started Mar 19 02:48:38 PM PDT 24
Finished Mar 19 02:48:39 PM PDT 24
Peak memory 209364 kb
Host smart-6f270197-6654-4e90-8e0e-8c768ebbea98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641122318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2641122318
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2713970665
Short name T1762
Test name
Test status
Simulation time 14043417 ps
CPU time 1.01 seconds
Started Mar 19 03:14:42 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 209292 kb
Host smart-eaacec6d-0755-4b36-ba23-9ffab66d4bd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713970665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2713970665
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.284234705
Short name T1813
Test name
Test status
Simulation time 25682582 ps
CPU time 1.09 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:40 PM PDT 24
Peak memory 209448 kb
Host smart-881fea42-ac79-4b40-8db8-247354220c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284234705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.284234705
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3498671396
Short name T1805
Test name
Test status
Simulation time 24382893 ps
CPU time 1.39 seconds
Started Mar 19 02:48:46 PM PDT 24
Finished Mar 19 02:48:47 PM PDT 24
Peak memory 209436 kb
Host smart-8eea762d-cb83-4636-8ffb-66a354a3359c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498671396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3498671396
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.130651260
Short name T1774
Test name
Test status
Simulation time 184598747 ps
CPU time 2.95 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 217804 kb
Host smart-afeb2516-645c-4292-b084-1c2e0161d15e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130651260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.130651260
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.665612200
Short name T1951
Test name
Test status
Simulation time 424456836 ps
CPU time 3.04 seconds
Started Mar 19 02:48:42 PM PDT 24
Finished Mar 19 02:48:45 PM PDT 24
Peak memory 217716 kb
Host smart-0d81e6da-9da1-439f-a757-d2e0b2dd9b00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665612200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.665612200
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1514667719
Short name T1853
Test name
Test status
Simulation time 227051885 ps
CPU time 3.69 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 217604 kb
Host smart-71198542-2376-4f60-8974-310d06d91bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514667719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1514667719
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2040938197
Short name T1831
Test name
Test status
Simulation time 73324448 ps
CPU time 1.67 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 219324 kb
Host smart-7c7c1aae-b7a3-456c-a6af-cd11ac241fe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040938197 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2040938197
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.28636471
Short name T1703
Test name
Test status
Simulation time 56385065 ps
CPU time 1.15 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 217740 kb
Host smart-36302d3a-f353-42bd-a862-711026096bea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28636471 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.28636471
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4073003959
Short name T216
Test name
Test status
Simulation time 41126181 ps
CPU time 0.84 seconds
Started Mar 19 03:14:38 PM PDT 24
Finished Mar 19 03:14:39 PM PDT 24
Peak memory 209216 kb
Host smart-598d853f-8f35-468b-8acc-bf0e802e5787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073003959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4073003959
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.927277461
Short name T1742
Test name
Test status
Simulation time 13422972 ps
CPU time 1.03 seconds
Started Mar 19 02:48:35 PM PDT 24
Finished Mar 19 02:48:36 PM PDT 24
Peak memory 209320 kb
Host smart-5f5f0f3c-e1bd-4e30-a129-818222fc46e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927277461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.927277461
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2824613664
Short name T1963
Test name
Test status
Simulation time 46304599 ps
CPU time 1.13 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 209484 kb
Host smart-2e5063d6-09f4-482e-967a-546613355073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824613664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2824613664
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3459583666
Short name T226
Test name
Test status
Simulation time 16586342 ps
CPU time 1.29 seconds
Started Mar 19 03:14:40 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 209432 kb
Host smart-0e64fddd-6508-47e2-8449-7c3e94712737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459583666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3459583666
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3189160817
Short name T123
Test name
Test status
Simulation time 29721449 ps
CPU time 1.77 seconds
Started Mar 19 02:48:34 PM PDT 24
Finished Mar 19 02:48:36 PM PDT 24
Peak memory 218812 kb
Host smart-402aceb4-a323-4cf9-9833-c957df65beca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189160817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3189160817
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3847282647
Short name T1970
Test name
Test status
Simulation time 111076726 ps
CPU time 2.99 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 217752 kb
Host smart-3144fa92-52e9-4f5d-8cc5-1e29cf032e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847282647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3847282647
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3036508457
Short name T116
Test name
Test status
Simulation time 202775520 ps
CPU time 2.16 seconds
Started Mar 19 03:14:39 PM PDT 24
Finished Mar 19 03:14:41 PM PDT 24
Peak memory 221388 kb
Host smart-6cc357af-c5e0-4774-bba6-ddbf9caaa501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036508457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3036508457
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3584089307
Short name T147
Test name
Test status
Simulation time 114810141 ps
CPU time 3.04 seconds
Started Mar 19 02:48:44 PM PDT 24
Finished Mar 19 02:48:47 PM PDT 24
Peak memory 221836 kb
Host smart-9c999073-9cbf-423f-864c-111f6995d964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584089307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3584089307
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1212650564
Short name T1733
Test name
Test status
Simulation time 26382411 ps
CPU time 1.3 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 219932 kb
Host smart-6d86eb88-3c96-40b4-8ac2-757d3d1cb8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212650564 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1212650564
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4164657789
Short name T186
Test name
Test status
Simulation time 76378504 ps
CPU time 1.46 seconds
Started Mar 19 03:14:43 PM PDT 24
Finished Mar 19 03:14:44 PM PDT 24
Peak memory 217708 kb
Host smart-5537d65c-acb0-46ae-8ddb-431dfb4b112d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164657789 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.4164657789
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4225734180
Short name T1969
Test name
Test status
Simulation time 41270009 ps
CPU time 0.98 seconds
Started Mar 19 02:48:34 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 209368 kb
Host smart-1e409eff-5626-4f65-aaf0-26b9f989c481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225734180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.4225734180
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.786101500
Short name T218
Test name
Test status
Simulation time 13152629 ps
CPU time 1.07 seconds
Started Mar 19 03:14:42 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 209312 kb
Host smart-512e810a-61dc-4b0a-8b60-b323a63e2908
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786101500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.786101500
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2900370719
Short name T1812
Test name
Test status
Simulation time 320228779 ps
CPU time 1.35 seconds
Started Mar 19 02:48:36 PM PDT 24
Finished Mar 19 02:48:37 PM PDT 24
Peak memory 209404 kb
Host smart-903c0f80-c1ba-4563-9e79-37e1923a8cc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900370719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2900370719
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4262063971
Short name T1855
Test name
Test status
Simulation time 24138309 ps
CPU time 1.62 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 211500 kb
Host smart-b8f7e4ac-5db1-4300-9d52-ca5f118d831e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262063971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.4262063971
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1638785950
Short name T1956
Test name
Test status
Simulation time 137415032 ps
CPU time 2.16 seconds
Started Mar 19 02:48:47 PM PDT 24
Finished Mar 19 02:48:49 PM PDT 24
Peak memory 217728 kb
Host smart-07af5163-ac96-49a4-a3b6-0cdd936ca653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638785950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1638785950
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3442362204
Short name T1926
Test name
Test status
Simulation time 42778613 ps
CPU time 2.55 seconds
Started Mar 19 03:14:40 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 217864 kb
Host smart-455cdb22-ce36-47ef-ad2f-f1e1feb6c1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442362204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3442362204
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2818102680
Short name T1943
Test name
Test status
Simulation time 230983770 ps
CPU time 2.66 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:44 PM PDT 24
Peak memory 217612 kb
Host smart-be71a2be-f6ed-4f31-b4cb-a247f52422b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818102680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2818102680
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1425825352
Short name T217
Test name
Test status
Simulation time 103277578 ps
CPU time 1.08 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 209456 kb
Host smart-3107300d-203b-4c66-ad47-d551c68299c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425825352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1425825352
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2119304198
Short name T1868
Test name
Test status
Simulation time 146156331 ps
CPU time 1.78 seconds
Started Mar 19 03:13:56 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 209424 kb
Host smart-dc877e31-9920-4442-bfec-4fd98eadac23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119304198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2119304198
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2494230614
Short name T1726
Test name
Test status
Simulation time 134940132 ps
CPU time 1.29 seconds
Started Mar 19 03:13:57 PM PDT 24
Finished Mar 19 03:13:59 PM PDT 24
Peak memory 208520 kb
Host smart-e7893ecd-768a-4f11-b98d-27db60fc2f74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494230614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2494230614
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2561009365
Short name T1975
Test name
Test status
Simulation time 50928537 ps
CPU time 1.16 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:17 PM PDT 24
Peak memory 209344 kb
Host smart-a9aaab71-e009-46ab-a8f3-3b6dd5d71504
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561009365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2561009365
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.228630624
Short name T210
Test name
Test status
Simulation time 43086001 ps
CPU time 1.1 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 218048 kb
Host smart-f034ae42-bf8b-472f-948c-38f68f887bf1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228630624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.228630624
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.430538139
Short name T1721
Test name
Test status
Simulation time 73812913 ps
CPU time 1.08 seconds
Started Mar 19 03:14:01 PM PDT 24
Finished Mar 19 03:14:03 PM PDT 24
Peak memory 209828 kb
Host smart-daac5e76-fec1-47bd-a1da-09693f84b117
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430538139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.430538139
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3517088765
Short name T1840
Test name
Test status
Simulation time 40206417 ps
CPU time 1.55 seconds
Started Mar 19 02:48:23 PM PDT 24
Finished Mar 19 02:48:24 PM PDT 24
Peak memory 219728 kb
Host smart-6b20d600-f61e-406a-9cec-8121c460c236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517088765 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3517088765
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4219368703
Short name T1714
Test name
Test status
Simulation time 61477467 ps
CPU time 1.27 seconds
Started Mar 19 03:13:56 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 218992 kb
Host smart-27c85c04-fa88-4c8c-8b82-5f724bd150db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219368703 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.4219368703
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1716886789
Short name T1777
Test name
Test status
Simulation time 39346919 ps
CPU time 0.94 seconds
Started Mar 19 03:13:59 PM PDT 24
Finished Mar 19 03:14:00 PM PDT 24
Peak memory 208960 kb
Host smart-88264496-3bb3-4d21-8168-77449a6ddd7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716886789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1716886789
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2555102347
Short name T1909
Test name
Test status
Simulation time 12737869 ps
CPU time 0.94 seconds
Started Mar 19 02:48:23 PM PDT 24
Finished Mar 19 02:48:25 PM PDT 24
Peak memory 209368 kb
Host smart-f9a1167c-f8d2-493c-9a50-ea2087c1d668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555102347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2555102347
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.207233442
Short name T1907
Test name
Test status
Simulation time 21096250 ps
CPU time 0.94 seconds
Started Mar 19 03:14:08 PM PDT 24
Finished Mar 19 03:14:09 PM PDT 24
Peak memory 207908 kb
Host smart-31050a30-8f13-4bb7-91d7-1add804b829f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207233442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.207233442
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2255252348
Short name T1780
Test name
Test status
Simulation time 88055529 ps
CPU time 1.68 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 209316 kb
Host smart-6348511f-c755-4f73-ba0a-e16ad187eb19
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255252348 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2255252348
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1527083761
Short name T1782
Test name
Test status
Simulation time 1836935534 ps
CPU time 7.73 seconds
Started Mar 19 03:13:57 PM PDT 24
Finished Mar 19 03:14:05 PM PDT 24
Peak memory 209124 kb
Host smart-d232a53e-64fd-4a5e-a606-270646955050
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527083761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1527083761
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2100925582
Short name T1931
Test name
Test status
Simulation time 1967887091 ps
CPU time 16.63 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:37 PM PDT 24
Peak memory 209140 kb
Host smart-ad92735a-3c3f-45ed-a0c8-b50d77689f58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100925582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2100925582
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.204645796
Short name T1858
Test name
Test status
Simulation time 806437767 ps
CPU time 7.04 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 209348 kb
Host smart-d17aa0c6-453a-4ff0-8749-f5f4593d0a16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204645796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.204645796
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.935625621
Short name T1976
Test name
Test status
Simulation time 2674612814 ps
CPU time 16.99 seconds
Started Mar 19 03:14:08 PM PDT 24
Finished Mar 19 03:14:25 PM PDT 24
Peak memory 208404 kb
Host smart-6247a648-2c11-42a9-97eb-72b1ccf8eac5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935625621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.935625621
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2344776648
Short name T1708
Test name
Test status
Simulation time 382966880 ps
CPU time 2.92 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 210852 kb
Host smart-91db3c6e-cbef-4235-8d26-a4fc5fecf735
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344776648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2344776648
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3757110472
Short name T1952
Test name
Test status
Simulation time 94364476 ps
CPU time 2.75 seconds
Started Mar 19 03:14:01 PM PDT 24
Finished Mar 19 03:14:05 PM PDT 24
Peak memory 210868 kb
Host smart-5287af04-1c49-4f41-b024-4e8df07ea8fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757110472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3757110472
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3681006221
Short name T140
Test name
Test status
Simulation time 522114835 ps
CPU time 4.02 seconds
Started Mar 19 03:13:56 PM PDT 24
Finished Mar 19 03:14:00 PM PDT 24
Peak memory 219164 kb
Host smart-c15ec77f-462b-46de-adde-a7b2e9f63f99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368100
6221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3681006221
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3793287699
Short name T1938
Test name
Test status
Simulation time 131675806 ps
CPU time 2.38 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 217624 kb
Host smart-18189f7d-e9a5-4fae-95c8-5dcb34b3faa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379328
7699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3793287699
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2479572976
Short name T1799
Test name
Test status
Simulation time 347281409 ps
CPU time 2.43 seconds
Started Mar 19 03:13:59 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 209400 kb
Host smart-315f1fca-5375-4991-b3ea-71be6638ba7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479572976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2479572976
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4185092437
Short name T1904
Test name
Test status
Simulation time 441042526 ps
CPU time 1.76 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 209344 kb
Host smart-561a70d7-48a0-418f-998e-670d45f1ea68
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185092437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.4185092437
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3082770457
Short name T1749
Test name
Test status
Simulation time 31047977 ps
CPU time 1.23 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 209452 kb
Host smart-1097415b-a4a1-41ae-9cef-6758a590c0b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082770457 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3082770457
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.525534134
Short name T1793
Test name
Test status
Simulation time 41330849 ps
CPU time 1.36 seconds
Started Mar 19 03:13:56 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 209412 kb
Host smart-77ab79e3-0e65-4b82-8429-3a4d6d61233a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525534134 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.525534134
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.184958271
Short name T1798
Test name
Test status
Simulation time 30451090 ps
CPU time 1.2 seconds
Started Mar 19 03:14:01 PM PDT 24
Finished Mar 19 03:14:03 PM PDT 24
Peak memory 209492 kb
Host smart-92f4b65c-e2e3-49f2-a77b-1971892c3f81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184958271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.184958271
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3100663920
Short name T222
Test name
Test status
Simulation time 21845261 ps
CPU time 1.23 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:20 PM PDT 24
Peak memory 209464 kb
Host smart-c35cd85a-2c55-41c6-89c4-10113a5e0858
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100663920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3100663920
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1029271029
Short name T1731
Test name
Test status
Simulation time 314418404 ps
CPU time 4.36 seconds
Started Mar 19 03:13:55 PM PDT 24
Finished Mar 19 03:14:00 PM PDT 24
Peak memory 217812 kb
Host smart-d9f69b18-a314-4318-aacb-64103aaa5ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029271029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1029271029
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3840734523
Short name T145
Test name
Test status
Simulation time 402361466 ps
CPU time 3.97 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 218364 kb
Host smart-8224bb20-6682-4496-94d4-a89a36838fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840734523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3840734523
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2650777170
Short name T162
Test name
Test status
Simulation time 140762689 ps
CPU time 3.44 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 222268 kb
Host smart-a182887b-c7d0-4837-ac92-fdf95ee2171a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650777170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2650777170
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2844557011
Short name T154
Test name
Test status
Simulation time 106645794 ps
CPU time 3.03 seconds
Started Mar 19 03:13:57 PM PDT 24
Finished Mar 19 03:14:00 PM PDT 24
Peak memory 222312 kb
Host smart-fcf4852f-804e-4c5d-9a6e-30523f1138eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844557011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2844557011
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1606827698
Short name T209
Test name
Test status
Simulation time 14502602 ps
CPU time 1.12 seconds
Started Mar 19 03:14:12 PM PDT 24
Finished Mar 19 03:14:13 PM PDT 24
Peak memory 209388 kb
Host smart-1f2582fb-5751-4647-a9f7-d3cd9e6e85a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606827698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1606827698
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2820342082
Short name T1942
Test name
Test status
Simulation time 40342409 ps
CPU time 1.86 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 209376 kb
Host smart-ebbb572c-0112-4bc6-9843-9c8bab4d3e12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820342082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2820342082
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.147334932
Short name T1839
Test name
Test status
Simulation time 46960688 ps
CPU time 1.42 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 209208 kb
Host smart-012a1925-ee4d-45ca-9c72-22c3d25e0e59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147334932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.147334932
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1937117668
Short name T1859
Test name
Test status
Simulation time 203764218 ps
CPU time 2.01 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:20 PM PDT 24
Peak memory 209036 kb
Host smart-20f4d0d7-82db-4cb1-9b43-70ffa00533b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937117668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1937117668
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1532917847
Short name T214
Test name
Test status
Simulation time 61108846 ps
CPU time 1.1 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 218160 kb
Host smart-05ff97de-25ef-49db-ac0f-7b9d619a89c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532917847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1532917847
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3329334676
Short name T1913
Test name
Test status
Simulation time 17005956 ps
CPU time 1.15 seconds
Started Mar 19 03:14:08 PM PDT 24
Finished Mar 19 03:14:10 PM PDT 24
Peak memory 210252 kb
Host smart-3b7804e1-e231-424a-80c1-e2feec0a6c62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329334676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3329334676
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1708020545
Short name T1934
Test name
Test status
Simulation time 24028283 ps
CPU time 1.51 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:19 PM PDT 24
Peak memory 217548 kb
Host smart-8788a1a9-e1ab-4f8c-97b8-b6f4bc295281
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708020545 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1708020545
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.52672799
Short name T1852
Test name
Test status
Simulation time 94986120 ps
CPU time 1.6 seconds
Started Mar 19 03:14:12 PM PDT 24
Finished Mar 19 03:14:13 PM PDT 24
Peak memory 217724 kb
Host smart-d6b8d455-6832-4374-9390-13acfd403085
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52672799 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.52672799
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3057688703
Short name T1776
Test name
Test status
Simulation time 57657143 ps
CPU time 0.83 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 209216 kb
Host smart-590769af-47c3-4992-bffb-2c43dca9a7cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057688703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3057688703
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4242108858
Short name T1921
Test name
Test status
Simulation time 19409189 ps
CPU time 0.84 seconds
Started Mar 19 03:14:11 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 209192 kb
Host smart-8e772360-d676-4f8c-b8fd-746327a2f652
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242108858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4242108858
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2007642386
Short name T1905
Test name
Test status
Simulation time 36782554 ps
CPU time 1.62 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 209336 kb
Host smart-7eac6f27-d72c-402b-8488-56abcb238100
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007642386 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2007642386
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.539683602
Short name T1790
Test name
Test status
Simulation time 38799690 ps
CPU time 1.06 seconds
Started Mar 19 03:14:13 PM PDT 24
Finished Mar 19 03:14:14 PM PDT 24
Peak memory 207932 kb
Host smart-038c0cd2-22fe-4a19-924b-0d8a36b0167c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539683602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.539683602
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2917189166
Short name T165
Test name
Test status
Simulation time 717288962 ps
CPU time 6.98 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:36 PM PDT 24
Peak memory 209080 kb
Host smart-ead4e8c6-5d38-4d36-9b52-814233974d16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917189166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2917189166
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3725510622
Short name T1745
Test name
Test status
Simulation time 788094972 ps
CPU time 8.27 seconds
Started Mar 19 03:14:12 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 209344 kb
Host smart-867ced4b-c45c-413d-9027-4724ea667be2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725510622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3725510622
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3170102631
Short name T1939
Test name
Test status
Simulation time 347634415 ps
CPU time 9.12 seconds
Started Mar 19 03:14:08 PM PDT 24
Finished Mar 19 03:14:17 PM PDT 24
Peak memory 209148 kb
Host smart-a6e6700d-3d32-4dd2-a787-316d0a6b68f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170102631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3170102631
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3866637232
Short name T1725
Test name
Test status
Simulation time 1375147087 ps
CPU time 5.23 seconds
Started Mar 19 02:48:22 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 208516 kb
Host smart-15b5ccef-dc43-4f90-8026-ba8f86969a96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866637232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3866637232
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1942849495
Short name T1797
Test name
Test status
Simulation time 182703606 ps
CPU time 1.77 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 210952 kb
Host smart-ee59522e-e014-403b-803e-d5b283126ab6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942849495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1942849495
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2990861738
Short name T1936
Test name
Test status
Simulation time 333293180 ps
CPU time 2.7 seconds
Started Mar 19 03:13:55 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 210752 kb
Host smart-ff1460a2-4163-4f9a-856d-5fa30f79dc5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990861738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2990861738
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1673469187
Short name T1947
Test name
Test status
Simulation time 222949534 ps
CPU time 2.1 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 218644 kb
Host smart-02eef5d1-dfd6-40c9-a67a-91965b6f1e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167346
9187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1673469187
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2023044946
Short name T1902
Test name
Test status
Simulation time 115310542 ps
CPU time 1.56 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 219472 kb
Host smart-84451000-1cad-4090-a4af-c77fbe3d0649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202304
4946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2023044946
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2681543934
Short name T1701
Test name
Test status
Simulation time 97854158 ps
CPU time 1.78 seconds
Started Mar 19 03:13:55 PM PDT 24
Finished Mar 19 03:13:56 PM PDT 24
Peak memory 209520 kb
Host smart-d241e498-9bed-4aca-b2eb-056b599c3866
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681543934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2681543934
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.520818619
Short name T1848
Test name
Test status
Simulation time 123594854 ps
CPU time 2.32 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 209372 kb
Host smart-08e492c4-a13a-45d6-aa2e-d73852a1ef5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520818619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.520818619
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1540056575
Short name T1845
Test name
Test status
Simulation time 45573884 ps
CPU time 1.46 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:20 PM PDT 24
Peak memory 209424 kb
Host smart-09da127f-8150-494c-af4a-46858f745c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540056575 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1540056575
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.191181857
Short name T125
Test name
Test status
Simulation time 45788863 ps
CPU time 1.38 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 209380 kb
Host smart-6dd1515b-08cf-4ccb-aee2-992db031bf0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191181857 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.191181857
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1418544866
Short name T1911
Test name
Test status
Simulation time 49443655 ps
CPU time 0.95 seconds
Started Mar 19 03:14:12 PM PDT 24
Finished Mar 19 03:14:13 PM PDT 24
Peak memory 209460 kb
Host smart-4039e538-3d35-4e97-9ebd-2f5a98d5965d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418544866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1418544866
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3943569605
Short name T1747
Test name
Test status
Simulation time 100252644 ps
CPU time 1.41 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:19 PM PDT 24
Peak memory 211552 kb
Host smart-5398b327-e272-4ded-9a1b-6fdaa99ff720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943569605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3943569605
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1855865874
Short name T1765
Test name
Test status
Simulation time 48240567 ps
CPU time 2.16 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 217744 kb
Host smart-a1c3911c-7918-46b4-afe0-dbd31761fae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855865874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1855865874
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2516150170
Short name T1770
Test name
Test status
Simulation time 71903316 ps
CPU time 1.61 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 218252 kb
Host smart-2f7f2c0b-8902-4143-aed9-e3c596cbf4c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516150170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2516150170
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3650319258
Short name T158
Test name
Test status
Simulation time 160788645 ps
CPU time 2.27 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 222056 kb
Host smart-d2a17d38-998f-44c1-afd7-7b2f9901436e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650319258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3650319258
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.427513688
Short name T135
Test name
Test status
Simulation time 110292753 ps
CPU time 2.69 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 222092 kb
Host smart-c73ecf2d-4136-44c1-b8a7-d8ca3811139f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427513688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.427513688
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.652966261
Short name T1923
Test name
Test status
Simulation time 24913160 ps
CPU time 1.14 seconds
Started Mar 19 02:48:19 PM PDT 24
Finished Mar 19 02:48:20 PM PDT 24
Peak memory 209380 kb
Host smart-8feb1652-eda3-4738-9e98-ed387c91e77f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652966261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.652966261
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.735627968
Short name T178
Test name
Test status
Simulation time 29429961 ps
CPU time 1.11 seconds
Started Mar 19 03:14:13 PM PDT 24
Finished Mar 19 03:14:15 PM PDT 24
Peak memory 209376 kb
Host smart-fd84f34c-b32a-43c9-be9c-e1e4d655a3a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735627968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.735627968
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1917413741
Short name T1891
Test name
Test status
Simulation time 1223871981 ps
CPU time 1.89 seconds
Started Mar 19 02:48:19 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 209264 kb
Host smart-37a530f8-5912-493c-92a1-52ac168566f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917413741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1917413741
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.776776233
Short name T1738
Test name
Test status
Simulation time 144260943 ps
CPU time 1.67 seconds
Started Mar 19 03:14:08 PM PDT 24
Finished Mar 19 03:14:09 PM PDT 24
Peak memory 209288 kb
Host smart-3b65bc4f-faff-4eb0-80df-3c7b35a8410a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776776233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.776776233
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1489033586
Short name T1900
Test name
Test status
Simulation time 36314084 ps
CPU time 1.01 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:10 PM PDT 24
Peak memory 209912 kb
Host smart-90e6c176-15e8-480d-b388-c1771a90638b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489033586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1489033586
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3380515501
Short name T1869
Test name
Test status
Simulation time 14794644 ps
CPU time 1.22 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 218204 kb
Host smart-994d7681-4102-4715-87de-cb835ccee04d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380515501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3380515501
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1838904041
Short name T1764
Test name
Test status
Simulation time 32750252 ps
CPU time 1.76 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 218684 kb
Host smart-fa9372ad-533a-47d6-967d-e05332135b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838904041 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1838904041
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3525038778
Short name T1871
Test name
Test status
Simulation time 33111913 ps
CPU time 1 seconds
Started Mar 19 03:14:11 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 217736 kb
Host smart-ecb660d1-0541-4b1e-a29b-1319dcf5ce80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525038778 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3525038778
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.175001196
Short name T1968
Test name
Test status
Simulation time 141478063 ps
CPU time 0.77 seconds
Started Mar 19 03:14:10 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 209188 kb
Host smart-62508aca-ca7d-4afe-a81f-a0cc0b18309f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175001196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.175001196
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2424951961
Short name T1741
Test name
Test status
Simulation time 42277047 ps
CPU time 0.81 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 209224 kb
Host smart-dca1f0ba-e65b-4a19-bf62-d4d197f5c767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424951961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2424951961
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1417267403
Short name T1810
Test name
Test status
Simulation time 92356178 ps
CPU time 1.55 seconds
Started Mar 19 03:14:10 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 209324 kb
Host smart-13a5f42d-98a9-45ff-88cf-3ee3535e3820
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417267403 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1417267403
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3972841347
Short name T1964
Test name
Test status
Simulation time 28088599 ps
CPU time 1.33 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 209372 kb
Host smart-d8a26f42-9366-42da-a299-02f9784a3059
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972841347 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3972841347
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1278585218
Short name T1729
Test name
Test status
Simulation time 7187948978 ps
CPU time 26.11 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:56 PM PDT 24
Peak memory 209424 kb
Host smart-dabeaf6f-d884-4c66-baf7-ff18e0aa9127
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278585218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1278585218
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3047425157
Short name T1899
Test name
Test status
Simulation time 352628665 ps
CPU time 8.34 seconds
Started Mar 19 03:14:10 PM PDT 24
Finished Mar 19 03:14:18 PM PDT 24
Peak memory 209136 kb
Host smart-e4c714d0-ead9-46d4-95c5-99846d5857ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047425157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3047425157
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1796553976
Short name T1961
Test name
Test status
Simulation time 608036081 ps
CPU time 6.98 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 209328 kb
Host smart-25c6479f-3712-4dee-ad35-f38d2cee081d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796553976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1796553976
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3407100246
Short name T1895
Test name
Test status
Simulation time 961837051 ps
CPU time 4.42 seconds
Started Mar 19 03:14:10 PM PDT 24
Finished Mar 19 03:14:14 PM PDT 24
Peak memory 208480 kb
Host smart-ad0e951b-7d28-49c4-9c94-4edd6a9c473f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407100246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3407100246
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2193703209
Short name T1928
Test name
Test status
Simulation time 416143974 ps
CPU time 2.88 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 210656 kb
Host smart-0231678c-c25a-441b-867d-8e37d598387f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193703209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2193703209
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2485003870
Short name T1720
Test name
Test status
Simulation time 114917892 ps
CPU time 3.32 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 210724 kb
Host smart-80204b45-c09c-4856-a3d2-f4b88686f07f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485003870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2485003870
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1581453910
Short name T1838
Test name
Test status
Simulation time 497627105 ps
CPU time 3.17 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 221012 kb
Host smart-3a1f5fef-b200-47f6-9a3b-d759aeb06f72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158145
3910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1581453910
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3271113412
Short name T1707
Test name
Test status
Simulation time 187622638 ps
CPU time 2.44 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 218708 kb
Host smart-539812fa-9273-482d-9e79-24f6e93a0576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327111
3412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3271113412
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1252247342
Short name T1804
Test name
Test status
Simulation time 68105884 ps
CPU time 2.24 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 209396 kb
Host smart-885db09c-c8b7-4926-abbb-ff58b395f525
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252247342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1252247342
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2018799441
Short name T1715
Test name
Test status
Simulation time 822430808 ps
CPU time 2.92 seconds
Started Mar 19 03:14:12 PM PDT 24
Finished Mar 19 03:14:15 PM PDT 24
Peak memory 209352 kb
Host smart-dba1a42a-9c9f-43b7-bb1e-24cf6740320c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018799441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2018799441
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2083679164
Short name T1980
Test name
Test status
Simulation time 20109184 ps
CPU time 1.18 seconds
Started Mar 19 03:14:11 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 217612 kb
Host smart-e19947d5-c4af-4c08-9db7-529e76843d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083679164 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2083679164
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2642397706
Short name T1820
Test name
Test status
Simulation time 136328412 ps
CPU time 1.24 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 209424 kb
Host smart-c5ab3414-b8bc-4cea-95d0-17c05b1c0c6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642397706 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2642397706
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4086495781
Short name T1914
Test name
Test status
Simulation time 33633790 ps
CPU time 1.25 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:18 PM PDT 24
Peak memory 209440 kb
Host smart-69d79d72-d299-4ce8-87d3-e87c95ff1495
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086495781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.4086495781
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.740534248
Short name T1803
Test name
Test status
Simulation time 143447433 ps
CPU time 1.33 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:10 PM PDT 24
Peak memory 209544 kb
Host smart-73c3c36c-56c8-4fb5-b2db-678e20c3dcc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740534248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.740534248
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.164270548
Short name T1740
Test name
Test status
Simulation time 27081707 ps
CPU time 1.76 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:24 PM PDT 24
Peak memory 218776 kb
Host smart-4888d188-3c06-4016-abd0-007519e02621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164270548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.164270548
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1835802324
Short name T1801
Test name
Test status
Simulation time 534544931 ps
CPU time 1.8 seconds
Started Mar 19 03:14:11 PM PDT 24
Finished Mar 19 03:14:13 PM PDT 24
Peak memory 217784 kb
Host smart-976bda03-3220-40c3-a32c-cd542905c59d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835802324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1835802324
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2604970171
Short name T1901
Test name
Test status
Simulation time 42241135 ps
CPU time 1.98 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:21 PM PDT 24
Peak memory 221952 kb
Host smart-f13bedcb-2cc0-471d-b3d6-3bee0a50178f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604970171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2604970171
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2416516870
Short name T1919
Test name
Test status
Simulation time 55962886 ps
CPU time 1.34 seconds
Started Mar 19 03:14:18 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 219512 kb
Host smart-983d10a7-cd6c-43f2-9905-eb5904b12e65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416516870 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2416516870
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3868210786
Short name T1892
Test name
Test status
Simulation time 372151133 ps
CPU time 1.86 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 219156 kb
Host smart-f097da72-cb89-4f29-8b38-b5f688b3530c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868210786 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3868210786
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2539891398
Short name T1829
Test name
Test status
Simulation time 40455563 ps
CPU time 0.91 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 209384 kb
Host smart-20298716-8a09-4b93-9807-eafe7798e48e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539891398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2539891398
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.911502029
Short name T1971
Test name
Test status
Simulation time 60592189 ps
CPU time 0.88 seconds
Started Mar 19 03:14:16 PM PDT 24
Finished Mar 19 03:14:18 PM PDT 24
Peak memory 209068 kb
Host smart-f5232058-597f-4caf-b587-2ea41d14a391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911502029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.911502029
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1523132931
Short name T1897
Test name
Test status
Simulation time 52255364 ps
CPU time 1.09 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:25 PM PDT 24
Peak memory 209112 kb
Host smart-fca2102d-b7a4-4f77-8769-2b6c79351d75
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523132931 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1523132931
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4000502572
Short name T1860
Test name
Test status
Simulation time 1881341616 ps
CPU time 2.78 seconds
Started Mar 19 03:14:23 PM PDT 24
Finished Mar 19 03:14:26 PM PDT 24
Peak memory 209316 kb
Host smart-25847a3c-3468-4409-9663-6d491e702e04
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000502572 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4000502572
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.201904353
Short name T1903
Test name
Test status
Simulation time 433347705 ps
CPU time 4.97 seconds
Started Mar 19 02:48:17 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 209204 kb
Host smart-7668df0f-152b-4c72-bca3-8fd8ce4e5a7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201904353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.201904353
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3869831024
Short name T1850
Test name
Test status
Simulation time 684324837 ps
CPU time 8.27 seconds
Started Mar 19 03:14:24 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 209200 kb
Host smart-2f259aad-409a-4e61-846e-eb52ae913b51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869831024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3869831024
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1613352609
Short name T1993
Test name
Test status
Simulation time 1213260136 ps
CPU time 10.77 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 207824 kb
Host smart-52043031-a39e-4c19-9ef2-bdd7c5966c0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613352609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1613352609
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.770262947
Short name T130
Test name
Test status
Simulation time 4287833893 ps
CPU time 7.3 seconds
Started Mar 19 03:14:24 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 209276 kb
Host smart-3a146373-3ece-4038-b919-8039cc154f6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770262947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.770262947
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.191149586
Short name T1925
Test name
Test status
Simulation time 179336060 ps
CPU time 2.42 seconds
Started Mar 19 02:48:19 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 210896 kb
Host smart-bd9afe16-e8b8-4b53-8e13-33325e56b0fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191149586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.191149586
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.384595480
Short name T1979
Test name
Test status
Simulation time 104185544 ps
CPU time 1.81 seconds
Started Mar 19 03:14:11 PM PDT 24
Finished Mar 19 03:14:13 PM PDT 24
Peak memory 210916 kb
Host smart-2cedfcd0-bd49-4461-b366-a19e0c7bc733
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384595480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.384595480
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1180591090
Short name T1906
Test name
Test status
Simulation time 677140819 ps
CPU time 2.93 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:19 PM PDT 24
Peak memory 218936 kb
Host smart-bfad9d71-ac0f-47be-9595-23e9cf6db27f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118059
1090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1180591090
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3453090208
Short name T1833
Test name
Test status
Simulation time 49771234 ps
CPU time 2.12 seconds
Started Mar 19 03:14:17 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 219224 kb
Host smart-2560f830-78a3-4fc9-a24b-04b665358137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345309
0208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3453090208
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3197147017
Short name T1832
Test name
Test status
Simulation time 1053063142 ps
CPU time 2.17 seconds
Started Mar 19 03:14:09 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 209380 kb
Host smart-a737f2df-a296-44b6-ba87-b603631dbfc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197147017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3197147017
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3739960001
Short name T1775
Test name
Test status
Simulation time 33771130 ps
CPU time 1.1 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 209332 kb
Host smart-be64eb31-173b-4629-a0e2-b88c866a29c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739960001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3739960001
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.256424064
Short name T1957
Test name
Test status
Simulation time 45272067 ps
CPU time 1.06 seconds
Started Mar 19 03:14:21 PM PDT 24
Finished Mar 19 03:14:22 PM PDT 24
Peak memory 208988 kb
Host smart-ab14b79c-bbd0-475e-9ba7-b378d75bd7d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256424064 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.256424064
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2927099802
Short name T1815
Test name
Test status
Simulation time 338650729 ps
CPU time 1.38 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:25 PM PDT 24
Peak memory 209320 kb
Host smart-11f491c3-cbc7-461c-ae20-85cc79f8d7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927099802 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2927099802
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1016127204
Short name T1981
Test name
Test status
Simulation time 26007660 ps
CPU time 1.41 seconds
Started Mar 19 02:48:22 PM PDT 24
Finished Mar 19 02:48:24 PM PDT 24
Peak memory 209428 kb
Host smart-983f5022-748d-49b5-b721-9ce96646dd73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016127204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1016127204
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2587194951
Short name T1766
Test name
Test status
Simulation time 141446326 ps
CPU time 1.7 seconds
Started Mar 19 03:14:18 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 209472 kb
Host smart-caa941d5-498f-494b-8fdb-2d278148ceca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587194951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2587194951
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1856408913
Short name T136
Test name
Test status
Simulation time 133386696 ps
CPU time 4.88 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 217672 kb
Host smart-ae1680b1-8604-49ca-a307-7de2f591a6da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856408913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1856408913
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2567633959
Short name T1846
Test name
Test status
Simulation time 87339815 ps
CPU time 1.68 seconds
Started Mar 19 03:14:20 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 217788 kb
Host smart-6729c7e1-dfa6-4966-b052-fd5711a85bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567633959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2567633959
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.731901704
Short name T153
Test name
Test status
Simulation time 44848204 ps
CPU time 1.84 seconds
Started Mar 19 03:14:18 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 221760 kb
Host smart-1d4668e9-b0c6-4a4d-87ca-daff1e241bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731901704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.731901704
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2050922594
Short name T1807
Test name
Test status
Simulation time 67601642 ps
CPU time 1.46 seconds
Started Mar 19 03:14:20 PM PDT 24
Finished Mar 19 03:14:22 PM PDT 24
Peak memory 219488 kb
Host smart-d9dcdee2-2cc2-4d65-b2e7-31f87050a8d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050922594 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2050922594
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2345833392
Short name T1753
Test name
Test status
Simulation time 23751416 ps
CPU time 1.68 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 219604 kb
Host smart-d44c3064-a0db-4b1a-ac88-7da4688e40ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345833392 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2345833392
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1382854611
Short name T1916
Test name
Test status
Simulation time 36252665 ps
CPU time 0.87 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 208604 kb
Host smart-7e3a8aaa-0d0d-4496-9c36-663a6d900444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382854611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1382854611
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2177952549
Short name T1862
Test name
Test status
Simulation time 31828605 ps
CPU time 1.08 seconds
Started Mar 19 03:14:19 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 209348 kb
Host smart-936fdc74-169e-46fe-9932-b3b013dd0665
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177952549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2177952549
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2994112122
Short name T1870
Test name
Test status
Simulation time 24868783 ps
CPU time 1.29 seconds
Started Mar 19 02:48:22 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 208032 kb
Host smart-047c11b9-b44b-4536-bc45-022694f83de3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994112122 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2994112122
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4237710724
Short name T1712
Test name
Test status
Simulation time 20728638 ps
CPU time 0.91 seconds
Started Mar 19 03:14:18 PM PDT 24
Finished Mar 19 03:14:19 PM PDT 24
Peak memory 209240 kb
Host smart-f4b48d84-fa1c-40aa-9596-530074ba6cb8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237710724 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4237710724
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2887527727
Short name T1750
Test name
Test status
Simulation time 722864564 ps
CPU time 7.4 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:38 PM PDT 24
Peak memory 207724 kb
Host smart-88fc4d36-8da6-4520-88e6-95230b9e4ea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887527727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2887527727
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3102624685
Short name T1965
Test name
Test status
Simulation time 189668003 ps
CPU time 2.74 seconds
Started Mar 19 03:14:16 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 208168 kb
Host smart-64761eb6-7a70-4a9c-9b32-de19c8932dfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102624685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3102624685
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2549237210
Short name T1889
Test name
Test status
Simulation time 1303704851 ps
CPU time 5.17 seconds
Started Mar 19 03:14:19 PM PDT 24
Finished Mar 19 03:14:25 PM PDT 24
Peak memory 209040 kb
Host smart-e7b0c274-acbd-4337-a530-f0d1ee715cfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549237210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2549237210
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.999566157
Short name T1735
Test name
Test status
Simulation time 1345508547 ps
CPU time 12.82 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:44 PM PDT 24
Peak memory 208428 kb
Host smart-215388d1-cbc6-4f43-affd-84aeb1322ad5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999566157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.999566157
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4066103714
Short name T1821
Test name
Test status
Simulation time 546365532 ps
CPU time 3.23 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 210744 kb
Host smart-852ff59d-5939-4aa4-af9f-5346b2e6c829
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066103714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4066103714
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.584714509
Short name T1711
Test name
Test status
Simulation time 106422295 ps
CPU time 3.43 seconds
Started Mar 19 03:14:16 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 210972 kb
Host smart-ed657389-c445-49b1-84a5-4f72d89d6b97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584714509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.584714509
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.762546127
Short name T1960
Test name
Test status
Simulation time 188778077 ps
CPU time 3.34 seconds
Started Mar 19 03:14:18 PM PDT 24
Finished Mar 19 03:14:22 PM PDT 24
Peak memory 217716 kb
Host smart-98ab4126-8b2d-48e2-b536-cafecbac83ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762546
127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.762546127
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3369179361
Short name T1986
Test name
Test status
Simulation time 64377835 ps
CPU time 2.11 seconds
Started Mar 19 02:48:23 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 209344 kb
Host smart-c028ea0c-d6be-48d5-a9dc-d97c8f4f124f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369179361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3369179361
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.720603867
Short name T1851
Test name
Test status
Simulation time 554038832 ps
CPU time 4.05 seconds
Started Mar 19 03:14:19 PM PDT 24
Finished Mar 19 03:14:24 PM PDT 24
Peak memory 209352 kb
Host smart-d6966293-9c5c-4f48-8140-819dd2c0e1cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720603867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.720603867
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2275371298
Short name T1808
Test name
Test status
Simulation time 309543736 ps
CPU time 1.29 seconds
Started Mar 19 03:14:19 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 211340 kb
Host smart-d43718ca-a4db-4f4a-983b-2918659fc7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275371298 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2275371298
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3226156632
Short name T1756
Test name
Test status
Simulation time 21164846 ps
CPU time 1.09 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 209536 kb
Host smart-0202a836-b534-4ed7-8bc3-fbdcc8c49a93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226156632 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3226156632
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1594259704
Short name T1824
Test name
Test status
Simulation time 23840437 ps
CPU time 1.26 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 211296 kb
Host smart-8dad87dc-2077-4781-b4a3-f4a0f853291c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594259704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1594259704
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.860428563
Short name T1929
Test name
Test status
Simulation time 94930207 ps
CPU time 1.23 seconds
Started Mar 19 03:14:19 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 209364 kb
Host smart-4bfba5c6-2bd1-4839-8f7d-bbfad6c7515c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860428563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.860428563
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1624063957
Short name T1792
Test name
Test status
Simulation time 501914529 ps
CPU time 4.39 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:35 PM PDT 24
Peak memory 217900 kb
Host smart-7be0d53a-2251-4886-8054-aee0e3a6106c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624063957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1624063957
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2202240265
Short name T1760
Test name
Test status
Simulation time 266622519 ps
CPU time 2.21 seconds
Started Mar 19 03:14:20 PM PDT 24
Finished Mar 19 03:14:22 PM PDT 24
Peak memory 218148 kb
Host smart-b8fdfb55-bb87-4ac7-a126-1fdf78c05a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202240265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2202240265
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1409116549
Short name T133
Test name
Test status
Simulation time 104518866 ps
CPU time 2.82 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 221968 kb
Host smart-bf4bc68c-607b-4ff4-bb42-40889583a96e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409116549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1409116549
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3750252678
Short name T142
Test name
Test status
Simulation time 71518314 ps
CPU time 2.78 seconds
Started Mar 19 03:14:19 PM PDT 24
Finished Mar 19 03:14:22 PM PDT 24
Peak memory 217668 kb
Host smart-d197bee0-2a5d-49e5-bd15-359fba3fdb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750252678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3750252678
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2594415919
Short name T1949
Test name
Test status
Simulation time 25329713 ps
CPU time 1.62 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 217800 kb
Host smart-917eb7e7-553d-4918-b9fc-ed6fd43cfff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594415919 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2594415919
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.29112223
Short name T1827
Test name
Test status
Simulation time 59581820 ps
CPU time 1.58 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 218784 kb
Host smart-ac7fd04e-d4a1-4797-864a-a5eeefb817a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29112223 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.29112223
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2663586421
Short name T1849
Test name
Test status
Simulation time 46595812 ps
CPU time 0.88 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 209384 kb
Host smart-960cbd35-c4d0-43a5-afc0-b715abb091f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663586421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2663586421
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.309002665
Short name T1955
Test name
Test status
Simulation time 13758484 ps
CPU time 1.05 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 209384 kb
Host smart-a51483e7-8dbb-4670-a80b-b393e547adc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309002665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.309002665
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.131753415
Short name T1988
Test name
Test status
Simulation time 67318356 ps
CPU time 1.49 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 209292 kb
Host smart-39d3f641-aaa0-4b2a-baad-adcc1f7ca081
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131753415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.131753415
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4117085205
Short name T1706
Test name
Test status
Simulation time 562939671 ps
CPU time 1.11 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 209348 kb
Host smart-2c034855-bf1b-43e9-ba0e-42490ab31d9d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117085205 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4117085205
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2045468134
Short name T1940
Test name
Test status
Simulation time 2439127010 ps
CPU time 13.74 seconds
Started Mar 19 03:14:19 PM PDT 24
Finished Mar 19 03:14:33 PM PDT 24
Peak memory 209372 kb
Host smart-a51ba72d-447e-45a7-84b8-9409cd73c9cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045468134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2045468134
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3683507970
Short name T1887
Test name
Test status
Simulation time 844023175 ps
CPU time 9.61 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:38 PM PDT 24
Peak memory 209156 kb
Host smart-e07af979-59b2-4bc4-a703-ab96d9d7be88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683507970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3683507970
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2190134250
Short name T1953
Test name
Test status
Simulation time 741234770 ps
CPU time 6.85 seconds
Started Mar 19 02:48:34 PM PDT 24
Finished Mar 19 02:48:41 PM PDT 24
Peak memory 208536 kb
Host smart-f5538baf-2dbb-423b-a38b-a38a5f02ff2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190134250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2190134250
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2321419246
Short name T1763
Test name
Test status
Simulation time 678985939 ps
CPU time 4.9 seconds
Started Mar 19 03:14:24 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 209200 kb
Host smart-afe36a74-3282-45c2-8145-3536764fbe03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321419246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2321419246
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1527317903
Short name T1809
Test name
Test status
Simulation time 104346400 ps
CPU time 3.12 seconds
Started Mar 19 03:14:21 PM PDT 24
Finished Mar 19 03:14:24 PM PDT 24
Peak memory 211080 kb
Host smart-d83ebbc4-5257-45b6-b205-7e125f022ae1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527317903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1527317903
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2316246556
Short name T1716
Test name
Test status
Simulation time 467849005 ps
CPU time 2.76 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 210920 kb
Host smart-983a5fd7-4bfe-460f-bbeb-0f42d4254118
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316246556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2316246556
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2115518612
Short name T1945
Test name
Test status
Simulation time 56586995 ps
CPU time 1.55 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 218712 kb
Host smart-85641762-73e4-49bf-9080-3d70c26264e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211551
8612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2115518612
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.957626827
Short name T1769
Test name
Test status
Simulation time 592874921 ps
CPU time 2.44 seconds
Started Mar 19 03:14:18 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 218784 kb
Host smart-6cab785e-8738-459d-aa7f-69845459b9b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957626
827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.957626827
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1072253359
Short name T1959
Test name
Test status
Simulation time 238556545 ps
CPU time 1.17 seconds
Started Mar 19 03:14:16 PM PDT 24
Finished Mar 19 03:14:18 PM PDT 24
Peak memory 209428 kb
Host smart-23d822c7-db42-4784-b1d8-10024ba49cce
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072253359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1072253359
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2630627107
Short name T1722
Test name
Test status
Simulation time 165835034 ps
CPU time 1.23 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 209368 kb
Host smart-a9ee8875-db44-46b4-b4b9-8888ca0a9a26
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630627107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2630627107
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.180008332
Short name T1730
Test name
Test status
Simulation time 224353348 ps
CPU time 1.15 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 209416 kb
Host smart-80089a75-3ba8-45ec-a146-3498f3f7b11b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180008332 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.180008332
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2378782645
Short name T1878
Test name
Test status
Simulation time 190129950 ps
CPU time 1.39 seconds
Started Mar 19 03:14:17 PM PDT 24
Finished Mar 19 03:14:19 PM PDT 24
Peak memory 209460 kb
Host smart-b0d94258-8842-4985-bd74-9c48ca6079eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378782645 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2378782645
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2931829421
Short name T1752
Test name
Test status
Simulation time 30515637 ps
CPU time 1.49 seconds
Started Mar 19 03:14:31 PM PDT 24
Finished Mar 19 03:14:33 PM PDT 24
Peak memory 209396 kb
Host smart-9dd1a1d3-248c-450b-ba3b-77e90d6da999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931829421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2931829421
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3576127136
Short name T1778
Test name
Test status
Simulation time 55866213 ps
CPU time 1.1 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:26 PM PDT 24
Peak memory 209512 kb
Host smart-2988dac7-4164-44a2-b4fe-3f7631448233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576127136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3576127136
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2743748461
Short name T1941
Test name
Test status
Simulation time 107045261 ps
CPU time 3.16 seconds
Started Mar 19 03:14:26 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 218496 kb
Host smart-827281aa-6167-4f2f-bc5b-9f7836a805cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743748461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2743748461
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4103397086
Short name T1709
Test name
Test status
Simulation time 79943053 ps
CPU time 3.04 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 217652 kb
Host smart-25bc7a26-2f3c-41a7-8670-f39a25039d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103397086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4103397086
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1596040664
Short name T122
Test name
Test status
Simulation time 354908511 ps
CPU time 2.1 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 222080 kb
Host smart-8e6a32f5-7e5e-4894-8168-48c8e8a165ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596040664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1596040664
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4170355787
Short name T141
Test name
Test status
Simulation time 484296475 ps
CPU time 2.93 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 222160 kb
Host smart-d0a805c3-4439-46ae-acf3-d98e586211a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170355787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4170355787
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1361271908
Short name T1744
Test name
Test status
Simulation time 42085278 ps
CPU time 1.24 seconds
Started Mar 19 02:48:23 PM PDT 24
Finished Mar 19 02:48:24 PM PDT 24
Peak memory 217864 kb
Host smart-d9974586-7a64-4d64-9228-f43cbc01ef97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361271908 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1361271908
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.854662745
Short name T1814
Test name
Test status
Simulation time 144084161 ps
CPU time 2.06 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:43 PM PDT 24
Peak memory 217800 kb
Host smart-90653b99-aa13-45f1-aa86-89eb42bc3bab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854662745 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.854662745
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.185963163
Short name T213
Test name
Test status
Simulation time 28113814 ps
CPU time 0.96 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:25 PM PDT 24
Peak memory 209344 kb
Host smart-60711674-22e3-49b2-bd81-fd3f6d08fb18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185963163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.185963163
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.778186934
Short name T1754
Test name
Test status
Simulation time 11447755 ps
CPU time 0.89 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 209360 kb
Host smart-091933fd-6cf1-4433-9271-be93eb385c95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778186934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.778186934
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3305475409
Short name T1724
Test name
Test status
Simulation time 1890882020 ps
CPU time 1.64 seconds
Started Mar 19 03:14:26 PM PDT 24
Finished Mar 19 03:14:27 PM PDT 24
Peak memory 209364 kb
Host smart-252abc96-2ea2-4f40-b02e-16dc3eb5efb1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305475409 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3305475409
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3408797168
Short name T1932
Test name
Test status
Simulation time 28164314 ps
CPU time 0.95 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 209052 kb
Host smart-ef03870c-2447-4f11-a320-0368ba44fea3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408797168 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3408797168
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1301891942
Short name T1974
Test name
Test status
Simulation time 2615936467 ps
CPU time 10.4 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:41 PM PDT 24
Peak memory 209432 kb
Host smart-cf970f13-b7c7-4bdc-8337-8f1cd08dfeed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301891942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1301891942
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3973347359
Short name T1835
Test name
Test status
Simulation time 430575875 ps
CPU time 11.22 seconds
Started Mar 19 03:14:30 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 208552 kb
Host smart-931ed498-90f2-403f-8bba-d972afd31370
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973347359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3973347359
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1358208401
Short name T1908
Test name
Test status
Simulation time 674871823 ps
CPU time 7.29 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 209328 kb
Host smart-5e6ec403-119d-4809-afcd-d7afc3dc96dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358208401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1358208401
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2336273050
Short name T1987
Test name
Test status
Simulation time 678916388 ps
CPU time 17.57 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:58 PM PDT 24
Peak memory 208064 kb
Host smart-bf9286d0-fb9b-47e0-b133-2a68904f4ce8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336273050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2336273050
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1312571780
Short name T1702
Test name
Test status
Simulation time 269703499 ps
CPU time 1.51 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 210692 kb
Host smart-5fe06ed0-2597-4e67-9677-b149a94324a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312571780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1312571780
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2641456616
Short name T1806
Test name
Test status
Simulation time 790604811 ps
CPU time 2.81 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 210952 kb
Host smart-5ccd65a9-1dca-40cf-93e0-a9bb810e4bee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641456616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2641456616
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3259480376
Short name T1743
Test name
Test status
Simulation time 1681841629 ps
CPU time 3.66 seconds
Started Mar 19 03:14:41 PM PDT 24
Finished Mar 19 03:14:45 PM PDT 24
Peak memory 217764 kb
Host smart-58e1efe0-f643-45cd-b5d0-fca9037dcd67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325948
0376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3259480376
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.492531263
Short name T1757
Test name
Test status
Simulation time 187567548 ps
CPU time 2.78 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 218468 kb
Host smart-014ac631-109a-41fb-bb83-6f9c47b3abc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492531
263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.492531263
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.569283500
Short name T1823
Test name
Test status
Simulation time 37242018 ps
CPU time 1.08 seconds
Started Mar 19 03:14:31 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 209224 kb
Host smart-828b006a-54de-4a33-a341-f31088741ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569283500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.569283500
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.625941273
Short name T1937
Test name
Test status
Simulation time 56907603 ps
CPU time 1.93 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 209400 kb
Host smart-11fd9a8e-55e0-406c-8d53-50bd0ac6c0c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625941273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.625941273
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1178917541
Short name T1898
Test name
Test status
Simulation time 317133258 ps
CPU time 1.28 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 209440 kb
Host smart-1a770fc3-9cfb-43f4-b9d1-7ecb96804e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178917541 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1178917541
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.798466728
Short name T221
Test name
Test status
Simulation time 135267759 ps
CPU time 1.75 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 209324 kb
Host smart-a3ade413-c74f-4f7c-bb31-68e0555ccd2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798466728 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.798466728
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4198122502
Short name T1737
Test name
Test status
Simulation time 20430669 ps
CPU time 1.49 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 209020 kb
Host smart-8c9cf279-2dde-4717-8ca5-dc8179669cba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198122502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4198122502
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.900670576
Short name T227
Test name
Test status
Simulation time 21279741 ps
CPU time 1.28 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:28 PM PDT 24
Peak memory 211476 kb
Host smart-feb77abf-a907-4182-9c52-8b7248d991d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900670576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.900670576
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1832541689
Short name T1800
Test name
Test status
Simulation time 24862250 ps
CPU time 1.66 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 218944 kb
Host smart-7fdfc78a-44bb-4fe9-9e07-5aea85586ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832541689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1832541689
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.68986148
Short name T1836
Test name
Test status
Simulation time 102880801 ps
CPU time 1.6 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 217788 kb
Host smart-178cee0d-ee51-4f91-ac39-3906080fc517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68986148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.68986148
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3118039175
Short name T139
Test name
Test status
Simulation time 54826231 ps
CPU time 2.1 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 221844 kb
Host smart-aa025be8-3fd4-48b8-ad46-3f96851dc3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118039175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3118039175
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4100295116
Short name T163
Test name
Test status
Simulation time 50822751 ps
CPU time 1.78 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 221388 kb
Host smart-f5c15456-970f-46a1-a526-69f390d6805f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100295116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.4100295116
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1754864007
Short name T1785
Test name
Test status
Simulation time 197179264 ps
CPU time 1.55 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:28 PM PDT 24
Peak memory 219808 kb
Host smart-33ed3183-6713-45f3-a252-1b791f092b05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754864007 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1754864007
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4077952414
Short name T1794
Test name
Test status
Simulation time 92538050 ps
CPU time 1.43 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 217700 kb
Host smart-975ecb10-45ed-459c-bfa7-e741ddd87b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077952414 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.4077952414
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1827569861
Short name T1977
Test name
Test status
Simulation time 34965379 ps
CPU time 1.13 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 209380 kb
Host smart-44953b0f-ac08-4b2a-b2ff-d065f7c5d440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827569861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1827569861
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3382668488
Short name T1917
Test name
Test status
Simulation time 12827785 ps
CPU time 0.9 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:32 PM PDT 24
Peak memory 209268 kb
Host smart-382913d6-76ec-4ef2-82d6-8994d4eb52fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382668488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3382668488
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1166301030
Short name T1874
Test name
Test status
Simulation time 44699288 ps
CPU time 1.14 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 209296 kb
Host smart-2859e398-bc34-471b-9c81-83e52dcaaf56
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166301030 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1166301030
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1282042118
Short name T1759
Test name
Test status
Simulation time 1027986091 ps
CPU time 2.06 seconds
Started Mar 19 03:14:31 PM PDT 24
Finished Mar 19 03:14:33 PM PDT 24
Peak memory 209324 kb
Host smart-e45e8faa-4df9-4e8d-9a67-27c29afea264
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282042118 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1282042118
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1094433363
Short name T1985
Test name
Test status
Simulation time 1061347905 ps
CPU time 6.75 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:35 PM PDT 24
Peak memory 209180 kb
Host smart-5040c9ae-e008-4e03-baa1-da38d39750b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094433363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1094433363
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3566929414
Short name T1989
Test name
Test status
Simulation time 1055862924 ps
CPU time 12.37 seconds
Started Mar 19 02:48:29 PM PDT 24
Finished Mar 19 02:48:42 PM PDT 24
Peak memory 209164 kb
Host smart-d7dc0c7c-f0ee-4b46-897e-96fe9c006285
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566929414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3566929414
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2375372059
Short name T1877
Test name
Test status
Simulation time 1349530550 ps
CPU time 7.4 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:35 PM PDT 24
Peak memory 209356 kb
Host smart-7ea706d9-c8cc-4799-a29d-3c6eec1d32e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375372059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2375372059
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3820623037
Short name T1930
Test name
Test status
Simulation time 611293557 ps
CPU time 14.61 seconds
Started Mar 19 02:48:21 PM PDT 24
Finished Mar 19 02:48:36 PM PDT 24
Peak memory 209356 kb
Host smart-33e6a8fd-4b67-471b-99cd-c472963e498a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820623037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3820623037
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1436735586
Short name T1727
Test name
Test status
Simulation time 92626822 ps
CPU time 1.41 seconds
Started Mar 19 03:14:28 PM PDT 24
Finished Mar 19 03:14:30 PM PDT 24
Peak memory 210608 kb
Host smart-d09cc0e4-926e-43d0-bb02-6e5b88d5f2f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436735586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1436735586
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.431790620
Short name T1854
Test name
Test status
Simulation time 768072631 ps
CPU time 1.93 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 210640 kb
Host smart-0921ce4a-6e6c-48a4-bcca-40aa244c8854
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431790620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.431790620
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.210887064
Short name T1828
Test name
Test status
Simulation time 274382536 ps
CPU time 6.72 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:36 PM PDT 24
Peak memory 218464 kb
Host smart-ce730f48-e15b-4217-8df3-f35f62cb189e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210887
064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.210887064
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2709134441
Short name T1718
Test name
Test status
Simulation time 47291489 ps
CPU time 2.18 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 217700 kb
Host smart-ed7a50ad-64ae-4603-b4b9-681778d33d57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270913
4441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2709134441
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2070594480
Short name T1795
Test name
Test status
Simulation time 380277523 ps
CPU time 1.37 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 209360 kb
Host smart-0dff45dd-9eca-4624-8a21-7a1b5408cebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070594480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2070594480
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2902890547
Short name T124
Test name
Test status
Simulation time 290164625 ps
CPU time 1.5 seconds
Started Mar 19 03:14:27 PM PDT 24
Finished Mar 19 03:14:29 PM PDT 24
Peak memory 209352 kb
Host smart-12842703-a12f-4540-84dc-1338a9c90913
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902890547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2902890547
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3205735446
Short name T1825
Test name
Test status
Simulation time 77705522 ps
CPU time 1.49 seconds
Started Mar 19 03:14:31 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 211284 kb
Host smart-47949764-1de0-42e1-8327-395380148857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205735446 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3205735446
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.671176624
Short name T1817
Test name
Test status
Simulation time 88672199 ps
CPU time 1.04 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:31 PM PDT 24
Peak memory 209172 kb
Host smart-36c2c4fb-535c-4b2a-b504-0e409e305fc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671176624 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.671176624
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2486368253
Short name T1915
Test name
Test status
Simulation time 179026801 ps
CPU time 1.99 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 211548 kb
Host smart-f191c9c0-243c-4703-be6d-d6f64b15cf05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486368253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2486368253
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3571229257
Short name T1736
Test name
Test status
Simulation time 25869565 ps
CPU time 1.05 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 209452 kb
Host smart-97ccbec9-a2d4-411b-93ec-f047b73237ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571229257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3571229257
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.283608634
Short name T1990
Test name
Test status
Simulation time 178132035 ps
CPU time 2.73 seconds
Started Mar 19 02:48:30 PM PDT 24
Finished Mar 19 02:48:33 PM PDT 24
Peak memory 217708 kb
Host smart-c25eaf8b-b242-467b-b5cb-cbb5e8da7e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283608634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.283608634
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3830881244
Short name T1811
Test name
Test status
Simulation time 270368601 ps
CPU time 3.34 seconds
Started Mar 19 03:14:29 PM PDT 24
Finished Mar 19 03:14:33 PM PDT 24
Peak memory 217792 kb
Host smart-b5dfde2d-47c6-43c4-b5f6-dbbc44042fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830881244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3830881244
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3998673927
Short name T155
Test name
Test status
Simulation time 435385814 ps
CPU time 2.47 seconds
Started Mar 19 03:14:35 PM PDT 24
Finished Mar 19 03:14:38 PM PDT 24
Peak memory 217716 kb
Host smart-b23eee81-c639-48ed-bc20-b59e3c99f277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998673927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3998673927
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.27225550
Short name T929
Test name
Test status
Simulation time 138706395 ps
CPU time 0.88 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:23 PM PDT 24
Peak memory 209572 kb
Host smart-dee8a862-5637-4e26-9cdd-cc2a4a0a8561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27225550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.27225550
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2859032104
Short name T1503
Test name
Test status
Simulation time 340496839 ps
CPU time 0.97 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:19:04 PM PDT 24
Peak memory 209608 kb
Host smart-84278436-5809-4895-b1dd-5c4f8522c309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859032104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2859032104
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2212485993
Short name T188
Test name
Test status
Simulation time 278490032 ps
CPU time 11.32 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:33 PM PDT 24
Peak memory 217980 kb
Host smart-98a9b205-35ef-4a7d-ae02-966758f53a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212485993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2212485993
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.287768000
Short name T1308
Test name
Test status
Simulation time 1618919352 ps
CPU time 13.4 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:19:02 PM PDT 24
Peak memory 209452 kb
Host smart-7ab2bd6f-c41c-466b-8188-255549242b9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287768000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.287768000
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.89192268
Short name T321
Test name
Test status
Simulation time 115447139 ps
CPU time 1.17 seconds
Started Mar 19 03:15:23 PM PDT 24
Finished Mar 19 03:15:25 PM PDT 24
Peak memory 209480 kb
Host smart-3f956e66-1d96-40d0-99fb-b24247bfe017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89192268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.89192268
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.4092938296
Short name T1661
Test name
Test status
Simulation time 4118792183 ps
CPU time 19.33 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 218084 kb
Host smart-e4788c73-902d-41db-8be2-a4b7ef005a10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092938296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.4092938296
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.796355210
Short name T1187
Test name
Test status
Simulation time 3099823061 ps
CPU time 40.59 seconds
Started Mar 19 03:15:23 PM PDT 24
Finished Mar 19 03:16:04 PM PDT 24
Peak memory 219072 kb
Host smart-b08193ad-6f3e-4e34-ad07-44c0cbba15f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796355210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.796355210
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2658552441
Short name T855
Test name
Test status
Simulation time 2242711155 ps
CPU time 2.92 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:25 PM PDT 24
Peak memory 217068 kb
Host smart-a9fb0061-e49d-4012-a307-744c4cb482af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658552441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
658552441
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.723090331
Short name T60
Test name
Test status
Simulation time 997632228 ps
CPU time 6.55 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:18:58 PM PDT 24
Peak memory 217052 kb
Host smart-b1e33f59-220e-40e6-8664-04e9009c00cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723090331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.723090331
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2571448367
Short name T309
Test name
Test status
Simulation time 135119830 ps
CPU time 4.43 seconds
Started Mar 19 03:19:01 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 217964 kb
Host smart-dc0d723e-c494-4a8e-ba02-8ec30b1b702b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571448367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2571448367
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3618612076
Short name T460
Test name
Test status
Simulation time 1983719159 ps
CPU time 26.44 seconds
Started Mar 19 03:15:20 PM PDT 24
Finished Mar 19 03:15:46 PM PDT 24
Peak memory 217952 kb
Host smart-2dc84c57-dbc7-471e-922c-846d783831fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618612076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3618612076
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1118577622
Short name T1553
Test name
Test status
Simulation time 868616470 ps
CPU time 14.98 seconds
Started Mar 19 03:15:19 PM PDT 24
Finished Mar 19 03:15:34 PM PDT 24
Peak memory 213176 kb
Host smart-9ebe73a1-b9b5-4f0c-b134-5ba9ebfc3c33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118577622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1118577622
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2641864363
Short name T1245
Test name
Test status
Simulation time 933392422 ps
CPU time 25.99 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 213200 kb
Host smart-22275220-834c-46ad-88f6-705aeef3ff7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641864363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2641864363
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1705979492
Short name T1573
Test name
Test status
Simulation time 242063887 ps
CPU time 3.53 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 213028 kb
Host smart-4b79054f-6fff-470d-9152-73c61a54fd8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705979492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1705979492
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.923303718
Short name T1194
Test name
Test status
Simulation time 339687911 ps
CPU time 4.51 seconds
Started Mar 19 03:15:20 PM PDT 24
Finished Mar 19 03:15:25 PM PDT 24
Peak memory 213312 kb
Host smart-129b3804-dd19-4efb-904d-8933f642dede
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923303718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.923303718
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1071126804
Short name T82
Test name
Test status
Simulation time 3491003923 ps
CPU time 30.94 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 251160 kb
Host smart-b5db0f0f-64aa-4582-856b-469026720338
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071126804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1071126804
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3166318447
Short name T778
Test name
Test status
Simulation time 1451492133 ps
CPU time 48.91 seconds
Started Mar 19 03:15:19 PM PDT 24
Finished Mar 19 03:16:09 PM PDT 24
Peak memory 269836 kb
Host smart-e5b38082-ae42-4c10-b857-b049cc2b626e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166318447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3166318447
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1893561789
Short name T932
Test name
Test status
Simulation time 1679064896 ps
CPU time 16.11 seconds
Started Mar 19 03:18:50 PM PDT 24
Finished Mar 19 03:19:07 PM PDT 24
Peak memory 250924 kb
Host smart-fa49217c-a622-4a7a-80da-8f87f6450cde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893561789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1893561789
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.32734176
Short name T374
Test name
Test status
Simulation time 611932394 ps
CPU time 9.23 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:30 PM PDT 24
Peak memory 250884 kb
Host smart-660a76a7-836e-4ad8-8070-4108afb7b4f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_state_post_trans.32734176
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.197807480
Short name T1511
Test name
Test status
Simulation time 76648493 ps
CPU time 4.02 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 222112 kb
Host smart-179ace3b-7dc9-4a6e-a5ab-a8bc2cfbba31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197807480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.197807480
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3192763329
Short name T1354
Test name
Test status
Simulation time 416261084 ps
CPU time 3.63 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:25 PM PDT 24
Peak memory 218012 kb
Host smart-8ee5c94a-feb1-4b37-b3f4-a48061bc1fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192763329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3192763329
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2379270833
Short name T1202
Test name
Test status
Simulation time 685237673 ps
CPU time 11.48 seconds
Started Mar 19 03:15:20 PM PDT 24
Finished Mar 19 03:15:32 PM PDT 24
Peak memory 217824 kb
Host smart-6cb60247-d615-4dde-b9ca-abdc8350ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379270833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2379270833
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.549423860
Short name T1043
Test name
Test status
Simulation time 409844269 ps
CPU time 9.85 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:59 PM PDT 24
Peak memory 213948 kb
Host smart-3de4ecf8-a791-4f48-b81c-d3cf48efabe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549423860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.549423860
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1219947859
Short name T102
Test name
Test status
Simulation time 1265362108 ps
CPU time 26.2 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:19:15 PM PDT 24
Peak memory 280724 kb
Host smart-cc46f13d-e114-4716-9b7a-0fcc588b51a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219947859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1219947859
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2518626450
Short name T84
Test name
Test status
Simulation time 110579854 ps
CPU time 22.42 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 284712 kb
Host smart-7aee10cd-5f4a-47c8-9f07-666d7c5f307e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518626450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2518626450
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1697278146
Short name T974
Test name
Test status
Simulation time 254210068 ps
CPU time 9.91 seconds
Started Mar 19 03:15:17 PM PDT 24
Finished Mar 19 03:15:28 PM PDT 24
Peak memory 225396 kb
Host smart-f90fcc8e-cf36-4113-9354-26830c3fa69c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697278146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1697278146
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.324053711
Short name T1178
Test name
Test status
Simulation time 934213509 ps
CPU time 8.52 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 226080 kb
Host smart-e1d65b34-a147-4228-a5dc-2174f7c31c1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324053711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.324053711
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2005339446
Short name T1271
Test name
Test status
Simulation time 1760066625 ps
CPU time 12.5 seconds
Started Mar 19 03:18:50 PM PDT 24
Finished Mar 19 03:19:02 PM PDT 24
Peak memory 217880 kb
Host smart-1de517a7-0924-43a6-992a-837c9e43341f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005339446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2005339446
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3381633791
Short name T405
Test name
Test status
Simulation time 1131057349 ps
CPU time 12.01 seconds
Started Mar 19 03:15:22 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 217880 kb
Host smart-6a9db1b6-81fe-49c3-af5a-41fc91c2001f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381633791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3381633791
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1936356344
Short name T1392
Test name
Test status
Simulation time 211732225 ps
CPU time 6.64 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:28 PM PDT 24
Peak memory 217884 kb
Host smart-d0d6aa40-a212-41b1-b8c4-60672fb566f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936356344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
936356344
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2382618433
Short name T1032
Test name
Test status
Simulation time 3594568550 ps
CPU time 10.84 seconds
Started Mar 19 03:18:53 PM PDT 24
Finished Mar 19 03:19:09 PM PDT 24
Peak memory 217972 kb
Host smart-87f1d785-7cdd-4365-80e3-55cee1d35a5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382618433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
382618433
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1153276216
Short name T783
Test name
Test status
Simulation time 2959643894 ps
CPU time 7.72 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:57 PM PDT 24
Peak memory 224904 kb
Host smart-d6cb17e8-7396-410a-a3df-c951b89d94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153276216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1153276216
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.886907523
Short name T1679
Test name
Test status
Simulation time 1023822439 ps
CPU time 6.96 seconds
Started Mar 19 03:15:18 PM PDT 24
Finished Mar 19 03:15:25 PM PDT 24
Peak memory 225972 kb
Host smart-74cea59e-1896-4e1a-add2-379966f14733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886907523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.886907523
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2249218420
Short name T540
Test name
Test status
Simulation time 96440623 ps
CPU time 1.82 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:51 PM PDT 24
Peak memory 213768 kb
Host smart-22145161-6d0b-4056-8c6b-a4b10fe8c2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249218420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2249218420
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.4218373058
Short name T1048
Test name
Test status
Simulation time 95953753 ps
CPU time 1.74 seconds
Started Mar 19 03:15:22 PM PDT 24
Finished Mar 19 03:15:24 PM PDT 24
Peak memory 213576 kb
Host smart-15bb523e-26f9-47aa-a3e2-cee23d7c107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218373058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.4218373058
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1666453581
Short name T318
Test name
Test status
Simulation time 554019453 ps
CPU time 26.63 seconds
Started Mar 19 03:15:20 PM PDT 24
Finished Mar 19 03:15:47 PM PDT 24
Peak memory 246408 kb
Host smart-008ccd32-582d-411d-b77a-e535df54ba5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666453581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1666453581
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.345062366
Short name T445
Test name
Test status
Simulation time 139309411 ps
CPU time 18.3 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:19:11 PM PDT 24
Peak memory 250880 kb
Host smart-6ff9f21a-1ef4-4e11-bc8a-da9200fd6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345062366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.345062366
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2769087389
Short name T684
Test name
Test status
Simulation time 270710849 ps
CPU time 8.3 seconds
Started Mar 19 03:18:53 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 249060 kb
Host smart-3372f53f-e87b-4e7d-b127-8e969162f161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769087389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2769087389
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3969505056
Short name T1268
Test name
Test status
Simulation time 292834639 ps
CPU time 8.79 seconds
Started Mar 19 03:15:15 PM PDT 24
Finished Mar 19 03:15:24 PM PDT 24
Peak memory 250868 kb
Host smart-c6f41ba1-dd43-46fc-b5b0-cbe2eae260b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969505056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3969505056
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2487926647
Short name T720
Test name
Test status
Simulation time 16941351596 ps
CPU time 173.18 seconds
Started Mar 19 03:18:50 PM PDT 24
Finished Mar 19 03:21:44 PM PDT 24
Peak memory 280656 kb
Host smart-48cd26ca-742b-47ba-a35d-f7e3fb561f95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487926647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2487926647
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3683163415
Short name T598
Test name
Test status
Simulation time 16367932119 ps
CPU time 60.43 seconds
Started Mar 19 03:15:18 PM PDT 24
Finished Mar 19 03:16:19 PM PDT 24
Peak memory 226188 kb
Host smart-4c9382fb-4e65-4665-b35e-67bbf76d674d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683163415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3683163415
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1611816588
Short name T500
Test name
Test status
Simulation time 17407838 ps
CPU time 0.89 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:23 PM PDT 24
Peak memory 211604 kb
Host smart-b8c8835e-d232-442e-a6f3-922e5e83d1a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611816588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1611816588
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2170322789
Short name T470
Test name
Test status
Simulation time 24357195 ps
CPU time 1.07 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 211524 kb
Host smart-7d7fef2a-51ec-438f-bb32-db5c9856834a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170322789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2170322789
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4124432111
Short name T755
Test name
Test status
Simulation time 97499764 ps
CPU time 1.32 seconds
Started Mar 19 03:19:08 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 209616 kb
Host smart-b56f5754-1cd4-4472-b3fd-8ec5be51af06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124432111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4124432111
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.873782964
Short name T1606
Test name
Test status
Simulation time 18789670 ps
CPU time 0.95 seconds
Started Mar 19 03:15:29 PM PDT 24
Finished Mar 19 03:15:30 PM PDT 24
Peak memory 209652 kb
Host smart-bb23881e-1534-4983-b941-3dafe3230fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873782964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.873782964
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1314213162
Short name T1333
Test name
Test status
Simulation time 10637805 ps
CPU time 0.95 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:23 PM PDT 24
Peak memory 209456 kb
Host smart-39b54630-f36c-4174-84f3-3eaca7a3a139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314213162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1314213162
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2439679395
Short name T237
Test name
Test status
Simulation time 12570043 ps
CPU time 0.85 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 209408 kb
Host smart-9deeeab6-37f2-4864-ad30-f8d3533319d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439679395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2439679395
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1004416777
Short name T1168
Test name
Test status
Simulation time 755026823 ps
CPU time 8.7 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:07 PM PDT 24
Peak memory 217976 kb
Host smart-d2a7f4c8-6b46-4138-9ee7-a0b79fe47491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004416777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1004416777
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2947687293
Short name T963
Test name
Test status
Simulation time 457639071 ps
CPU time 11.82 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:33 PM PDT 24
Peak memory 217956 kb
Host smart-59ad3219-41d2-4929-b1aa-a04a63ebd428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947687293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2947687293
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2008635655
Short name T1489
Test name
Test status
Simulation time 819544723 ps
CPU time 4.72 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:26 PM PDT 24
Peak memory 209480 kb
Host smart-efafaa95-02d4-4e46-b404-c57e376ad71a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008635655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2008635655
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4245209989
Short name T1074
Test name
Test status
Simulation time 1140430706 ps
CPU time 7.41 seconds
Started Mar 19 03:18:53 PM PDT 24
Finished Mar 19 03:19:00 PM PDT 24
Peak memory 217048 kb
Host smart-44ea8a68-b6db-4a99-b586-9dedfa8437fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245209989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4245209989
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1011815578
Short name T1182
Test name
Test status
Simulation time 1743112793 ps
CPU time 25.97 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:48 PM PDT 24
Peak memory 217956 kb
Host smart-7f41614f-9644-4a64-9faa-577abf4c38d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011815578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1011815578
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2736395379
Short name T1320
Test name
Test status
Simulation time 421002369 ps
CPU time 7.12 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:56 PM PDT 24
Peak memory 217768 kb
Host smart-ee436626-5ffc-4ff2-8a75-a4be1f2ab8d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736395379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
736395379
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.445701607
Short name T936
Test name
Test status
Simulation time 980535749 ps
CPU time 2.24 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:15:34 PM PDT 24
Peak memory 217020 kb
Host smart-8431e050-99b8-4de3-aa50-16ae4a4794c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445701607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.445701607
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3103592819
Short name T654
Test name
Test status
Simulation time 146945852 ps
CPU time 3.31 seconds
Started Mar 19 03:15:19 PM PDT 24
Finished Mar 19 03:15:23 PM PDT 24
Peak memory 217992 kb
Host smart-79460b1b-e470-41cf-8094-89e9cdf3d68a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103592819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3103592819
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.777465469
Short name T481
Test name
Test status
Simulation time 2015533632 ps
CPU time 4.05 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:19:15 PM PDT 24
Peak memory 218004 kb
Host smart-da7c7686-5abc-44f1-aaad-1255d0063e3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777465469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.777465469
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1577163344
Short name T1610
Test name
Test status
Simulation time 598225855 ps
CPU time 10.05 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:15:47 PM PDT 24
Peak memory 213064 kb
Host smart-bdbeb873-215e-4567-a3a9-a7daf48ff240
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577163344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1577163344
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4035182543
Short name T515
Test name
Test status
Simulation time 1271911340 ps
CPU time 20.61 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 213456 kb
Host smart-dbcfdd85-0156-4c4a-9631-2d7d073e37b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035182543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4035182543
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1483145459
Short name T1230
Test name
Test status
Simulation time 124433173 ps
CPU time 2.4 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:18:53 PM PDT 24
Peak memory 213196 kb
Host smart-4a3b435b-b3ca-41ec-a952-72200977436b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483145459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1483145459
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2376600694
Short name T546
Test name
Test status
Simulation time 842116798 ps
CPU time 8.72 seconds
Started Mar 19 03:15:17 PM PDT 24
Finished Mar 19 03:15:25 PM PDT 24
Peak memory 213572 kb
Host smart-2df5856f-3b22-4fdf-b5c3-172971a81bac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376600694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2376600694
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2689921838
Short name T794
Test name
Test status
Simulation time 2672037261 ps
CPU time 40.24 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 253020 kb
Host smart-50b44385-97e2-4e8d-ad1a-c2db7a98ef41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689921838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2689921838
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3225447041
Short name T627
Test name
Test status
Simulation time 4935623505 ps
CPU time 45.82 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 276644 kb
Host smart-ed90d7b3-3d39-4b2a-8b79-f66ff70cf8fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225447041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3225447041
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1168895628
Short name T1644
Test name
Test status
Simulation time 718229803 ps
CPU time 19.21 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:41 PM PDT 24
Peak memory 244788 kb
Host smart-891d2725-905a-4dfd-862e-b00d14bfb7d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168895628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1168895628
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2731654744
Short name T1171
Test name
Test status
Simulation time 1041522360 ps
CPU time 9.24 seconds
Started Mar 19 03:18:50 PM PDT 24
Finished Mar 19 03:18:59 PM PDT 24
Peak memory 217864 kb
Host smart-7f2c1de6-af44-4fd7-94ea-41a4d4953e0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731654744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2731654744
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1262383993
Short name T1270
Test name
Test status
Simulation time 196767690 ps
CPU time 3.07 seconds
Started Mar 19 03:15:22 PM PDT 24
Finished Mar 19 03:15:25 PM PDT 24
Peak memory 221712 kb
Host smart-78733a48-1d09-4b14-8a7b-55dcd877e3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262383993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1262383993
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.261553415
Short name T920
Test name
Test status
Simulation time 165202139 ps
CPU time 2.64 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:18:55 PM PDT 24
Peak memory 221740 kb
Host smart-f2174825-135c-497d-8cca-5096927c7e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261553415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.261553415
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3871481080
Short name T1353
Test name
Test status
Simulation time 334864445 ps
CPU time 23.51 seconds
Started Mar 19 03:15:22 PM PDT 24
Finished Mar 19 03:15:45 PM PDT 24
Peak memory 214392 kb
Host smart-f3146447-b2eb-4f52-b30c-ca630caabc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871481080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3871481080
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4041522652
Short name T99
Test name
Test status
Simulation time 998736865 ps
CPU time 25.15 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:15:57 PM PDT 24
Peak memory 268760 kb
Host smart-f779c95a-c106-4021-b8d2-3964a337b924
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041522652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4041522652
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3977018382
Short name T1101
Test name
Test status
Simulation time 385075179 ps
CPU time 12.48 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:11 PM PDT 24
Peak memory 225580 kb
Host smart-6678db27-5d17-4968-8950-cff5b641992b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977018382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3977018382
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.888203133
Short name T847
Test name
Test status
Simulation time 373770710 ps
CPU time 12.78 seconds
Started Mar 19 03:15:30 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 226008 kb
Host smart-df203701-faa7-4d3a-a995-fcbe32586376
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888203133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.888203133
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1006120395
Short name T1130
Test name
Test status
Simulation time 3343535636 ps
CPU time 20.61 seconds
Started Mar 19 03:19:07 PM PDT 24
Finished Mar 19 03:19:28 PM PDT 24
Peak memory 218000 kb
Host smart-040f5f6a-cf84-4a89-b701-b3760d572cb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006120395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1006120395
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2690568282
Short name T443
Test name
Test status
Simulation time 424507655 ps
CPU time 15.69 seconds
Started Mar 19 03:15:38 PM PDT 24
Finished Mar 19 03:15:54 PM PDT 24
Peak memory 217844 kb
Host smart-79624552-d992-42b8-a681-3ac817667ec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690568282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2690568282
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2271356171
Short name T1591
Test name
Test status
Simulation time 308705462 ps
CPU time 9.58 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:08 PM PDT 24
Peak memory 217864 kb
Host smart-659682d8-8e0c-41c4-b453-3aa4221a644b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271356171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
271356171
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.4233123705
Short name T647
Test name
Test status
Simulation time 341915595 ps
CPU time 9.06 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 217884 kb
Host smart-ef10de24-f698-4654-a0f7-530ee75c1d25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233123705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.4
233123705
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2769763057
Short name T1526
Test name
Test status
Simulation time 1234906201 ps
CPU time 9.91 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:58 PM PDT 24
Peak memory 226028 kb
Host smart-d9d45292-b87e-409a-9c65-daa200e3872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769763057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2769763057
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4216728208
Short name T1367
Test name
Test status
Simulation time 1552008328 ps
CPU time 11.91 seconds
Started Mar 19 03:15:20 PM PDT 24
Finished Mar 19 03:15:32 PM PDT 24
Peak memory 225380 kb
Host smart-3d0a2bf6-5eca-43f1-a243-1e08aa85cbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216728208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4216728208
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2960154455
Short name T333
Test name
Test status
Simulation time 129953097 ps
CPU time 2.89 seconds
Started Mar 19 03:15:18 PM PDT 24
Finished Mar 19 03:15:22 PM PDT 24
Peak memory 214420 kb
Host smart-988ee15b-3329-4f5c-8f9e-66c6e8dba743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960154455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2960154455
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3079904312
Short name T362
Test name
Test status
Simulation time 245791207 ps
CPU time 10.29 seconds
Started Mar 19 03:18:50 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 214796 kb
Host smart-4dda218f-c1ad-4e22-be6a-3dbc229a8685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079904312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3079904312
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.653244583
Short name T838
Test name
Test status
Simulation time 162059964 ps
CPU time 18.57 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 244964 kb
Host smart-0bd9b24d-f4db-4361-b5b3-3331c05dd364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653244583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.653244583
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.733410593
Short name T306
Test name
Test status
Simulation time 643417430 ps
CPU time 28.12 seconds
Started Mar 19 03:15:21 PM PDT 24
Finished Mar 19 03:15:50 PM PDT 24
Peak memory 250944 kb
Host smart-902b2e28-8dc7-413f-8a13-26724af09f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733410593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.733410593
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1549518933
Short name T1324
Test name
Test status
Simulation time 114877197 ps
CPU time 7.51 seconds
Started Mar 19 03:15:19 PM PDT 24
Finished Mar 19 03:15:27 PM PDT 24
Peak memory 250972 kb
Host smart-582f0964-d5ca-4861-b525-95a1790a3566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549518933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1549518933
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2543284465
Short name T901
Test name
Test status
Simulation time 842700651 ps
CPU time 6.48 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:55 PM PDT 24
Peak memory 250836 kb
Host smart-75a4acfc-4966-45f2-91c8-4a74063a27f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543284465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2543284465
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2223509899
Short name T1495
Test name
Test status
Simulation time 38611701696 ps
CPU time 159.67 seconds
Started Mar 19 03:18:59 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 251040 kb
Host smart-9730b2c7-181c-4f06-ae59-23fc96244625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223509899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2223509899
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3699840284
Short name T42
Test name
Test status
Simulation time 10822740211 ps
CPU time 176.15 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:18:34 PM PDT 24
Peak memory 252144 kb
Host smart-9fd1742e-9d8e-4f28-a20d-5b9885cc3747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699840284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3699840284
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2211246362
Short name T182
Test name
Test status
Simulation time 39178713576 ps
CPU time 364.31 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:25:03 PM PDT 24
Peak memory 268464 kb
Host smart-6bc234e0-0a76-4434-8257-884d62031170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2211246362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2211246362
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1210677716
Short name T503
Test name
Test status
Simulation time 17244424 ps
CPU time 1.07 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:18:53 PM PDT 24
Peak memory 212548 kb
Host smart-936bca55-3b7d-4aa4-8810-d57e149e87e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210677716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1210677716
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1545765972
Short name T1078
Test name
Test status
Simulation time 14463505 ps
CPU time 1.07 seconds
Started Mar 19 03:15:17 PM PDT 24
Finished Mar 19 03:15:18 PM PDT 24
Peak memory 211488 kb
Host smart-0c028fd9-f744-48d9-95b3-42d8a123ec2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545765972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1545765972
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2237557760
Short name T1317
Test name
Test status
Simulation time 162086587 ps
CPU time 1.25 seconds
Started Mar 19 03:16:06 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 209592 kb
Host smart-3c238f06-80dd-4ba1-b7b7-6ae5c6f82e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237557760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2237557760
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.884925887
Short name T1158
Test name
Test status
Simulation time 104614628 ps
CPU time 0.93 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 209588 kb
Host smart-e6269d23-bee2-45b6-a48f-0a1f5f89fcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884925887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.884925887
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1388912231
Short name T295
Test name
Test status
Simulation time 1389193858 ps
CPU time 10.04 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:19:43 PM PDT 24
Peak memory 226080 kb
Host smart-360d11cd-fb2d-4124-a883-0890877afb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388912231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1388912231
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2353367884
Short name T1424
Test name
Test status
Simulation time 539043399 ps
CPU time 11.81 seconds
Started Mar 19 03:16:04 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 217912 kb
Host smart-fc7f2f10-1f87-4eab-9b35-8597b5e08b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353367884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2353367884
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1572106252
Short name T1579
Test name
Test status
Simulation time 1842113682 ps
CPU time 6.8 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 216784 kb
Host smart-ce1d1ceb-f2cd-4210-ab99-389c446d32ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572106252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1572106252
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1674024739
Short name T1004
Test name
Test status
Simulation time 230816362 ps
CPU time 3.78 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:09 PM PDT 24
Peak memory 209532 kb
Host smart-79451a26-ac9c-48bb-a347-192ea4e4454c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674024739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1674024739
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2930184492
Short name T964
Test name
Test status
Simulation time 3635732981 ps
CPU time 45.69 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:20:13 PM PDT 24
Peak memory 218556 kb
Host smart-be7c3f9b-0f30-4b09-b755-3be31406759c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930184492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2930184492
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.4091554372
Short name T753
Test name
Test status
Simulation time 4863859876 ps
CPU time 35.42 seconds
Started Mar 19 03:16:07 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 218052 kb
Host smart-b0303788-05f1-4aa7-b45d-220755b0de62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091554372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.4091554372
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2472426599
Short name T1314
Test name
Test status
Simulation time 143723397 ps
CPU time 2.71 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 218068 kb
Host smart-5d348cdf-13fc-4f12-be1a-84491bd60664
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472426599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2472426599
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3993799304
Short name T397
Test name
Test status
Simulation time 251929188 ps
CPU time 2.21 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 217992 kb
Host smart-ec28adf4-1fc5-43a3-b948-0e6860dd4f2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993799304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3993799304
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3808572536
Short name T828
Test name
Test status
Simulation time 1087841041 ps
CPU time 6.17 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:10 PM PDT 24
Peak memory 213344 kb
Host smart-24ee7467-d4fc-4b12-8ed5-a90138b66a3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808572536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3808572536
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.439200259
Short name T1394
Test name
Test status
Simulation time 1337091776 ps
CPU time 4.81 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:25 PM PDT 24
Peak memory 212972 kb
Host smart-94cdbd2c-37ba-4383-b311-bc9688ad9ccf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439200259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
439200259
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1681549109
Short name T1275
Test name
Test status
Simulation time 15913940675 ps
CPU time 76.27 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 283804 kb
Host smart-03eb47fd-4537-489b-b294-e48ad0833737
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681549109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1681549109
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.969593743
Short name T1114
Test name
Test status
Simulation time 910948353 ps
CPU time 41.05 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:20:02 PM PDT 24
Peak memory 250952 kb
Host smart-af2f21fa-dc88-4aeb-82ca-72f69af52a26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969593743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.969593743
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1407386650
Short name T1007
Test name
Test status
Simulation time 916443913 ps
CPU time 17.77 seconds
Started Mar 19 03:19:37 PM PDT 24
Finished Mar 19 03:19:55 PM PDT 24
Peak memory 245308 kb
Host smart-d36e0d8d-54f5-4944-b59d-413b1d6c9ac1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407386650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1407386650
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.188473637
Short name T1448
Test name
Test status
Simulation time 8758993580 ps
CPU time 19.54 seconds
Started Mar 19 03:16:06 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 251024 kb
Host smart-b8cfec74-36f7-4217-9881-a25451152779
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188473637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.188473637
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2099270638
Short name T1452
Test name
Test status
Simulation time 380065001 ps
CPU time 1.65 seconds
Started Mar 19 03:16:00 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 218020 kb
Host smart-55baa5d5-a111-456a-a0c8-690298541327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099270638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2099270638
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2739584411
Short name T589
Test name
Test status
Simulation time 637174574 ps
CPU time 3.98 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:25 PM PDT 24
Peak memory 222104 kb
Host smart-cbb4c45c-d409-4dba-8a5d-4a542d4cb491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739584411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2739584411
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.131632005
Short name T296
Test name
Test status
Simulation time 434950676 ps
CPU time 11.8 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:17 PM PDT 24
Peak memory 226040 kb
Host smart-be5cbf26-ad38-4de2-93f8-2d9cd0e70eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131632005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.131632005
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.4283675858
Short name T1433
Test name
Test status
Simulation time 232281531 ps
CPU time 10.61 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:19:32 PM PDT 24
Peak memory 217952 kb
Host smart-d17a693a-aa4c-4bd5-96c1-f4dc95d2478e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283675858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4283675858
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3333455858
Short name T956
Test name
Test status
Simulation time 570509603 ps
CPU time 12.32 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:18 PM PDT 24
Peak memory 217884 kb
Host smart-95f5891e-8544-40d3-842f-9e0796ce0f01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333455858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3333455858
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3673495636
Short name T714
Test name
Test status
Simulation time 577812369 ps
CPU time 9.38 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:19:29 PM PDT 24
Peak memory 217888 kb
Host smart-d54ba64b-905d-4e7d-a66c-db87ccd4c905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673495636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3673495636
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2571701271
Short name T1055
Test name
Test status
Simulation time 1067313004 ps
CPU time 6.89 seconds
Started Mar 19 03:16:06 PM PDT 24
Finished Mar 19 03:16:13 PM PDT 24
Peak memory 217872 kb
Host smart-b70f152d-3698-445d-8399-9bd43f6d8831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571701271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2571701271
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.4271580277
Short name T547
Test name
Test status
Simulation time 678194222 ps
CPU time 16 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 217948 kb
Host smart-11b192b8-9a4b-41e9-9642-25660545a7a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271580277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
4271580277
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1811562825
Short name T1041
Test name
Test status
Simulation time 5623411306 ps
CPU time 9.79 seconds
Started Mar 19 03:19:40 PM PDT 24
Finished Mar 19 03:19:50 PM PDT 24
Peak memory 226196 kb
Host smart-98617d5d-97b2-47a2-8606-7adcb2e17c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811562825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1811562825
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3594152008
Short name T536
Test name
Test status
Simulation time 217037002 ps
CPU time 9.79 seconds
Started Mar 19 03:16:06 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 225988 kb
Host smart-ea4fac34-8f02-4d3c-aafc-be988b7e9b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594152008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3594152008
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3116858924
Short name T508
Test name
Test status
Simulation time 180626478 ps
CPU time 2.05 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:19:35 PM PDT 24
Peak memory 217692 kb
Host smart-63993672-121a-4754-9881-0607359e2252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116858924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3116858924
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.692437808
Short name T1557
Test name
Test status
Simulation time 205396526 ps
CPU time 6.15 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:11 PM PDT 24
Peak memory 217868 kb
Host smart-71617668-dc6d-4b08-abe8-42f427c6ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692437808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.692437808
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1190345081
Short name T1258
Test name
Test status
Simulation time 1685753346 ps
CPU time 29.12 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:20:02 PM PDT 24
Peak memory 250964 kb
Host smart-59e746f8-ee31-4fc5-9bed-716cad634877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190345081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1190345081
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2700077698
Short name T197
Test name
Test status
Simulation time 412828799 ps
CPU time 23.25 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:27 PM PDT 24
Peak memory 250888 kb
Host smart-937b27a2-c759-4862-8500-e97d27ea8b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700077698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2700077698
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.111113812
Short name T573
Test name
Test status
Simulation time 926592428 ps
CPU time 3.35 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:23 PM PDT 24
Peak memory 222100 kb
Host smart-e1fce444-b0ba-4298-914d-25bf73b1751f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111113812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.111113812
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3242096416
Short name T288
Test name
Test status
Simulation time 248174997 ps
CPU time 8.5 seconds
Started Mar 19 03:16:04 PM PDT 24
Finished Mar 19 03:16:13 PM PDT 24
Peak memory 247496 kb
Host smart-355b4ba2-e404-4b62-ad9a-0406cc4fb5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242096416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3242096416
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1221506704
Short name T1342
Test name
Test status
Simulation time 34886440007 ps
CPU time 211.58 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 268320 kb
Host smart-cb8f41ee-4cd9-4b4a-806b-63b6397ab258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221506704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1221506704
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3411718684
Short name T924
Test name
Test status
Simulation time 11090762523 ps
CPU time 240.46 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:23:21 PM PDT 24
Peak memory 404748 kb
Host smart-e5a32425-d06d-44e5-ab51-aa82abe39cf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411718684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3411718684
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4101642220
Short name T447
Test name
Test status
Simulation time 34318325 ps
CPU time 0.87 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 208332 kb
Host smart-72f730d6-14b6-45ee-af8a-1bff6c70bacb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101642220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4101642220
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4130927020
Short name T1464
Test name
Test status
Simulation time 16808501 ps
CPU time 0.96 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:19:20 PM PDT 24
Peak memory 212556 kb
Host smart-8b5b91fb-a48b-4460-a6ea-23d50978143b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130927020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4130927020
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4037944564
Short name T1441
Test name
Test status
Simulation time 26906407 ps
CPU time 1.11 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 209620 kb
Host smart-09ca7daf-dd40-4383-afd6-fbd161c28a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037944564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4037944564
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.496294637
Short name T640
Test name
Test status
Simulation time 18286787 ps
CPU time 0.89 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:16:18 PM PDT 24
Peak memory 209584 kb
Host smart-c07b4045-f9b1-4bcf-b9d5-4195a8bdb212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496294637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.496294637
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.422464194
Short name T1366
Test name
Test status
Simulation time 486736778 ps
CPU time 13.62 seconds
Started Mar 19 03:19:40 PM PDT 24
Finished Mar 19 03:19:55 PM PDT 24
Peak memory 217944 kb
Host smart-a5f9814b-7124-4ad7-bc67-1cecf299c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422464194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.422464194
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.839076063
Short name T1465
Test name
Test status
Simulation time 381868513 ps
CPU time 16.9 seconds
Started Mar 19 03:16:07 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 217956 kb
Host smart-deca1c52-8563-4259-9c6c-9cbd05463aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839076063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.839076063
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1966025348
Short name T1124
Test name
Test status
Simulation time 793208594 ps
CPU time 11.08 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 209452 kb
Host smart-27d43833-a5f0-4069-886e-28a54746dd13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966025348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1966025348
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3148074300
Short name T390
Test name
Test status
Simulation time 1101068625 ps
CPU time 5.95 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 209476 kb
Host smart-13cb6d8b-4021-42df-b1f6-0a954f63500d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148074300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3148074300
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2083699301
Short name T1502
Test name
Test status
Simulation time 7238684205 ps
CPU time 102.17 seconds
Started Mar 19 03:16:08 PM PDT 24
Finished Mar 19 03:17:50 PM PDT 24
Peak memory 219608 kb
Host smart-7d40c2e4-3a65-4b2b-a985-effbb7352213
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083699301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2083699301
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.443214860
Short name T1016
Test name
Test status
Simulation time 3338678338 ps
CPU time 24.8 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 218592 kb
Host smart-ffa2897a-7c26-47ff-b777-d693880f1bc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443214860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.443214860
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3567153697
Short name T1518
Test name
Test status
Simulation time 429578851 ps
CPU time 6.61 seconds
Started Mar 19 03:16:07 PM PDT 24
Finished Mar 19 03:16:14 PM PDT 24
Peak memory 217968 kb
Host smart-a29b724e-6891-493c-a0b5-708c2f1acec6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567153697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3567153697
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.745110594
Short name T1612
Test name
Test status
Simulation time 549474117 ps
CPU time 5.8 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 217948 kb
Host smart-9b60982b-c6a3-4d6d-8301-6b3343cefc4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745110594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.745110594
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2608914136
Short name T1475
Test name
Test status
Simulation time 866657138 ps
CPU time 8.8 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 213660 kb
Host smart-ca49eda1-f0ee-4984-be2d-c58011567f7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608914136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2608914136
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.905893887
Short name T859
Test name
Test status
Simulation time 387637161 ps
CPU time 9.98 seconds
Started Mar 19 03:16:04 PM PDT 24
Finished Mar 19 03:16:14 PM PDT 24
Peak memory 213660 kb
Host smart-e5a54465-2539-4e5b-bf3a-949b3659b20e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905893887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
905893887
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2816500782
Short name T971
Test name
Test status
Simulation time 6557151254 ps
CPU time 57.14 seconds
Started Mar 19 03:16:08 PM PDT 24
Finished Mar 19 03:17:06 PM PDT 24
Peak memory 271320 kb
Host smart-8194dd63-1a2d-4bf0-93f1-f14ef22f09e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816500782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2816500782
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3813037928
Short name T457
Test name
Test status
Simulation time 14559987192 ps
CPU time 46.36 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:20:16 PM PDT 24
Peak memory 267476 kb
Host smart-90ade760-5541-4313-97d4-9b3fa3844f34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813037928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3813037928
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1663324882
Short name T354
Test name
Test status
Simulation time 413886559 ps
CPU time 10.81 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 246580 kb
Host smart-349c2f4d-2792-40f0-8606-1f8aa0e37d89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663324882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1663324882
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3059889779
Short name T585
Test name
Test status
Simulation time 849150179 ps
CPU time 16.77 seconds
Started Mar 19 03:16:08 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 250928 kb
Host smart-dc629663-2c17-44cf-b92c-765623e607f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059889779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3059889779
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1453727765
Short name T1700
Test name
Test status
Simulation time 146754644 ps
CPU time 2.33 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 221736 kb
Host smart-a6fe40b5-74fd-4d50-987f-5131a1465742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453727765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1453727765
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3056053413
Short name T458
Test name
Test status
Simulation time 82454219 ps
CPU time 4.37 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 222220 kb
Host smart-84412cd0-6587-4de5-8327-8ab1be22d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056053413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3056053413
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2607529446
Short name T1633
Test name
Test status
Simulation time 846511132 ps
CPU time 12.89 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 218172 kb
Host smart-6dbf2864-6114-4407-bd51-84cf94e2c3b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607529446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2607529446
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3564307155
Short name T1360
Test name
Test status
Simulation time 1214899362 ps
CPU time 11.3 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:40 PM PDT 24
Peak memory 218912 kb
Host smart-b4c576e1-059f-4421-9c2c-e72d8e876e63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564307155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3564307155
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.20842934
Short name T490
Test name
Test status
Simulation time 1782226105 ps
CPU time 12.75 seconds
Started Mar 19 03:16:12 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 217916 kb
Host smart-cc7ef218-592c-4fe9-ae4e-50ebea3d560f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20842934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_dig
est.20842934
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2941353186
Short name T678
Test name
Test status
Simulation time 354034761 ps
CPU time 10.9 seconds
Started Mar 19 03:19:38 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 217916 kb
Host smart-cab29baf-42a1-48fb-b60c-b61c849f4f92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941353186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2941353186
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.13571298
Short name T1347
Test name
Test status
Simulation time 363387976 ps
CPU time 10.11 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 217880 kb
Host smart-b178f89e-7a67-4710-aa0b-de52fd729b2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13571298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.13571298
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1414860017
Short name T719
Test name
Test status
Simulation time 587938078 ps
CPU time 10.49 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:40 PM PDT 24
Peak memory 217864 kb
Host smart-43020bd3-9754-46a1-9332-9c3fd5b89cdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414860017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1414860017
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1016696639
Short name T1108
Test name
Test status
Simulation time 1680835917 ps
CPU time 10.14 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 226032 kb
Host smart-20d9d7d9-33ae-4371-8fbf-e92fc56e030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016696639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1016696639
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1065592488
Short name T953
Test name
Test status
Simulation time 679596067 ps
CPU time 13.87 seconds
Started Mar 19 03:19:40 PM PDT 24
Finished Mar 19 03:19:54 PM PDT 24
Peak memory 224860 kb
Host smart-72c619cc-8119-41ab-8fbb-d9e239e8dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065592488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1065592488
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3530603361
Short name T280
Test name
Test status
Simulation time 55244332 ps
CPU time 2.98 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 213924 kb
Host smart-7114f725-7361-43c4-82da-7b841ca85b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530603361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3530603361
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.436382492
Short name T307
Test name
Test status
Simulation time 165986419 ps
CPU time 2.07 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 213788 kb
Host smart-6479c3a5-22cf-4525-9094-0d444892879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436382492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.436382492
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1078464941
Short name T1361
Test name
Test status
Simulation time 434054303 ps
CPU time 30.95 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 246716 kb
Host smart-497b4e1f-240a-417b-93a2-e0ff3816abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078464941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1078464941
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1902543398
Short name T1352
Test name
Test status
Simulation time 583906993 ps
CPU time 17.18 seconds
Started Mar 19 03:19:35 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 250968 kb
Host smart-feb81d6e-4da8-4f64-b503-ca57ac3a2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902543398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1902543398
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1141554583
Short name T511
Test name
Test status
Simulation time 88881919 ps
CPU time 7.85 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:13 PM PDT 24
Peak memory 250356 kb
Host smart-09657c81-4559-4b48-8242-22d1873f196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141554583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1141554583
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2594376587
Short name T1010
Test name
Test status
Simulation time 90539237 ps
CPU time 8.11 seconds
Started Mar 19 03:19:40 PM PDT 24
Finished Mar 19 03:19:48 PM PDT 24
Peak memory 250476 kb
Host smart-4c38bddc-12e0-4b8f-bce4-c201c827f50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594376587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2594376587
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1053636659
Short name T404
Test name
Test status
Simulation time 2609189875 ps
CPU time 84.55 seconds
Started Mar 19 03:16:12 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 246488 kb
Host smart-7123726e-c1aa-4fe7-9e0a-e3570f662b7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053636659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1053636659
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.737924239
Short name T962
Test name
Test status
Simulation time 15609397401 ps
CPU time 154.14 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 313548 kb
Host smart-407b4706-85ab-44b5-8c6a-359b97d239a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737924239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.737924239
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1021182412
Short name T1058
Test name
Test status
Simulation time 45497620 ps
CPU time 0.97 seconds
Started Mar 19 03:19:38 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 211604 kb
Host smart-74b6e247-2bf9-4ce6-922d-b3d583166d27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021182412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1021182412
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3516608765
Short name T1694
Test name
Test status
Simulation time 55742778 ps
CPU time 0.94 seconds
Started Mar 19 03:16:07 PM PDT 24
Finished Mar 19 03:16:08 PM PDT 24
Peak memory 212848 kb
Host smart-54fa73f3-f09f-4b99-ad13-a18efd95e5b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516608765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3516608765
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1310339285
Short name T1018
Test name
Test status
Simulation time 18708398 ps
CPU time 1.24 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:22 PM PDT 24
Peak memory 209528 kb
Host smart-555bae1b-2685-448e-97b2-253e7fe182f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310339285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1310339285
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1533741808
Short name T613
Test name
Test status
Simulation time 22305187 ps
CPU time 1.27 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 209684 kb
Host smart-a0380d0b-2b17-41d5-88ff-59cbf1d0b80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533741808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1533741808
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1750010780
Short name T933
Test name
Test status
Simulation time 784933739 ps
CPU time 18.98 seconds
Started Mar 19 03:19:37 PM PDT 24
Finished Mar 19 03:19:56 PM PDT 24
Peak memory 217952 kb
Host smart-bc51b6e3-e324-4f79-83ce-d524722c332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750010780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1750010780
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.4038183273
Short name T1587
Test name
Test status
Simulation time 211901294 ps
CPU time 10.28 seconds
Started Mar 19 03:16:12 PM PDT 24
Finished Mar 19 03:16:23 PM PDT 24
Peak memory 217968 kb
Host smart-c08e67fb-4d90-4c49-a2c5-dc37b9aca14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038183273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4038183273
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1762081042
Short name T842
Test name
Test status
Simulation time 446410465 ps
CPU time 11.78 seconds
Started Mar 19 03:16:16 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 209468 kb
Host smart-e0001a7f-e8a7-4bbf-8085-b7810ac9054a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762081042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1762081042
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.648909679
Short name T30
Test name
Test status
Simulation time 597955187 ps
CPU time 7.76 seconds
Started Mar 19 03:19:40 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 209436 kb
Host smart-c90a917e-d3d4-4298-9999-b97013a37e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648909679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.648909679
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1370397398
Short name T199
Test name
Test status
Simulation time 9095458443 ps
CPU time 36.43 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:56 PM PDT 24
Peak memory 218144 kb
Host smart-38a8cafc-a18a-445a-87c7-510463f4e84e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370397398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1370397398
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3998816905
Short name T1691
Test name
Test status
Simulation time 8490819830 ps
CPU time 55.27 seconds
Started Mar 19 03:19:31 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 218524 kb
Host smart-eb56d6ac-2fff-4d5c-8456-818469ac1f6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998816905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3998816905
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1279147576
Short name T1517
Test name
Test status
Simulation time 1621903340 ps
CPU time 12.04 seconds
Started Mar 19 03:19:37 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 217940 kb
Host smart-a67b4791-eeb8-4343-8d6b-611d14a7e964
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279147576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1279147576
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2000143464
Short name T1524
Test name
Test status
Simulation time 434028610 ps
CPU time 11.83 seconds
Started Mar 19 03:16:22 PM PDT 24
Finished Mar 19 03:16:34 PM PDT 24
Peak memory 217964 kb
Host smart-67a1206d-8a42-4a94-b2bd-2002be3aa1c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000143464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2000143464
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2363718067
Short name T911
Test name
Test status
Simulation time 155190361 ps
CPU time 4.56 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 213140 kb
Host smart-8b2051ea-2292-4f00-a9a8-9dc55357bd66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363718067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2363718067
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3680599121
Short name T399
Test name
Test status
Simulation time 738716347 ps
CPU time 5.48 seconds
Started Mar 19 03:19:36 PM PDT 24
Finished Mar 19 03:19:41 PM PDT 24
Peak memory 213448 kb
Host smart-d77bd1e0-a4fd-4135-9098-cfb31f23a78d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680599121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3680599121
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.327693158
Short name T1140
Test name
Test status
Simulation time 3217338088 ps
CPU time 26.49 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:16:44 PM PDT 24
Peak memory 251048 kb
Host smart-b2fa0169-86da-4456-a622-ddd9007ea64e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327693158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.327693158
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3824824646
Short name T1335
Test name
Test status
Simulation time 2024407386 ps
CPU time 36.68 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:20:10 PM PDT 24
Peak memory 270588 kb
Host smart-fad3a800-06ec-4371-afe4-b9d8c7578490
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824824646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3824824646
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1968607400
Short name T1373
Test name
Test status
Simulation time 410499225 ps
CPU time 17.51 seconds
Started Mar 19 03:19:36 PM PDT 24
Finished Mar 19 03:19:53 PM PDT 24
Peak memory 250860 kb
Host smart-3976bd17-b660-424a-9992-08177a8c462d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968607400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1968607400
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2256056916
Short name T1637
Test name
Test status
Simulation time 4784299080 ps
CPU time 10.03 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:20 PM PDT 24
Peak memory 218068 kb
Host smart-1df3f988-039a-4f46-8b5d-89c463527edd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256056916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2256056916
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1503250928
Short name T1220
Test name
Test status
Simulation time 1209616349 ps
CPU time 3.08 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 222068 kb
Host smart-cf46ca98-449b-43f2-ada5-8863a5dbd917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503250928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1503250928
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3172351075
Short name T1049
Test name
Test status
Simulation time 36316323 ps
CPU time 2.53 seconds
Started Mar 19 03:16:18 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 221616 kb
Host smart-42bb0e6d-0110-4857-8e38-b17903856881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172351075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3172351075
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.244132643
Short name T407
Test name
Test status
Simulation time 975258402 ps
CPU time 11.01 seconds
Started Mar 19 03:16:16 PM PDT 24
Finished Mar 19 03:16:27 PM PDT 24
Peak memory 218112 kb
Host smart-234b7bda-7e42-4832-925d-428a83c16343
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244132643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.244132643
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3701362637
Short name T1060
Test name
Test status
Simulation time 270145112 ps
CPU time 8.17 seconds
Started Mar 19 03:19:31 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 226320 kb
Host smart-95e3f0fd-0c38-4200-8051-acc0a3940ea8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701362637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3701362637
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.585632032
Short name T662
Test name
Test status
Simulation time 6994005141 ps
CPU time 14.13 seconds
Started Mar 19 03:19:31 PM PDT 24
Finished Mar 19 03:19:45 PM PDT 24
Peak memory 217988 kb
Host smart-a13cd556-87ef-43ed-9ffc-503cb30894a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585632032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.585632032
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.959520979
Short name T1151
Test name
Test status
Simulation time 2691793095 ps
CPU time 15.14 seconds
Started Mar 19 03:16:11 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 218012 kb
Host smart-77173e4f-7688-4936-b562-848787a21904
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959520979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.959520979
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2943875916
Short name T1627
Test name
Test status
Simulation time 733295385 ps
CPU time 8.54 seconds
Started Mar 19 03:16:14 PM PDT 24
Finished Mar 19 03:16:22 PM PDT 24
Peak memory 217352 kb
Host smart-62d85b51-02fc-41c8-92b3-9c64f7163034
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943875916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2943875916
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3341509598
Short name T1678
Test name
Test status
Simulation time 580124353 ps
CPU time 11.72 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:19:45 PM PDT 24
Peak memory 217936 kb
Host smart-6f9823fe-ad8e-4c59-abef-df2eafa512f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341509598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3341509598
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2930381644
Short name T1676
Test name
Test status
Simulation time 229202779 ps
CPU time 9.15 seconds
Started Mar 19 03:16:14 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 224880 kb
Host smart-0f158f2c-0a09-4b91-ae55-bff4ae7f1fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930381644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2930381644
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.4046681085
Short name T1274
Test name
Test status
Simulation time 2956018349 ps
CPU time 14.41 seconds
Started Mar 19 03:19:38 PM PDT 24
Finished Mar 19 03:19:53 PM PDT 24
Peak memory 226192 kb
Host smart-f52bc559-d481-4150-bb47-7b3a7c9adea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046681085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.4046681085
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.111375425
Short name T1069
Test name
Test status
Simulation time 104283378 ps
CPU time 7.21 seconds
Started Mar 19 03:19:39 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 217724 kb
Host smart-b7669dfb-1c66-4f46-9236-86605465c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111375425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.111375425
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2458122993
Short name T1698
Test name
Test status
Simulation time 38970432 ps
CPU time 2.58 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:23 PM PDT 24
Peak memory 214088 kb
Host smart-3a0bcf56-df8f-4625-a84b-15a8a49bdc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458122993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2458122993
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1146971819
Short name T561
Test name
Test status
Simulation time 224368458 ps
CPU time 24.92 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 250936 kb
Host smart-acb1c022-5983-4c05-9717-3ea3e96d6acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146971819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1146971819
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.215463870
Short name T655
Test name
Test status
Simulation time 2367951355 ps
CPU time 29.54 seconds
Started Mar 19 03:19:36 PM PDT 24
Finished Mar 19 03:20:06 PM PDT 24
Peak memory 251056 kb
Host smart-9bccbb51-7794-4ef6-b9d7-08fb878b4a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215463870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.215463870
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2661210213
Short name T1217
Test name
Test status
Simulation time 295150698 ps
CPU time 7.77 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:37 PM PDT 24
Peak memory 242764 kb
Host smart-d731b328-1a4e-40b0-99a9-17f69c33a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661210213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2661210213
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.886210574
Short name T262
Test name
Test status
Simulation time 142175042 ps
CPU time 8.98 seconds
Started Mar 19 03:16:13 PM PDT 24
Finished Mar 19 03:16:22 PM PDT 24
Peak memory 250900 kb
Host smart-28e3aef0-71d6-402d-8bcc-45595ab3a8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886210574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.886210574
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1209687149
Short name T1210
Test name
Test status
Simulation time 19110636348 ps
CPU time 120.71 seconds
Started Mar 19 03:19:38 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 283544 kb
Host smart-4fc85347-6de4-4131-9648-74209cf5bca4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209687149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1209687149
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3372524235
Short name T708
Test name
Test status
Simulation time 16143530502 ps
CPU time 462.12 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:23:59 PM PDT 24
Peak memory 251796 kb
Host smart-1c43f6ac-34af-4370-9e0d-9048ff831b9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372524235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3372524235
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.956333356
Short name T1300
Test name
Test status
Simulation time 43371358388 ps
CPU time 1871.76 seconds
Started Mar 19 03:16:11 PM PDT 24
Finished Mar 19 03:47:23 PM PDT 24
Peak memory 349492 kb
Host smart-dcedeb8a-3f21-4040-a674-08fa2b46ab70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=956333356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.956333356
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1197462727
Short name T1176
Test name
Test status
Simulation time 10222280 ps
CPU time 0.87 seconds
Started Mar 19 03:16:11 PM PDT 24
Finished Mar 19 03:16:12 PM PDT 24
Peak memory 208072 kb
Host smart-50109a4f-9dde-410b-ac48-b5167e89e707
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197462727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1197462727
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1745027078
Short name T516
Test name
Test status
Simulation time 19372930 ps
CPU time 1.4 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:43 PM PDT 24
Peak memory 212820 kb
Host smart-a6c47122-ea53-4ea0-a391-4f5be094f2d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745027078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1745027078
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3741154489
Short name T1492
Test name
Test status
Simulation time 13769748 ps
CPU time 0.84 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:30 PM PDT 24
Peak memory 209524 kb
Host smart-2c53942e-c2e3-46d0-814a-2ca04d985383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741154489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3741154489
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.4119911451
Short name T1036
Test name
Test status
Simulation time 15029181 ps
CPU time 0.85 seconds
Started Mar 19 03:16:11 PM PDT 24
Finished Mar 19 03:16:12 PM PDT 24
Peak memory 209580 kb
Host smart-4e44a56a-b417-4685-81c1-f7539f03a049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119911451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4119911451
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2158637442
Short name T683
Test name
Test status
Simulation time 398218120 ps
CPU time 17.26 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:19:45 PM PDT 24
Peak memory 226044 kb
Host smart-c3f9d739-2ded-48ab-ab2f-c12ec1709cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158637442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2158637442
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3043186206
Short name T493
Test name
Test status
Simulation time 347549820 ps
CPU time 11.25 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:16:29 PM PDT 24
Peak memory 217964 kb
Host smart-3a93241e-fcd8-42ab-85b1-62ade52be920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043186206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3043186206
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1572184774
Short name T583
Test name
Test status
Simulation time 5202665887 ps
CPU time 7.56 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 209580 kb
Host smart-3d607543-6dab-4ac6-ac34-10e14dffbea7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572184774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1572184774
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1938149837
Short name T983
Test name
Test status
Simulation time 2311747894 ps
CPU time 7.13 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:19:41 PM PDT 24
Peak memory 209516 kb
Host smart-d2b3499a-4db3-42d0-8b01-d88ddadd00ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938149837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1938149837
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.353973899
Short name T1002
Test name
Test status
Simulation time 2047739383 ps
CPU time 32.8 seconds
Started Mar 19 03:19:38 PM PDT 24
Finished Mar 19 03:20:11 PM PDT 24
Peak memory 217928 kb
Host smart-e2121631-4ce6-46f4-98de-7fb4ccf2e7d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353973899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.353973899
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.457019774
Short name T868
Test name
Test status
Simulation time 2770796856 ps
CPU time 34.91 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:55 PM PDT 24
Peak memory 219344 kb
Host smart-bcccc115-b61a-4885-8d3e-6fb43a6dfd64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457019774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.457019774
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1441763980
Short name T754
Test name
Test status
Simulation time 3754923540 ps
CPU time 11.4 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:41 PM PDT 24
Peak memory 218080 kb
Host smart-c2126120-6a33-4ac9-a041-e7ddbe0affc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441763980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1441763980
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3349891623
Short name T1372
Test name
Test status
Simulation time 114973249 ps
CPU time 4.68 seconds
Started Mar 19 03:16:12 PM PDT 24
Finished Mar 19 03:16:17 PM PDT 24
Peak memory 217968 kb
Host smart-564f450e-9be0-4fa2-bc35-831cd66704bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349891623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3349891623
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2015220801
Short name T949
Test name
Test status
Simulation time 135657421 ps
CPU time 4.14 seconds
Started Mar 19 03:16:14 PM PDT 24
Finished Mar 19 03:16:19 PM PDT 24
Peak memory 213028 kb
Host smart-f6adc606-37a6-4c0e-beed-b5f9a046d73f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015220801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2015220801
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3174490459
Short name T1247
Test name
Test status
Simulation time 233948982 ps
CPU time 4.15 seconds
Started Mar 19 03:19:35 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 213524 kb
Host smart-a702a8db-6234-404f-af2d-1f0e69d32e9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174490459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3174490459
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1857941288
Short name T1359
Test name
Test status
Simulation time 2829483803 ps
CPU time 48.59 seconds
Started Mar 19 03:19:31 PM PDT 24
Finished Mar 19 03:20:20 PM PDT 24
Peak memory 272532 kb
Host smart-47d7ba9c-ea57-4c43-bc57-52a5806eab9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857941288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1857941288
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2199078590
Short name T282
Test name
Test status
Simulation time 1658299088 ps
CPU time 51.68 seconds
Started Mar 19 03:16:18 PM PDT 24
Finished Mar 19 03:17:10 PM PDT 24
Peak memory 250944 kb
Host smart-fa047765-9d40-4190-8ebe-4a7922b76ad3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199078590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2199078590
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1257688106
Short name T1680
Test name
Test status
Simulation time 589479801 ps
CPU time 9.6 seconds
Started Mar 19 03:16:18 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 242776 kb
Host smart-56b60433-751e-4770-962d-c2da5475b766
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257688106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1257688106
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.153409951
Short name T341
Test name
Test status
Simulation time 1138228571 ps
CPU time 10.28 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:40 PM PDT 24
Peak memory 250916 kb
Host smart-239d3e61-341e-4b5d-a0a9-9d1292d87da6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153409951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.153409951
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1854167710
Short name T886
Test name
Test status
Simulation time 75531834 ps
CPU time 2.09 seconds
Started Mar 19 03:19:35 PM PDT 24
Finished Mar 19 03:19:37 PM PDT 24
Peak memory 221668 kb
Host smart-426778f9-80f4-424f-9e33-58f64a1ac5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854167710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1854167710
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4131239340
Short name T9
Test name
Test status
Simulation time 86499103 ps
CPU time 2.26 seconds
Started Mar 19 03:16:22 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 220996 kb
Host smart-23259349-d81d-44e1-8dd4-1e30b59a885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131239340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4131239340
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1200725660
Short name T790
Test name
Test status
Simulation time 2678548476 ps
CPU time 17.84 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 226124 kb
Host smart-de31407e-0c49-4698-bcc0-82857c5cd8b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200725660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1200725660
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.640212835
Short name T551
Test name
Test status
Simulation time 245497944 ps
CPU time 13.17 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:43 PM PDT 24
Peak memory 218160 kb
Host smart-87e18318-3583-41f3-9616-d8846ded0ebb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640212835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.640212835
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1699638687
Short name T756
Test name
Test status
Simulation time 325175597 ps
CPU time 11.12 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:22 PM PDT 24
Peak memory 217868 kb
Host smart-b55493c1-3f27-4b39-bc0d-9f617315c9cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699638687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1699638687
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.612144033
Short name T1313
Test name
Test status
Simulation time 653478258 ps
CPU time 18.47 seconds
Started Mar 19 03:19:36 PM PDT 24
Finished Mar 19 03:19:55 PM PDT 24
Peak memory 217912 kb
Host smart-98742313-b7b0-4e0c-8bbd-903338c331f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612144033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.612144033
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.16569880
Short name T1575
Test name
Test status
Simulation time 439740108 ps
CPU time 7.05 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 217956 kb
Host smart-d4b3487e-de27-4b55-8c91-113820da4ad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16569880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.16569880
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1698206520
Short name T1578
Test name
Test status
Simulation time 350183185 ps
CPU time 9.61 seconds
Started Mar 19 03:16:22 PM PDT 24
Finished Mar 19 03:16:32 PM PDT 24
Peak memory 217212 kb
Host smart-4af72af1-f942-410e-a963-bc978a6163d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698206520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1698206520
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2347368512
Short name T1122
Test name
Test status
Simulation time 681759918 ps
CPU time 5.84 seconds
Started Mar 19 03:16:11 PM PDT 24
Finished Mar 19 03:16:17 PM PDT 24
Peak memory 224360 kb
Host smart-33b575f9-7ecf-4190-9300-4e903b11ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347368512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2347368512
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.4048377132
Short name T1564
Test name
Test status
Simulation time 3787318966 ps
CPU time 13.15 seconds
Started Mar 19 03:19:39 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 226192 kb
Host smart-ade79c3e-4a04-4203-8a6d-5bf76a656a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048377132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.4048377132
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1058714921
Short name T312
Test name
Test status
Simulation time 66428355 ps
CPU time 2.5 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:13 PM PDT 24
Peak memory 217652 kb
Host smart-f04be234-7bcc-4ad9-8699-363012f91994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058714921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1058714921
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.971626781
Short name T364
Test name
Test status
Simulation time 265162762 ps
CPU time 2.97 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:32 PM PDT 24
Peak memory 214456 kb
Host smart-a355dc3e-7319-462d-8263-556eee578964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971626781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.971626781
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.215178519
Short name T1596
Test name
Test status
Simulation time 810070454 ps
CPU time 22.47 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:33 PM PDT 24
Peak memory 245472 kb
Host smart-a6fbfe7d-51bf-4f14-9109-811223fcbc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215178519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.215178519
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2867554708
Short name T918
Test name
Test status
Simulation time 940134976 ps
CPU time 26.92 seconds
Started Mar 19 03:19:38 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 250952 kb
Host smart-4686678f-e54d-4f54-8c8e-991a68e049ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867554708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2867554708
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1187056369
Short name T851
Test name
Test status
Simulation time 152774330 ps
CPU time 6.83 seconds
Started Mar 19 03:16:21 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 246864 kb
Host smart-3c38a701-1f09-45b8-87a9-15fafdbb4d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187056369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1187056369
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3626625556
Short name T863
Test name
Test status
Simulation time 65257811 ps
CPU time 6.57 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 250924 kb
Host smart-0b4e523b-8c80-4691-be80-68c3d6ee2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626625556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3626625556
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3434608698
Short name T1256
Test name
Test status
Simulation time 188291437 ps
CPU time 11.96 seconds
Started Mar 19 03:16:18 PM PDT 24
Finished Mar 19 03:16:30 PM PDT 24
Peak memory 245984 kb
Host smart-7667db51-f4c2-4be6-aeae-5565a4cdd3b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434608698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3434608698
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2435324382
Short name T171
Test name
Test status
Simulation time 37607766518 ps
CPU time 1278.43 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:41:00 PM PDT 24
Peak memory 389440 kb
Host smart-3d450a0e-0f03-4566-804c-81ca24367615
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2435324382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2435324382
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.334916600
Short name T966
Test name
Test status
Simulation time 11501630 ps
CPU time 0.96 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 211504 kb
Host smart-10e619c1-f0ec-47e9-b3e7-a1675482c29b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334916600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.334916600
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.920068860
Short name T915
Test name
Test status
Simulation time 21219948 ps
CPU time 1.07 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 211552 kb
Host smart-b70ae9f1-0323-4cb8-bbf4-22868ed3254b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920068860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.920068860
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2937035590
Short name T109
Test name
Test status
Simulation time 57883880 ps
CPU time 1.05 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 209580 kb
Host smart-436e1f29-71c7-47b9-be69-57b4e8bed533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937035590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2937035590
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.422221864
Short name T1450
Test name
Test status
Simulation time 37673311 ps
CPU time 0.81 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 209512 kb
Host smart-1dda1e06-d1f4-4832-9228-4c8e8ab76e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422221864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.422221864
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2707765270
Short name T1322
Test name
Test status
Simulation time 543316234 ps
CPU time 9.34 seconds
Started Mar 19 03:16:13 PM PDT 24
Finished Mar 19 03:16:22 PM PDT 24
Peak memory 225204 kb
Host smart-3ae92a49-3101-4628-a652-8f562b242f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707765270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2707765270
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.4209223359
Short name T278
Test name
Test status
Simulation time 537469764 ps
CPU time 15.75 seconds
Started Mar 19 03:19:35 PM PDT 24
Finished Mar 19 03:19:51 PM PDT 24
Peak memory 217936 kb
Host smart-b66e0ef1-b310-4dac-9972-04ddc9567c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209223359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.4209223359
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1310195499
Short name T712
Test name
Test status
Simulation time 127564929 ps
CPU time 1.18 seconds
Started Mar 19 03:19:31 PM PDT 24
Finished Mar 19 03:19:32 PM PDT 24
Peak memory 209488 kb
Host smart-044cf605-85f2-4687-bd84-69fee77a7204
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310195499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1310195499
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1764134032
Short name T1090
Test name
Test status
Simulation time 868849440 ps
CPU time 5.74 seconds
Started Mar 19 03:16:18 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 209484 kb
Host smart-e87a1904-c26a-48c9-9db8-fe64bebf9c10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764134032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1764134032
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1773985991
Short name T1369
Test name
Test status
Simulation time 9517898858 ps
CPU time 58.49 seconds
Started Mar 19 03:16:19 PM PDT 24
Finished Mar 19 03:17:18 PM PDT 24
Peak memory 218120 kb
Host smart-257a72a0-89ab-42b7-bf03-d2925064dc77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773985991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1773985991
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2349193215
Short name T1325
Test name
Test status
Simulation time 10997402682 ps
CPU time 71.9 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:20:54 PM PDT 24
Peak memory 218536 kb
Host smart-33e27e9d-bbe2-43fb-9245-39ba16fdea66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349193215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2349193215
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1487371006
Short name T1409
Test name
Test status
Simulation time 488441752 ps
CPU time 8.42 seconds
Started Mar 19 03:16:22 PM PDT 24
Finished Mar 19 03:16:30 PM PDT 24
Peak memory 217964 kb
Host smart-5e2f404c-17ca-4da4-8799-0045825ecf6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487371006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1487371006
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2841914478
Short name T291
Test name
Test status
Simulation time 145825079 ps
CPU time 5.4 seconds
Started Mar 19 03:19:37 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 217932 kb
Host smart-0b96db0d-e426-4e77-b168-3c3a1e6a5e61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841914478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2841914478
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1773107412
Short name T1507
Test name
Test status
Simulation time 144234700 ps
CPU time 2.96 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:23 PM PDT 24
Peak memory 213168 kb
Host smart-cddb3490-2698-468c-bbe3-19247a55df51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773107412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1773107412
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2529580360
Short name T21
Test name
Test status
Simulation time 877903344 ps
CPU time 6.26 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:37 PM PDT 24
Peak memory 213848 kb
Host smart-fcbd6663-9d0f-4d4f-be88-726ad4bb93bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529580360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2529580360
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2648678992
Short name T1527
Test name
Test status
Simulation time 27485819628 ps
CPU time 65.3 seconds
Started Mar 19 03:16:11 PM PDT 24
Finished Mar 19 03:17:17 PM PDT 24
Peak memory 272736 kb
Host smart-330a1cc8-dd31-48f5-adac-5fdc55be2111
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648678992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2648678992
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.564087832
Short name T1286
Test name
Test status
Simulation time 1307589720 ps
CPU time 50.59 seconds
Started Mar 19 03:19:40 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 270392 kb
Host smart-b791e1e4-7e4a-4145-a28d-846e08321c62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564087832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.564087832
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1108763853
Short name T438
Test name
Test status
Simulation time 2018095723 ps
CPU time 20.08 seconds
Started Mar 19 03:16:19 PM PDT 24
Finished Mar 19 03:16:40 PM PDT 24
Peak memory 249620 kb
Host smart-952894ac-94c5-41e5-ae17-c53713d9523d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108763853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1108763853
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2228345611
Short name T1669
Test name
Test status
Simulation time 3883059915 ps
CPU time 31.31 seconds
Started Mar 19 03:19:31 PM PDT 24
Finished Mar 19 03:20:02 PM PDT 24
Peak memory 247716 kb
Host smart-0dce863e-35d5-4543-8067-a1420e5361cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228345611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2228345611
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1498353522
Short name T1057
Test name
Test status
Simulation time 89931496 ps
CPU time 3.15 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:23 PM PDT 24
Peak memory 218040 kb
Host smart-0ebd5554-5ba2-41b5-a171-9af9ddb99cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498353522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1498353522
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3775070045
Short name T18
Test name
Test status
Simulation time 196203499 ps
CPU time 2.33 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 222132 kb
Host smart-f3a2af0f-9fdd-4d7f-8c4d-44197d308b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775070045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3775070045
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1172292175
Short name T1254
Test name
Test status
Simulation time 3218149697 ps
CPU time 16.11 seconds
Started Mar 19 03:19:36 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 226168 kb
Host smart-9d3aa20e-f39b-4397-a3d8-ee98c3bfba83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172292175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1172292175
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1654811705
Short name T38
Test name
Test status
Simulation time 2018789272 ps
CPU time 15.88 seconds
Started Mar 19 03:16:18 PM PDT 24
Finished Mar 19 03:16:34 PM PDT 24
Peak memory 225512 kb
Host smart-52fd09a5-0b0a-4682-94d0-ced1d291b09c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654811705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1654811705
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.159451691
Short name T1221
Test name
Test status
Simulation time 260678400 ps
CPU time 11.15 seconds
Started Mar 19 03:16:11 PM PDT 24
Finished Mar 19 03:16:23 PM PDT 24
Peak memory 217856 kb
Host smart-cbd9fc31-988f-4e0c-ae99-b548d9fe80cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159451691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.159451691
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.865577194
Short name T689
Test name
Test status
Simulation time 8454611138 ps
CPU time 17.27 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:48 PM PDT 24
Peak memory 218352 kb
Host smart-c0db65b3-544d-4372-ab96-0755f119c477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865577194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.865577194
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.243714917
Short name T1279
Test name
Test status
Simulation time 368374455 ps
CPU time 12.85 seconds
Started Mar 19 03:16:22 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 217908 kb
Host smart-bd29090b-f825-4308-8269-0d3b20fb1a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243714917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.243714917
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.443333379
Short name T1112
Test name
Test status
Simulation time 747473659 ps
CPU time 26.51 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:20:08 PM PDT 24
Peak memory 217940 kb
Host smart-09da4400-05f5-4cda-a217-1b27241c9a73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443333379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.443333379
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2012726806
Short name T1088
Test name
Test status
Simulation time 975763172 ps
CPU time 6.76 seconds
Started Mar 19 03:16:16 PM PDT 24
Finished Mar 19 03:16:23 PM PDT 24
Peak memory 224032 kb
Host smart-70c26779-3710-4ec2-ab68-36f7b5554192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012726806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2012726806
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3729573233
Short name T1368
Test name
Test status
Simulation time 263976198 ps
CPU time 7.87 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 224464 kb
Host smart-a4cae0ea-2966-43fe-9c4a-f93cccde0892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729573233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3729573233
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.410421228
Short name T1455
Test name
Test status
Simulation time 202371146 ps
CPU time 3.03 seconds
Started Mar 19 03:16:22 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 214556 kb
Host smart-ae11cc08-238a-4526-89f7-b6f8a317491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410421228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.410421228
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.4264745032
Short name T337
Test name
Test status
Simulation time 49559147 ps
CPU time 2.61 seconds
Started Mar 19 03:19:35 PM PDT 24
Finished Mar 19 03:19:38 PM PDT 24
Peak memory 214064 kb
Host smart-168bf440-3298-491b-b38c-f9ccd29d5cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264745032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4264745032
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3230640098
Short name T1255
Test name
Test status
Simulation time 992337966 ps
CPU time 26.18 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 250388 kb
Host smart-32d64b8d-8899-4ca5-8ded-9edd878d17ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230640098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3230640098
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.4047536667
Short name T586
Test name
Test status
Simulation time 197434119 ps
CPU time 23.39 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:16:41 PM PDT 24
Peak memory 250940 kb
Host smart-53ccc172-47cd-4872-b562-588e3d88a5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047536667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4047536667
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1325211338
Short name T634
Test name
Test status
Simulation time 330036523 ps
CPU time 7.37 seconds
Started Mar 19 03:19:35 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 246756 kb
Host smart-fcf8a49d-c66e-420b-8400-994d3e85c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325211338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1325211338
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3469579473
Short name T1330
Test name
Test status
Simulation time 83420504 ps
CPU time 6.67 seconds
Started Mar 19 03:16:14 PM PDT 24
Finished Mar 19 03:16:20 PM PDT 24
Peak memory 247032 kb
Host smart-e08f5162-5c27-4663-b16b-f73b6cb83443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469579473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3469579473
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2435619521
Short name T104
Test name
Test status
Simulation time 12499216841 ps
CPU time 67.38 seconds
Started Mar 19 03:16:19 PM PDT 24
Finished Mar 19 03:17:27 PM PDT 24
Peak memory 250628 kb
Host smart-9f96852b-74cd-4dcd-acc1-90358d0f14b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435619521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2435619521
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4113532713
Short name T17
Test name
Test status
Simulation time 2691878939 ps
CPU time 109.46 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:21:17 PM PDT 24
Peak memory 269796 kb
Host smart-dc813d9f-e637-4358-8863-4d13ec03a612
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113532713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4113532713
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1838381711
Short name T168
Test name
Test status
Simulation time 34375080939 ps
CPU time 258.44 seconds
Started Mar 19 03:19:38 PM PDT 24
Finished Mar 19 03:23:57 PM PDT 24
Peak memory 278884 kb
Host smart-4f291ce2-15dd-46f9-bcc1-7f617ac647c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1838381711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1838381711
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2819718780
Short name T865
Test name
Test status
Simulation time 47184079 ps
CPU time 0.88 seconds
Started Mar 19 03:19:39 PM PDT 24
Finished Mar 19 03:19:40 PM PDT 24
Peak memory 211508 kb
Host smart-5747ea09-4dfb-4cda-90d7-a4dce4e416eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819718780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2819718780
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.105602394
Short name T645
Test name
Test status
Simulation time 52000668 ps
CPU time 0.97 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:19:35 PM PDT 24
Peak memory 209596 kb
Host smart-afe2dcd0-007d-4d86-9235-183e7c79bbf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105602394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.105602394
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.273725085
Short name T1028
Test name
Test status
Simulation time 362812031 ps
CPU time 1.32 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 209592 kb
Host smart-a4d98d2b-a4bf-484d-9dc4-5a06a8a44ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273725085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.273725085
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1921713403
Short name T299
Test name
Test status
Simulation time 3304593617 ps
CPU time 17.49 seconds
Started Mar 19 03:16:21 PM PDT 24
Finished Mar 19 03:16:39 PM PDT 24
Peak memory 219036 kb
Host smart-ada344e0-a6a1-4d25-8b52-b28ae7ae143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921713403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1921713403
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.38536288
Short name T1671
Test name
Test status
Simulation time 862318536 ps
CPU time 13.27 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:54 PM PDT 24
Peak memory 217932 kb
Host smart-2ad6b8c2-afd6-4571-beaa-22a5fc79536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38536288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.38536288
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3866553132
Short name T112
Test name
Test status
Simulation time 1236238539 ps
CPU time 8.45 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:50 PM PDT 24
Peak memory 209452 kb
Host smart-1c71db05-1eb9-478a-9187-6290b96a0c91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866553132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3866553132
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.4260456694
Short name T1584
Test name
Test status
Simulation time 361490063 ps
CPU time 8.1 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 209552 kb
Host smart-a8f25957-68ca-4b57-93c3-5e8d3cbd17e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260456694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.4260456694
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1880471784
Short name T814
Test name
Test status
Simulation time 5186639021 ps
CPU time 20.99 seconds
Started Mar 19 03:19:31 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 218880 kb
Host smart-357ad59a-a5e8-49b4-b8fc-b4184c652081
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880471784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1880471784
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3151672474
Short name T378
Test name
Test status
Simulation time 1614505731 ps
CPU time 25.09 seconds
Started Mar 19 03:16:19 PM PDT 24
Finished Mar 19 03:16:45 PM PDT 24
Peak memory 218016 kb
Host smart-219aaa84-3f3f-498c-bdf9-c4cdccca4ce6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151672474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3151672474
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1528556237
Short name T679
Test name
Test status
Simulation time 360379976 ps
CPU time 11.13 seconds
Started Mar 19 03:19:28 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 218004 kb
Host smart-904c8d52-0a51-4906-9f1d-7e5b34a40861
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528556237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1528556237
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.213790629
Short name T1280
Test name
Test status
Simulation time 177902393 ps
CPU time 2.54 seconds
Started Mar 19 03:16:12 PM PDT 24
Finished Mar 19 03:16:14 PM PDT 24
Peak memory 217968 kb
Host smart-2d850bc6-5475-4a90-a60f-39d0452dca9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213790629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.213790629
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2655887191
Short name T717
Test name
Test status
Simulation time 151627895 ps
CPU time 2.82 seconds
Started Mar 19 03:16:21 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 213040 kb
Host smart-8403cee9-f90f-4bcc-aefd-27eb24893a2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655887191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2655887191
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4080647143
Short name T926
Test name
Test status
Simulation time 915487518 ps
CPU time 10.5 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:53 PM PDT 24
Peak memory 213496 kb
Host smart-71ba9890-9aa3-42ff-986d-534d7f4f5785
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080647143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4080647143
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.263259440
Short name T401
Test name
Test status
Simulation time 1765694765 ps
CPU time 43.16 seconds
Started Mar 19 03:16:21 PM PDT 24
Finished Mar 19 03:17:04 PM PDT 24
Peak memory 272052 kb
Host smart-b92c5323-e37f-4c45-8154-03d4e955640d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263259440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.263259440
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2741412833
Short name T1666
Test name
Test status
Simulation time 6325811818 ps
CPU time 50.96 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:20:34 PM PDT 24
Peak memory 269796 kb
Host smart-fde4e554-34a6-4b95-930e-043d499ef961
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741412833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2741412833
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1650006726
Short name T431
Test name
Test status
Simulation time 1601287625 ps
CPU time 22.47 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 250912 kb
Host smart-48e9da60-e827-4769-951b-9d3b3261ff80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650006726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1650006726
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.4053965437
Short name T614
Test name
Test status
Simulation time 780728737 ps
CPU time 13.38 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:55 PM PDT 24
Peak memory 250816 kb
Host smart-6722d9e3-f88a-41fa-bd3d-1808b6315d0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053965437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.4053965437
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1841111084
Short name T889
Test name
Test status
Simulation time 147417466 ps
CPU time 3.33 seconds
Started Mar 19 03:16:21 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 222116 kb
Host smart-1b0cb8e9-894c-4ca9-af8a-87dfc9d68c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841111084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1841111084
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.367422111
Short name T1296
Test name
Test status
Simulation time 19803677 ps
CPU time 1.7 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:43 PM PDT 24
Peak memory 217992 kb
Host smart-68b7f3c0-69fc-42a0-b7b1-7ea0f09739f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367422111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.367422111
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1858809798
Short name T978
Test name
Test status
Simulation time 1312979736 ps
CPU time 9.85 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 217940 kb
Host smart-a91308f4-6c97-4d0e-a98b-45a81c826525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858809798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1858809798
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3464175591
Short name T669
Test name
Test status
Simulation time 1745537009 ps
CPU time 9.69 seconds
Started Mar 19 03:16:10 PM PDT 24
Finished Mar 19 03:16:20 PM PDT 24
Peak memory 226112 kb
Host smart-afa968ee-bc22-4486-9bc3-d06a833c9fcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464175591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3464175591
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1735988818
Short name T739
Test name
Test status
Simulation time 411813773 ps
CPU time 12.77 seconds
Started Mar 19 03:16:33 PM PDT 24
Finished Mar 19 03:16:46 PM PDT 24
Peak memory 217868 kb
Host smart-31142066-dc35-439a-bc05-7db1412ace23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735988818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1735988818
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.974533677
Short name T1240
Test name
Test status
Simulation time 3199319968 ps
CPU time 11.49 seconds
Started Mar 19 03:19:39 PM PDT 24
Finished Mar 19 03:19:51 PM PDT 24
Peak memory 218064 kb
Host smart-a0096d43-859d-4bec-bf52-21ccece52518
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974533677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.974533677
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2230183467
Short name T885
Test name
Test status
Simulation time 803755584 ps
CPU time 11.35 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:53 PM PDT 24
Peak memory 217872 kb
Host smart-f1fcbbab-99af-45b4-be37-06771ba4e74a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230183467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2230183467
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4088336301
Short name T1554
Test name
Test status
Simulation time 1269173663 ps
CPU time 11.79 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:16:38 PM PDT 24
Peak memory 217836 kb
Host smart-a39247ea-7f41-41c5-948b-d49933a614fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088336301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4088336301
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1124748052
Short name T1192
Test name
Test status
Simulation time 224087110 ps
CPU time 8.93 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:29 PM PDT 24
Peak memory 224180 kb
Host smart-7479a76b-dec9-4096-82cf-6423bad7d3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124748052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1124748052
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3736959810
Short name T1532
Test name
Test status
Simulation time 1020369952 ps
CPU time 8.69 seconds
Started Mar 19 03:19:37 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 225168 kb
Host smart-c6ff7c03-4bab-4674-9e61-4eb2f4d28a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736959810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3736959810
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1964327788
Short name T774
Test name
Test status
Simulation time 28854060 ps
CPU time 2.08 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:16:19 PM PDT 24
Peak memory 213756 kb
Host smart-6218a865-64c2-470f-a8bb-34a7f5b21a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964327788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1964327788
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.4204924351
Short name T350
Test name
Test status
Simulation time 46155033 ps
CPU time 1.89 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:43 PM PDT 24
Peak memory 217656 kb
Host smart-fc5a8ff1-332c-485c-8fa0-42c9b08ffab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204924351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.4204924351
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2168673045
Short name T723
Test name
Test status
Simulation time 980844441 ps
CPU time 17.7 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:38 PM PDT 24
Peak memory 250960 kb
Host smart-40cd6855-2d54-4c54-a814-c5fa0f504be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168673045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2168673045
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.597646595
Short name T667
Test name
Test status
Simulation time 912857072 ps
CPU time 18.18 seconds
Started Mar 19 03:19:36 PM PDT 24
Finished Mar 19 03:19:54 PM PDT 24
Peak memory 250824 kb
Host smart-2e0f4edc-39ab-4099-b70f-924e0359c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597646595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.597646595
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3185782545
Short name T537
Test name
Test status
Simulation time 222674565 ps
CPU time 3.32 seconds
Started Mar 19 03:16:17 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 221932 kb
Host smart-251f1f95-69b3-4955-becc-f59926b5a64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185782545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3185782545
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3594101849
Short name T923
Test name
Test status
Simulation time 243589596 ps
CPU time 7.05 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:48 PM PDT 24
Peak memory 250920 kb
Host smart-3930e4c0-88da-4649-b4d7-b7f40362ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594101849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3594101849
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3064383945
Short name T807
Test name
Test status
Simulation time 4614941975 ps
CPU time 94.38 seconds
Started Mar 19 03:16:38 PM PDT 24
Finished Mar 19 03:18:13 PM PDT 24
Peak memory 280488 kb
Host smart-db108697-56fe-4b49-9d53-f14bef518bb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064383945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3064383945
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.84852943
Short name T1385
Test name
Test status
Simulation time 13533829375 ps
CPU time 84.28 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 267448 kb
Host smart-4e5cfb31-3cf5-4264-9f43-b8927fb60c69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84852943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.lc_ctrl_stress_all.84852943
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1229643065
Short name T231
Test name
Test status
Simulation time 100956237525 ps
CPU time 462.02 seconds
Started Mar 19 03:16:33 PM PDT 24
Finished Mar 19 03:24:15 PM PDT 24
Peak memory 281504 kb
Host smart-a986f128-6fee-474b-ade7-9c93cf18b216
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1229643065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1229643065
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2302764131
Short name T1338
Test name
Test status
Simulation time 57987130 ps
CPU time 0.95 seconds
Started Mar 19 03:16:20 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 211520 kb
Host smart-47c92d43-38e2-40e2-81b7-f34171b071b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302764131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2302764131
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4288998502
Short name T1599
Test name
Test status
Simulation time 19115174 ps
CPU time 0.94 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 211496 kb
Host smart-b6e2ca56-56ba-472c-aa76-1315959d8a29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288998502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4288998502
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2268353181
Short name T1405
Test name
Test status
Simulation time 61236659 ps
CPU time 1.48 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 209672 kb
Host smart-88391624-b6d1-4ae7-950f-313a2fc6b061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268353181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2268353181
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.393328597
Short name T273
Test name
Test status
Simulation time 54446777 ps
CPU time 1.03 seconds
Started Mar 19 03:19:43 PM PDT 24
Finished Mar 19 03:19:44 PM PDT 24
Peak memory 209584 kb
Host smart-fb07042e-0944-41c8-9428-4d944a9bc4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393328597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.393328597
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1923105670
Short name T825
Test name
Test status
Simulation time 300784405 ps
CPU time 14.35 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:57 PM PDT 24
Peak memory 226044 kb
Host smart-f1e6138b-b37d-40a5-999b-b9281b26f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923105670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1923105670
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2911260384
Short name T770
Test name
Test status
Simulation time 1373276852 ps
CPU time 25.62 seconds
Started Mar 19 03:16:29 PM PDT 24
Finished Mar 19 03:16:55 PM PDT 24
Peak memory 217896 kb
Host smart-e632396b-b238-414f-8685-32c260f48ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911260384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2911260384
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1725913980
Short name T97
Test name
Test status
Simulation time 346905401 ps
CPU time 4.07 seconds
Started Mar 19 03:19:48 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 209456 kb
Host smart-66dee872-6397-4ad0-956b-f8d4732dd895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725913980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1725913980
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3067476322
Short name T477
Test name
Test status
Simulation time 115707510 ps
CPU time 1.91 seconds
Started Mar 19 03:16:39 PM PDT 24
Finished Mar 19 03:16:41 PM PDT 24
Peak memory 216772 kb
Host smart-2201a4b4-92d6-4585-8af5-09a2646b04bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067476322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3067476322
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3039987885
Short name T35
Test name
Test status
Simulation time 17760005192 ps
CPU time 72.27 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:20:53 PM PDT 24
Peak memory 219648 kb
Host smart-496a9cac-1727-4310-a98d-aa795a1cbe4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039987885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3039987885
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.883188838
Short name T195
Test name
Test status
Simulation time 5462627416 ps
CPU time 41.7 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:17:09 PM PDT 24
Peak memory 218600 kb
Host smart-74cccc08-a32c-46f6-8541-9068c83b8492
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883188838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.883188838
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3988849953
Short name T891
Test name
Test status
Simulation time 676893563 ps
CPU time 6.06 seconds
Started Mar 19 03:19:46 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 218028 kb
Host smart-e49caade-306f-4d82-b50d-3f8f3f9cba8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988849953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3988849953
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.801089312
Short name T1337
Test name
Test status
Simulation time 512172915 ps
CPU time 3.81 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 218004 kb
Host smart-866a8128-bc0b-4095-a0ef-abdaab998e69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801089312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.801089312
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1016045417
Short name T913
Test name
Test status
Simulation time 3063216397 ps
CPU time 8.71 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:51 PM PDT 24
Peak memory 214464 kb
Host smart-4a96a7be-6156-42ec-ba08-1bc28a23ae5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016045417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1016045417
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3775919797
Short name T434
Test name
Test status
Simulation time 397493302 ps
CPU time 1.98 seconds
Started Mar 19 03:16:26 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 212960 kb
Host smart-fa56efff-9c28-4a45-844e-042f0a55c98c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775919797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3775919797
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1224553998
Short name T324
Test name
Test status
Simulation time 27920666411 ps
CPU time 43.18 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:20:29 PM PDT 24
Peak memory 270972 kb
Host smart-130f6704-4bff-40bb-9fd6-e26e0f1b0dbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224553998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1224553998
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.4096663979
Short name T388
Test name
Test status
Simulation time 18532733925 ps
CPU time 64.18 seconds
Started Mar 19 03:16:38 PM PDT 24
Finished Mar 19 03:17:43 PM PDT 24
Peak memory 283736 kb
Host smart-b81927c2-5a66-4904-81d1-3fefb0d536f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096663979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.4096663979
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3861397864
Short name T1402
Test name
Test status
Simulation time 442055023 ps
CPU time 11.97 seconds
Started Mar 19 03:16:34 PM PDT 24
Finished Mar 19 03:16:46 PM PDT 24
Peak memory 250432 kb
Host smart-e9dd8b53-119f-4bb0-a67a-8c513e17af10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861397864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3861397864
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.492038954
Short name T1249
Test name
Test status
Simulation time 1949202571 ps
CPU time 19.04 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 250916 kb
Host smart-1dcb98dd-42fc-4136-bf59-51dc319b322f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492038954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.492038954
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2690325427
Short name T1583
Test name
Test status
Simulation time 190293333 ps
CPU time 3.54 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 218024 kb
Host smart-0c25c104-5696-40f9-b43e-2725163dcc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690325427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2690325427
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3596711750
Short name T379
Test name
Test status
Simulation time 295588141 ps
CPU time 3.94 seconds
Started Mar 19 03:16:26 PM PDT 24
Finished Mar 19 03:16:31 PM PDT 24
Peak memory 218044 kb
Host smart-6d70c086-bcb8-4ae6-bb83-7b31f352351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596711750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3596711750
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1356970437
Short name T1326
Test name
Test status
Simulation time 5352061863 ps
CPU time 16.46 seconds
Started Mar 19 03:19:53 PM PDT 24
Finished Mar 19 03:20:10 PM PDT 24
Peak memory 226200 kb
Host smart-b355efda-b207-4ae3-9fe3-f36a63e4e2c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356970437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1356970437
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3233109465
Short name T1500
Test name
Test status
Simulation time 516206410 ps
CPU time 23.38 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:48 PM PDT 24
Peak memory 218912 kb
Host smart-64502de1-5c1f-4abb-9693-7a4514fe588c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233109465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3233109465
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2213658050
Short name T948
Test name
Test status
Simulation time 1540292810 ps
CPU time 11.1 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 217864 kb
Host smart-3ac61c31-9636-42c6-abed-f2bd82034e30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213658050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2213658050
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.453904511
Short name T795
Test name
Test status
Simulation time 617583002 ps
CPU time 14.07 seconds
Started Mar 19 03:19:53 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 217928 kb
Host smart-9ea47248-4c3e-4238-8fcb-72dcddc9b45a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453904511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.453904511
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1268279037
Short name T1674
Test name
Test status
Simulation time 1461039127 ps
CPU time 11.26 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:52 PM PDT 24
Peak memory 217864 kb
Host smart-0b57b6ce-b78c-46e3-aa14-1ca029426ee3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268279037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1268279037
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1654417350
Short name T729
Test name
Test status
Simulation time 1315315595 ps
CPU time 8.17 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:16:34 PM PDT 24
Peak memory 217900 kb
Host smart-642c8f2d-c40f-4f43-ad72-68816ff1d4c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654417350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1654417350
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3560711065
Short name T1458
Test name
Test status
Simulation time 349661173 ps
CPU time 9.07 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:16:32 PM PDT 24
Peak memory 224964 kb
Host smart-13312765-a377-44d9-bbb7-3339a1610d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560711065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3560711065
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3981302357
Short name T247
Test name
Test status
Simulation time 212011796 ps
CPU time 7.32 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:50 PM PDT 24
Peak memory 224524 kb
Host smart-34154435-2e0e-4455-9e3f-eda64ab4c29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981302357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3981302357
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3495139105
Short name T1305
Test name
Test status
Simulation time 41370178 ps
CPU time 2.34 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:31 PM PDT 24
Peak memory 217756 kb
Host smart-10a16897-94f9-4027-b739-0e202c82fd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495139105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3495139105
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.90370111
Short name T258
Test name
Test status
Simulation time 204417283 ps
CPU time 2.37 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 214112 kb
Host smart-db9e8981-a613-4db5-841a-e067574160af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90370111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.90370111
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2531237126
Short name T1188
Test name
Test status
Simulation time 321086883 ps
CPU time 27.67 seconds
Started Mar 19 03:16:34 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 250740 kb
Host smart-9b613043-8fe9-4d9c-ab41-0c8f15a114c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531237126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2531237126
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2552928566
Short name T1177
Test name
Test status
Simulation time 256057343 ps
CPU time 24.87 seconds
Started Mar 19 03:19:47 PM PDT 24
Finished Mar 19 03:20:13 PM PDT 24
Peak memory 250732 kb
Host smart-50151051-0a5e-4858-87d1-8d996dd2f5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552928566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2552928566
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2128558743
Short name T625
Test name
Test status
Simulation time 1217557706 ps
CPU time 7.53 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 246616 kb
Host smart-7a50f5d5-4d1f-45a0-996e-b5c7c179d917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128558743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2128558743
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3803562414
Short name T410
Test name
Test status
Simulation time 507809387 ps
CPU time 9.42 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:44 PM PDT 24
Peak memory 248600 kb
Host smart-1f5e5d7d-732b-48f4-a239-94fe0b4c2153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803562414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3803562414
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2941475985
Short name T1319
Test name
Test status
Simulation time 886351824 ps
CPU time 30.66 seconds
Started Mar 19 03:19:47 PM PDT 24
Finished Mar 19 03:20:18 PM PDT 24
Peak memory 250880 kb
Host smart-286d2305-1235-422d-8b6a-b487c716b501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941475985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2941475985
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3749439717
Short name T1387
Test name
Test status
Simulation time 216178489763 ps
CPU time 534.41 seconds
Started Mar 19 03:16:33 PM PDT 24
Finished Mar 19 03:25:28 PM PDT 24
Peak memory 283716 kb
Host smart-c6f8eed7-1d4b-43d2-b18b-4f6c6141f125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749439717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3749439717
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2533941350
Short name T232
Test name
Test status
Simulation time 66357126690 ps
CPU time 512.8 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:24:56 PM PDT 24
Peak memory 267568 kb
Host smart-9a70ebf0-a829-4a6e-b9e6-68c133d19c92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2533941350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2533941350
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3036869547
Short name T1656
Test name
Test status
Simulation time 28142247 ps
CPU time 0.83 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:16:29 PM PDT 24
Peak memory 211556 kb
Host smart-ed9f8eb9-8f79-416d-b895-b5cbd742b1ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036869547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3036869547
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3166585660
Short name T294
Test name
Test status
Simulation time 12126916 ps
CPU time 0.81 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:19:35 PM PDT 24
Peak memory 211588 kb
Host smart-b681a535-e5e6-40b7-8641-61e3308df441
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166585660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3166585660
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4148285962
Short name T304
Test name
Test status
Simulation time 83047772 ps
CPU time 0.91 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 209564 kb
Host smart-4211194a-2d6f-4ec6-9b8a-51e0ae543fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148285962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4148285962
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.672102303
Short name T694
Test name
Test status
Simulation time 16828657 ps
CPU time 0.91 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 209568 kb
Host smart-876da71a-e8c1-46de-b5ef-8a773a2f76cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672102303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.672102303
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1993486932
Short name T528
Test name
Test status
Simulation time 782646545 ps
CPU time 9.12 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:34 PM PDT 24
Peak memory 217968 kb
Host smart-59e1a2ed-2660-4e66-94fe-02ab404c5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993486932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1993486932
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.229972612
Short name T1414
Test name
Test status
Simulation time 667033038 ps
CPU time 13.87 seconds
Started Mar 19 03:19:40 PM PDT 24
Finished Mar 19 03:19:54 PM PDT 24
Peak memory 217888 kb
Host smart-7daad77a-c593-418b-a888-b471eb85c993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229972612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.229972612
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2636656955
Short name T1417
Test name
Test status
Simulation time 1252304319 ps
CPU time 9.48 seconds
Started Mar 19 03:16:27 PM PDT 24
Finished Mar 19 03:16:37 PM PDT 24
Peak memory 216832 kb
Host smart-3dbc2bec-e7ba-4ccc-87e3-aa9288f808b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636656955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2636656955
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.998655652
Short name T840
Test name
Test status
Simulation time 1665344739 ps
CPU time 10.2 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:19:56 PM PDT 24
Peak memory 209492 kb
Host smart-bfc6915a-beed-4d7d-bd8e-9f4baa8fed4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998655652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.998655652
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4099217663
Short name T1690
Test name
Test status
Simulation time 6779102557 ps
CPU time 28.88 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:53 PM PDT 24
Peak memory 219044 kb
Host smart-da176371-a191-47d1-b839-25a7a8324d6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099217663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4099217663
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4276950199
Short name T1137
Test name
Test status
Simulation time 2558256524 ps
CPU time 69.15 seconds
Started Mar 19 03:19:50 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 219016 kb
Host smart-3acc118e-a350-4ad5-b4ab-52ff72bf805b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276950199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4276950199
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1156867531
Short name T1470
Test name
Test status
Simulation time 1676879628 ps
CPU time 6.09 seconds
Started Mar 19 03:19:48 PM PDT 24
Finished Mar 19 03:19:54 PM PDT 24
Peak memory 217964 kb
Host smart-75038929-8ccd-41d1-889d-044de5e0e588
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156867531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1156867531
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1866100318
Short name T1446
Test name
Test status
Simulation time 325579045 ps
CPU time 10.91 seconds
Started Mar 19 03:16:39 PM PDT 24
Finished Mar 19 03:16:50 PM PDT 24
Peak memory 218004 kb
Host smart-553cf439-d1da-40cf-9372-7f34834a3ef9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866100318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1866100318
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2093899821
Short name T637
Test name
Test status
Simulation time 390440919 ps
CPU time 10.53 seconds
Started Mar 19 03:19:46 PM PDT 24
Finished Mar 19 03:19:57 PM PDT 24
Peak memory 213724 kb
Host smart-fa18f4d4-a8a6-4067-bc38-5dc6d9ca1bfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093899821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2093899821
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2281990358
Short name T422
Test name
Test status
Simulation time 4885375711 ps
CPU time 8.65 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 214512 kb
Host smart-bb5550cf-d70f-4423-857c-cec09789a98f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281990358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2281990358
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3563626231
Short name T620
Test name
Test status
Simulation time 2794809587 ps
CPU time 63.62 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:17:28 PM PDT 24
Peak memory 271904 kb
Host smart-bdd3ac77-ce0f-460f-9471-f7c0010ab5d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563626231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3563626231
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.569345699
Short name T330
Test name
Test status
Simulation time 5209642393 ps
CPU time 35.44 seconds
Started Mar 19 03:19:46 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 251012 kb
Host smart-2751ac5c-f963-4f2c-9adc-bc90cb6ad421
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569345699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.569345699
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2892256170
Short name T348
Test name
Test status
Simulation time 4370775667 ps
CPU time 32.02 seconds
Started Mar 19 03:16:39 PM PDT 24
Finished Mar 19 03:17:11 PM PDT 24
Peak memory 250632 kb
Host smart-04f83ae4-38a2-4b48-a3dd-ed5be039b905
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892256170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2892256170
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.605459508
Short name T478
Test name
Test status
Simulation time 494878889 ps
CPU time 20.71 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:20:06 PM PDT 24
Peak memory 245092 kb
Host smart-b0b2cc5f-7238-4cee-82b5-704070628f6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605459508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.605459508
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1411316251
Short name T1170
Test name
Test status
Simulation time 58543914 ps
CPU time 2.15 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:19:47 PM PDT 24
Peak memory 221604 kb
Host smart-a761537a-656f-49a3-b3e3-f7370a8ea5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411316251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1411316251
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1601576106
Short name T1267
Test name
Test status
Simulation time 79895731 ps
CPU time 2.51 seconds
Started Mar 19 03:16:26 PM PDT 24
Finished Mar 19 03:16:29 PM PDT 24
Peak memory 218016 kb
Host smart-5ecb99e6-1474-43c5-a326-d0ed9945389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601576106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1601576106
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1143360808
Short name T541
Test name
Test status
Simulation time 276762634 ps
CPU time 13.16 seconds
Started Mar 19 03:16:39 PM PDT 24
Finished Mar 19 03:16:52 PM PDT 24
Peak memory 226036 kb
Host smart-53634016-4785-4193-93b1-98509fc07cac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143360808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1143360808
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2072436816
Short name T666
Test name
Test status
Simulation time 799933875 ps
CPU time 10.87 seconds
Started Mar 19 03:19:51 PM PDT 24
Finished Mar 19 03:20:02 PM PDT 24
Peak memory 226032 kb
Host smart-a8ed4874-c269-4767-8cd0-b3fd456c1ae5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072436816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2072436816
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1818496850
Short name T1419
Test name
Test status
Simulation time 417933726 ps
CPU time 11.55 seconds
Started Mar 19 03:19:43 PM PDT 24
Finished Mar 19 03:19:55 PM PDT 24
Peak memory 217860 kb
Host smart-4eadb9c0-ae5e-4ece-b97a-c27bd3bae5a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818496850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1818496850
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.600537011
Short name T921
Test name
Test status
Simulation time 1527054220 ps
CPU time 14.04 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 217860 kb
Host smart-f3de8031-274d-404d-9036-06136ad31245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600537011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.600537011
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3421333112
Short name T650
Test name
Test status
Simulation time 483948999 ps
CPU time 7.78 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:16:36 PM PDT 24
Peak memory 217912 kb
Host smart-75bb3437-f115-4baf-b466-af30c7e01314
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421333112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3421333112
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.502282698
Short name T648
Test name
Test status
Simulation time 293190374 ps
CPU time 6.61 seconds
Started Mar 19 03:19:44 PM PDT 24
Finished Mar 19 03:19:51 PM PDT 24
Peak memory 217952 kb
Host smart-83250b94-12ec-4ee5-9687-cc0fe670b416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502282698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.502282698
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1153926945
Short name T1064
Test name
Test status
Simulation time 170308108 ps
CPU time 8.09 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 225344 kb
Host smart-47ff5f25-6a90-413b-ab49-0ee18b2630f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153926945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1153926945
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3517802207
Short name T777
Test name
Test status
Simulation time 1608373463 ps
CPU time 15.3 seconds
Started Mar 19 03:19:47 PM PDT 24
Finished Mar 19 03:20:04 PM PDT 24
Peak memory 224804 kb
Host smart-8fbbfcb7-e815-4d2e-8e48-cda30a99e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517802207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3517802207
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1232776430
Short name T79
Test name
Test status
Simulation time 56680257 ps
CPU time 1.99 seconds
Started Mar 19 03:19:47 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 217872 kb
Host smart-2ac95fcc-7c03-4574-8607-1de0152dde35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232776430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1232776430
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.582840526
Short name T1461
Test name
Test status
Simulation time 28427347 ps
CPU time 1.84 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:16:30 PM PDT 24
Peak memory 217608 kb
Host smart-a552dc5a-1bc0-463e-929a-af841cd3e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582840526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.582840526
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1918043543
Short name T686
Test name
Test status
Simulation time 376464308 ps
CPU time 20.97 seconds
Started Mar 19 03:19:43 PM PDT 24
Finished Mar 19 03:20:04 PM PDT 24
Peak memory 245564 kb
Host smart-c55031f7-f82e-4eb1-82f4-e2b1d0bcaf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918043543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1918043543
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4104789209
Short name T1595
Test name
Test status
Simulation time 498615644 ps
CPU time 31.35 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:16:55 PM PDT 24
Peak memory 248652 kb
Host smart-e3297256-2673-468f-bfc6-79c9d5bf12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104789209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4104789209
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2595385629
Short name T420
Test name
Test status
Simulation time 83113247 ps
CPU time 9.51 seconds
Started Mar 19 03:19:44 PM PDT 24
Finished Mar 19 03:19:53 PM PDT 24
Peak memory 250972 kb
Host smart-a6dd2f7c-513e-4179-af59-1725a885ede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595385629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2595385629
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3237149242
Short name T1516
Test name
Test status
Simulation time 343706328 ps
CPU time 2.77 seconds
Started Mar 19 03:16:33 PM PDT 24
Finished Mar 19 03:16:36 PM PDT 24
Peak memory 222088 kb
Host smart-9c42d45a-617a-4a9d-b8d2-a037b59a60ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237149242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3237149242
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.307320321
Short name T618
Test name
Test status
Simulation time 29413739507 ps
CPU time 143.33 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 270836 kb
Host smart-aaed2f04-c159-4e46-b74c-efeae7bee7de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307320321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.307320321
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.633367113
Short name T1015
Test name
Test status
Simulation time 7265770153 ps
CPU time 98.91 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 279784 kb
Host smart-a1880fcc-ed7b-4dab-aeb6-04b6267fbe74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633367113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.633367113
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1480504951
Short name T54
Test name
Test status
Simulation time 12611190383 ps
CPU time 423.53 seconds
Started Mar 19 03:19:46 PM PDT 24
Finished Mar 19 03:26:50 PM PDT 24
Peak memory 316756 kb
Host smart-8266d8c3-22b2-48b2-95ab-26d1886b2fbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1480504951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1480504951
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2946897076
Short name T351
Test name
Test status
Simulation time 14488673 ps
CPU time 0.92 seconds
Started Mar 19 03:16:27 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 211472 kb
Host smart-7571bf36-2110-49d4-9838-591ba61f9317
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946897076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2946897076
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2963959280
Short name T542
Test name
Test status
Simulation time 76058339 ps
CPU time 0.91 seconds
Started Mar 19 03:19:44 PM PDT 24
Finished Mar 19 03:19:45 PM PDT 24
Peak memory 212768 kb
Host smart-38b4a9a6-17d4-4422-9ffa-ca502200b8a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963959280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2963959280
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2133884195
Short name T1051
Test name
Test status
Simulation time 17158065 ps
CPU time 1.11 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:19:59 PM PDT 24
Peak memory 209612 kb
Host smart-ae3e977d-135b-4f7c-985b-34fd57f07651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133884195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2133884195
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3547962308
Short name T944
Test name
Test status
Simulation time 23764101 ps
CPU time 1 seconds
Started Mar 19 03:16:34 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 209624 kb
Host smart-bc32fd61-7579-46f4-8e68-33a816b58d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547962308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3547962308
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1105921329
Short name T1476
Test name
Test status
Simulation time 1434257981 ps
CPU time 13.57 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:56 PM PDT 24
Peak memory 226036 kb
Host smart-78a059a6-1538-4bdf-9eee-51c522c2ee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105921329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1105921329
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.4092611603
Short name T845
Test name
Test status
Simulation time 1516284918 ps
CPU time 10.48 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:16:36 PM PDT 24
Peak memory 217904 kb
Host smart-5576d79e-5f28-48f1-9731-afdaa04050f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092611603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.4092611603
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3589680547
Short name T1008
Test name
Test status
Simulation time 328723380 ps
CPU time 4.56 seconds
Started Mar 19 03:19:57 PM PDT 24
Finished Mar 19 03:20:02 PM PDT 24
Peak memory 217056 kb
Host smart-2ea75648-cde9-45d3-96bb-66fe36324783
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589680547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3589680547
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3972792370
Short name T1589
Test name
Test status
Simulation time 1880504021 ps
CPU time 22.66 seconds
Started Mar 19 03:16:23 PM PDT 24
Finished Mar 19 03:16:46 PM PDT 24
Peak memory 209480 kb
Host smart-9234a876-66d0-48e1-8aaf-1ca54ecfe64f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972792370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3972792370
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2150112427
Short name T1512
Test name
Test status
Simulation time 3210209713 ps
CPU time 48.12 seconds
Started Mar 19 03:20:00 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 219200 kb
Host smart-c5d8d01f-8df5-4e82-b4cf-9dfe08309138
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150112427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2150112427
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.22364364
Short name T284
Test name
Test status
Simulation time 2524473382 ps
CPU time 39.1 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 219008 kb
Host smart-378deb45-e4e5-429e-8965-b0b1653d3d6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22364364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_err
ors.22364364
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1993030380
Short name T692
Test name
Test status
Simulation time 5342369031 ps
CPU time 11.25 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 218088 kb
Host smart-2565ec1a-989d-4b3d-b59e-0088a35cc85c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993030380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1993030380
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.859490377
Short name T274
Test name
Test status
Simulation time 944667177 ps
CPU time 9.49 seconds
Started Mar 19 03:16:32 PM PDT 24
Finished Mar 19 03:16:42 PM PDT 24
Peak memory 217936 kb
Host smart-c6f1c0ae-63b4-4a3a-817f-1c529016e518
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859490377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.859490377
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1127300617
Short name T1404
Test name
Test status
Simulation time 83562460 ps
CPU time 3.13 seconds
Started Mar 19 03:19:46 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 212944 kb
Host smart-8f156e4d-9f5d-4b6e-8fbe-d0dfb8c9bf02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127300617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1127300617
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1515845176
Short name T78
Test name
Test status
Simulation time 1188944149 ps
CPU time 12.8 seconds
Started Mar 19 03:16:38 PM PDT 24
Finished Mar 19 03:16:52 PM PDT 24
Peak memory 213572 kb
Host smart-9fb6a77d-407f-4827-9557-7dda27c1891a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515845176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1515845176
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1744189932
Short name T328
Test name
Test status
Simulation time 71441510309 ps
CPU time 119.76 seconds
Started Mar 19 03:19:53 PM PDT 24
Finished Mar 19 03:21:53 PM PDT 24
Peak memory 271996 kb
Host smart-4a88508c-c04b-42a1-a9b1-0817c4d174a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744189932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1744189932
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3743606816
Short name T721
Test name
Test status
Simulation time 1386906508 ps
CPU time 35.54 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:17:11 PM PDT 24
Peak memory 268708 kb
Host smart-f3cbf227-9d35-4090-9d30-ef43f0c4fa13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743606816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3743606816
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2077816731
Short name T1141
Test name
Test status
Simulation time 848296357 ps
CPU time 29.79 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:54 PM PDT 24
Peak memory 247232 kb
Host smart-5ddf3c30-5129-4800-b822-b67a5e66c983
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077816731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2077816731
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3406070260
Short name T492
Test name
Test status
Simulation time 421652446 ps
CPU time 13.04 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:20:09 PM PDT 24
Peak memory 250940 kb
Host smart-bf490039-c243-421d-97d9-698078b32207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406070260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3406070260
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1516749435
Short name T1418
Test name
Test status
Simulation time 409485685 ps
CPU time 3.84 seconds
Started Mar 19 03:16:29 PM PDT 24
Finished Mar 19 03:16:33 PM PDT 24
Peak memory 221792 kb
Host smart-48a9a104-6104-4b77-9393-1ddbd4ac20e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516749435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1516749435
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.4137823884
Short name T454
Test name
Test status
Simulation time 29640244 ps
CPU time 1.99 seconds
Started Mar 19 03:19:42 PM PDT 24
Finished Mar 19 03:19:45 PM PDT 24
Peak memory 221540 kb
Host smart-3c10a918-d257-4688-98a1-7cb2a6ff3606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137823884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.4137823884
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1269595944
Short name T1011
Test name
Test status
Simulation time 327248273 ps
CPU time 13.37 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:38 PM PDT 24
Peak memory 226068 kb
Host smart-f9d1cbe2-8dfd-446c-9f71-bb8cc708abc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269595944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1269595944
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2751403153
Short name T498
Test name
Test status
Simulation time 1042300462 ps
CPU time 9.2 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:08 PM PDT 24
Peak memory 225948 kb
Host smart-9961a2f1-de8e-4fed-89b0-f310fc5d2912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751403153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2751403153
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1165242320
Short name T1389
Test name
Test status
Simulation time 2939957593 ps
CPU time 15.5 seconds
Started Mar 19 03:20:04 PM PDT 24
Finished Mar 19 03:20:20 PM PDT 24
Peak memory 218036 kb
Host smart-fdb86435-e827-420e-9d3e-e7b6e1328914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165242320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1165242320
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3731174870
Short name T473
Test name
Test status
Simulation time 595877163 ps
CPU time 16.52 seconds
Started Mar 19 03:16:33 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 217868 kb
Host smart-da4f3c50-0453-413b-ae61-f129a5e34611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731174870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3731174870
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2121464990
Short name T785
Test name
Test status
Simulation time 225370814 ps
CPU time 7.26 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 217976 kb
Host smart-47ee0884-db45-4dc9-94d5-fb041e58c3d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121464990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2121464990
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2700771625
Short name T832
Test name
Test status
Simulation time 558736562 ps
CPU time 11.63 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:16:37 PM PDT 24
Peak memory 217848 kb
Host smart-9d47256f-fd3e-4cc2-a8ad-06ee6a95d698
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700771625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2700771625
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3135262721
Short name T1146
Test name
Test status
Simulation time 1244456745 ps
CPU time 14.29 seconds
Started Mar 19 03:19:44 PM PDT 24
Finished Mar 19 03:19:58 PM PDT 24
Peak memory 226072 kb
Host smart-6a4db924-00f2-45b5-a3c6-dba550cc0d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135262721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3135262721
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3704133172
Short name T922
Test name
Test status
Simulation time 343181533 ps
CPU time 13.32 seconds
Started Mar 19 03:16:24 PM PDT 24
Finished Mar 19 03:16:38 PM PDT 24
Peak memory 224860 kb
Host smart-dde2665d-b437-4fe3-9c6e-b77a1ff7d425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704133172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3704133172
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.700778051
Short name T391
Test name
Test status
Simulation time 50060629 ps
CPU time 0.99 seconds
Started Mar 19 03:16:25 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 212664 kb
Host smart-742b86f2-e5c1-45db-bccf-d9ce85636be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700778051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.700778051
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.194521140
Short name T1576
Test name
Test status
Simulation time 783624672 ps
CPU time 20.04 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:16:48 PM PDT 24
Peak memory 245796 kb
Host smart-cf481cd7-767d-4f21-b78f-e04fe83e4eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194521140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.194521140
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3030736276
Short name T820
Test name
Test status
Simulation time 282801243 ps
CPU time 31.46 seconds
Started Mar 19 03:19:41 PM PDT 24
Finished Mar 19 03:20:13 PM PDT 24
Peak memory 250880 kb
Host smart-c7fbab69-40fe-4a9e-b634-a941c8e7a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030736276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3030736276
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2487895992
Short name T768
Test name
Test status
Simulation time 330465184 ps
CPU time 7.61 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 246992 kb
Host smart-d651e902-9653-48e1-b8f4-ec7d1157eb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487895992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2487895992
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.4232525985
Short name T472
Test name
Test status
Simulation time 712774734 ps
CPU time 6.35 seconds
Started Mar 19 03:19:43 PM PDT 24
Finished Mar 19 03:19:50 PM PDT 24
Peak memory 245784 kb
Host smart-48bb4712-472e-4204-a447-be5a2d4dcb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232525985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4232525985
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2418686849
Short name T513
Test name
Test status
Simulation time 2716431892 ps
CPU time 35.56 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:34 PM PDT 24
Peak memory 226172 kb
Host smart-eb466203-365d-4c71-a46a-178bec4e8c8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418686849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2418686849
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3148529448
Short name T423
Test name
Test status
Simulation time 5293431963 ps
CPU time 47.31 seconds
Started Mar 19 03:16:28 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 226180 kb
Host smart-bb466729-1888-420f-8eb4-7aed139c7594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148529448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3148529448
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2230039970
Short name T176
Test name
Test status
Simulation time 66192713035 ps
CPU time 740.33 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:28:57 PM PDT 24
Peak memory 431420 kb
Host smart-a4b4595c-9fa4-4220-ac02-099f6446a02b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2230039970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2230039970
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3321368547
Short name T549
Test name
Test status
Simulation time 11949358 ps
CPU time 0.99 seconds
Started Mar 19 03:19:45 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 211548 kb
Host smart-b9cf2452-9f4c-4b40-9a75-31d912331932
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321368547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3321368547
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3760598829
Short name T766
Test name
Test status
Simulation time 13648316 ps
CPU time 0.87 seconds
Started Mar 19 03:16:26 PM PDT 24
Finished Mar 19 03:16:27 PM PDT 24
Peak memory 211580 kb
Host smart-6e791dd4-5870-44ff-8ffb-0353a70fac07
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760598829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3760598829
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1841923717
Short name T412
Test name
Test status
Simulation time 48579746 ps
CPU time 0.85 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:19:59 PM PDT 24
Peak memory 209468 kb
Host smart-fffbceb4-2de2-4e1a-9249-e15dca58af60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841923717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1841923717
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3117951181
Short name T1482
Test name
Test status
Simulation time 27834910 ps
CPU time 0.84 seconds
Started Mar 19 03:16:36 PM PDT 24
Finished Mar 19 03:16:37 PM PDT 24
Peak memory 209528 kb
Host smart-80e56c5c-9db3-4853-a42d-b45e97aafbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117951181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3117951181
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1871384228
Short name T705
Test name
Test status
Simulation time 813691758 ps
CPU time 7.26 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:45 PM PDT 24
Peak memory 226080 kb
Host smart-0ad30093-9d21-40ed-a399-0eaa4dac1e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871384228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1871384228
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3312754294
Short name T1620
Test name
Test status
Simulation time 544742393 ps
CPU time 12.26 seconds
Started Mar 19 03:19:54 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 217876 kb
Host smart-b268d4c3-3d9a-44a3-94d8-35e6d685865d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312754294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3312754294
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.406985645
Short name T677
Test name
Test status
Simulation time 933584554 ps
CPU time 12.78 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:48 PM PDT 24
Peak memory 209492 kb
Host smart-0eec8c16-cd38-4338-83e7-aa6175f4169a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406985645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.406985645
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.851881396
Short name T907
Test name
Test status
Simulation time 453574848 ps
CPU time 11.42 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:09 PM PDT 24
Peak memory 209480 kb
Host smart-6e58bf47-07ff-46d0-bdc0-6ba90fdf4306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851881396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.851881396
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1075355803
Short name T887
Test name
Test status
Simulation time 2053521734 ps
CPU time 35.13 seconds
Started Mar 19 03:16:38 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 217940 kb
Host smart-3190e96b-8591-4bcf-92f8-74a2ea5cc495
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075355803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1075355803
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.32651650
Short name T1513
Test name
Test status
Simulation time 1825909908 ps
CPU time 26.96 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 217936 kb
Host smart-d012c5cd-fe92-431b-8e97-aad3865b1f99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_err
ors.32651650
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.236233967
Short name T1390
Test name
Test status
Simulation time 216128271 ps
CPU time 4.4 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:03 PM PDT 24
Peak memory 217996 kb
Host smart-b9dd57bb-6e2d-4d32-b603-fbfae51f4619
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236233967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.236233967
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2459022536
Short name T427
Test name
Test status
Simulation time 1065742824 ps
CPU time 11.27 seconds
Started Mar 19 03:16:36 PM PDT 24
Finished Mar 19 03:16:48 PM PDT 24
Peak memory 218004 kb
Host smart-694acb6c-0638-4ecb-adfa-8096886d1ec3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459022536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2459022536
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2229408167
Short name T298
Test name
Test status
Simulation time 885919240 ps
CPU time 6.52 seconds
Started Mar 19 03:20:04 PM PDT 24
Finished Mar 19 03:20:11 PM PDT 24
Peak memory 213560 kb
Host smart-c941b0ad-ae63-4c96-a7ac-e23d3dece179
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229408167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2229408167
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3284556841
Short name T984
Test name
Test status
Simulation time 337815344 ps
CPU time 1.75 seconds
Started Mar 19 03:16:36 PM PDT 24
Finished Mar 19 03:16:37 PM PDT 24
Peak memory 212808 kb
Host smart-08fc5e6d-48d9-40ad-b01a-0fb60f496f72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284556841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3284556841
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3275373482
Short name T1083
Test name
Test status
Simulation time 1511857555 ps
CPU time 49.82 seconds
Started Mar 19 03:16:34 PM PDT 24
Finished Mar 19 03:17:24 PM PDT 24
Peak memory 267952 kb
Host smart-54108b2f-21c8-4b5e-98ff-2cc0c6cc650e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275373482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3275373482
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.474819520
Short name T1020
Test name
Test status
Simulation time 1576067683 ps
CPU time 35.82 seconds
Started Mar 19 03:20:00 PM PDT 24
Finished Mar 19 03:20:36 PM PDT 24
Peak memory 269604 kb
Host smart-d77b8abb-8005-448f-9d71-0a8ccb0d6700
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474819520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.474819520
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1386114805
Short name T1397
Test name
Test status
Simulation time 227034596 ps
CPU time 8.42 seconds
Started Mar 19 03:19:55 PM PDT 24
Finished Mar 19 03:20:04 PM PDT 24
Peak memory 246224 kb
Host smart-30b251be-134e-4f09-9475-b1d50d4b3a06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386114805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1386114805
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2378914996
Short name T653
Test name
Test status
Simulation time 660515523 ps
CPU time 7.52 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 226468 kb
Host smart-0dc806a3-572d-49ee-a476-beb990517be2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378914996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2378914996
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1302863588
Short name T1096
Test name
Test status
Simulation time 67574713 ps
CPU time 2.81 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:19:59 PM PDT 24
Peak memory 222016 kb
Host smart-779c85db-a047-4654-90ea-85cba539ccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302863588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1302863588
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2506221272
Short name T1645
Test name
Test status
Simulation time 236350590 ps
CPU time 3.6 seconds
Started Mar 19 03:16:38 PM PDT 24
Finished Mar 19 03:16:42 PM PDT 24
Peak memory 218020 kb
Host smart-54896a98-49b3-49ab-9a45-d91e4fb0c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506221272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2506221272
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1353866073
Short name T1070
Test name
Test status
Simulation time 288764417 ps
CPU time 12.69 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:20:09 PM PDT 24
Peak memory 218956 kb
Host smart-088700a9-a7e6-4ecb-99e5-6a9ef8ee613e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353866073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1353866073
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3381423359
Short name T784
Test name
Test status
Simulation time 283133063 ps
CPU time 14.23 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:51 PM PDT 24
Peak memory 226044 kb
Host smart-b99f761b-5ede-4c82-a369-d8b2d4408a54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381423359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3381423359
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2170944688
Short name T1677
Test name
Test status
Simulation time 818946655 ps
CPU time 16.71 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:54 PM PDT 24
Peak memory 217900 kb
Host smart-fe9aae53-5b83-452d-97f2-ab5c8fff9258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170944688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2170944688
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.429073406
Short name T1529
Test name
Test status
Simulation time 436332825 ps
CPU time 11.89 seconds
Started Mar 19 03:20:03 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 217896 kb
Host smart-7d7bd268-b3cf-480b-9362-195446a4438f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429073406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.429073406
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2981322296
Short name T329
Test name
Test status
Simulation time 294790452 ps
CPU time 7.92 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 217892 kb
Host smart-030bb17d-b641-4dcb-88ca-ebaf0ded0503
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981322296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2981322296
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.494527482
Short name T1091
Test name
Test status
Simulation time 611462750 ps
CPU time 9.66 seconds
Started Mar 19 03:16:39 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 217836 kb
Host smart-72392513-d479-41e9-8dc9-632debd36b3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494527482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.494527482
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1522998383
Short name T849
Test name
Test status
Simulation time 978107415 ps
CPU time 10.25 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:47 PM PDT 24
Peak memory 225172 kb
Host smart-5ad7969a-701b-41ac-8df4-51ce3e7cbec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522998383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1522998383
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3139537434
Short name T45
Test name
Test status
Simulation time 4461382035 ps
CPU time 8.49 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:20:04 PM PDT 24
Peak memory 225056 kb
Host smart-2d484453-0353-4c54-93a4-a0fc6f9858f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139537434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3139537434
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2644420296
Short name T468
Test name
Test status
Simulation time 123744692 ps
CPU time 3.85 seconds
Started Mar 19 03:20:03 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 217716 kb
Host smart-d2bca240-6c68-48dd-8444-d77effb2dd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644420296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2644420296
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.616610153
Short name T72
Test name
Test status
Simulation time 27638681 ps
CPU time 1.88 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:39 PM PDT 24
Peak memory 213516 kb
Host smart-c53be98e-1654-49a5-a30d-cdc5fd6971bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616610153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.616610153
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1377486879
Short name T357
Test name
Test status
Simulation time 1424479194 ps
CPU time 33.92 seconds
Started Mar 19 03:20:06 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 250940 kb
Host smart-6cf35ae3-277c-4af3-8b40-afdd8eead54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377486879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1377486879
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3683783969
Short name T1211
Test name
Test status
Simulation time 287026619 ps
CPU time 29.75 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 250964 kb
Host smart-34c7c4e9-f0f5-4314-9a3c-cab301b41115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683783969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3683783969
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1622501840
Short name T642
Test name
Test status
Simulation time 86331250 ps
CPU time 8.17 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 246944 kb
Host smart-d2b29618-b35b-4fe3-8410-19eda8f22821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622501840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1622501840
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.73084192
Short name T1491
Test name
Test status
Simulation time 308403772 ps
CPU time 3.29 seconds
Started Mar 19 03:19:57 PM PDT 24
Finished Mar 19 03:20:01 PM PDT 24
Peak memory 226340 kb
Host smart-b9b89afe-7beb-4d04-b470-ab75b6633150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73084192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.73084192
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1712150899
Short name T685
Test name
Test status
Simulation time 1270471433 ps
CPU time 53.77 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:53 PM PDT 24
Peak memory 250872 kb
Host smart-9bb955cd-de97-46ba-a26e-aa6913b28084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712150899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1712150899
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4242681588
Short name T890
Test name
Test status
Simulation time 15382639416 ps
CPU time 250.38 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:20:47 PM PDT 24
Peak memory 275552 kb
Host smart-97aa8265-c49b-4f00-b255-dee3ca3ba9f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242681588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4242681588
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.480960734
Short name T169
Test name
Test status
Simulation time 15352455685 ps
CPU time 293.9 seconds
Started Mar 19 03:20:04 PM PDT 24
Finished Mar 19 03:24:58 PM PDT 24
Peak memory 324936 kb
Host smart-a2a9fbb5-62f8-4319-a55e-12966dbdd1e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=480960734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.480960734
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3284350259
Short name T1040
Test name
Test status
Simulation time 36444483 ps
CPU time 0.82 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:00 PM PDT 24
Peak memory 211508 kb
Host smart-e31eeab8-a880-4410-a21f-0876f2652a23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284350259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3284350259
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4190176472
Short name T279
Test name
Test status
Simulation time 20951349 ps
CPU time 0.9 seconds
Started Mar 19 03:16:41 PM PDT 24
Finished Mar 19 03:16:42 PM PDT 24
Peak memory 211648 kb
Host smart-87102767-3099-4fec-bb20-b6af6f243d71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190176472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4190176472
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1916371169
Short name T711
Test name
Test status
Simulation time 50862055 ps
CPU time 0.85 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:19 PM PDT 24
Peak memory 209536 kb
Host smart-f0a91e63-597c-4d1c-9d4d-8fa14c0352e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916371169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1916371169
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4095110354
Short name T411
Test name
Test status
Simulation time 53641132 ps
CPU time 1.34 seconds
Started Mar 19 03:15:29 PM PDT 24
Finished Mar 19 03:15:31 PM PDT 24
Peak memory 209592 kb
Host smart-9b8ac223-a6eb-4505-8d44-bb1d74a1088e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095110354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4095110354
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.291699193
Short name T806
Test name
Test status
Simulation time 49545388 ps
CPU time 0.85 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:18:59 PM PDT 24
Peak memory 209384 kb
Host smart-d87d64dc-ab92-4abc-8c6d-db437f827295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291699193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.291699193
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1108776219
Short name T400
Test name
Test status
Simulation time 4816131242 ps
CPU time 11.86 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:19:15 PM PDT 24
Peak memory 218368 kb
Host smart-a53140cc-adbd-4097-aa18-90a4b5dfb563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108776219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1108776219
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2604912451
Short name T791
Test name
Test status
Simulation time 827180024 ps
CPU time 8.86 seconds
Started Mar 19 03:15:30 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 217960 kb
Host smart-d2222138-55a1-4e49-bc10-a5f78899c3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604912451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2604912451
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1726060546
Short name T735
Test name
Test status
Simulation time 616288648 ps
CPU time 2.48 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 209452 kb
Host smart-958ef201-0036-4e18-bca6-c86439ff506e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726060546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1726060546
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1842107640
Short name T1089
Test name
Test status
Simulation time 734754458 ps
CPU time 5.19 seconds
Started Mar 19 03:19:03 PM PDT 24
Finished Mar 19 03:19:09 PM PDT 24
Peak memory 209456 kb
Host smart-860674e4-32b2-4dd0-a667-1df58aae172b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842107640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1842107640
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1005859821
Short name T1403
Test name
Test status
Simulation time 2264195400 ps
CPU time 65.65 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:20:08 PM PDT 24
Peak memory 219976 kb
Host smart-94c4b00f-ec44-4bd2-b0fc-47eaca5b0eff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005859821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1005859821
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.242946418
Short name T1590
Test name
Test status
Simulation time 3300901279 ps
CPU time 94.9 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 220084 kb
Host smart-53dd87fd-d040-478a-9d04-48a552c441f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242946418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.242946418
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3053783164
Short name T1617
Test name
Test status
Simulation time 597257169 ps
CPU time 6.34 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:15:39 PM PDT 24
Peak memory 217592 kb
Host smart-3025b2cd-4c81-4da2-8654-7eb68f514c86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053783164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
053783164
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3614059719
Short name T229
Test name
Test status
Simulation time 255666447 ps
CPU time 1.87 seconds
Started Mar 19 03:19:11 PM PDT 24
Finished Mar 19 03:19:13 PM PDT 24
Peak memory 217008 kb
Host smart-d793b031-ba8a-49ff-8dfe-2e21cf0448dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614059719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
614059719
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.483620353
Short name T417
Test name
Test status
Simulation time 204336707 ps
CPU time 3.89 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:39 PM PDT 24
Peak memory 217996 kb
Host smart-768a9eae-4b11-47f8-ba55-e890ea46e8d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483620353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.483620353
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.81341868
Short name T769
Test name
Test status
Simulation time 312392799 ps
CPU time 6.41 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 217956 kb
Host smart-ef85dc2d-31eb-4213-8a0f-a37697966e89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81341868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_p
rog_failure.81341868
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2332943765
Short name T870
Test name
Test status
Simulation time 951621637 ps
CPU time 27.84 seconds
Started Mar 19 03:19:04 PM PDT 24
Finished Mar 19 03:19:32 PM PDT 24
Peak memory 213272 kb
Host smart-d3ef7e99-8c66-48d0-aade-4a4c079acb60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332943765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2332943765
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.932212654
Short name T1665
Test name
Test status
Simulation time 1337187469 ps
CPU time 19.74 seconds
Started Mar 19 03:15:35 PM PDT 24
Finished Mar 19 03:15:55 PM PDT 24
Peak memory 213276 kb
Host smart-d8d02854-f85a-42d1-8092-42797fd841dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932212654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.932212654
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2878887325
Short name T108
Test name
Test status
Simulation time 192430567 ps
CPU time 3.32 seconds
Started Mar 19 03:19:14 PM PDT 24
Finished Mar 19 03:19:17 PM PDT 24
Peak memory 213044 kb
Host smart-5c9a5a64-bf08-4275-b861-b73e5e8cd28a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878887325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2878887325
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.821846460
Short name T664
Test name
Test status
Simulation time 704178616 ps
CPU time 3.22 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:34 PM PDT 24
Peak memory 213072 kb
Host smart-b6d43e8c-ac3b-49c0-9188-fff3f40fc419
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821846460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.821846460
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1045809873
Short name T1264
Test name
Test status
Simulation time 11778463623 ps
CPU time 67.43 seconds
Started Mar 19 03:18:57 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 272076 kb
Host smart-bfedd51b-c513-46f1-892d-66968bdca7e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045809873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1045809873
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.944852687
Short name T1136
Test name
Test status
Simulation time 3594860888 ps
CPU time 28.9 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:16:00 PM PDT 24
Peak memory 251148 kb
Host smart-41f61e1b-b301-4f2c-a4c1-b58611da26fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944852687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.944852687
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2331357345
Short name T1466
Test name
Test status
Simulation time 961363107 ps
CPU time 20.07 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:19 PM PDT 24
Peak memory 250152 kb
Host smart-5d06382f-2190-4fe0-a953-d60752f5bfa0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331357345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2331357345
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2440568976
Short name T1652
Test name
Test status
Simulation time 6979472395 ps
CPU time 12.93 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:44 PM PDT 24
Peak memory 242964 kb
Host smart-ca3cac5c-5081-4846-a2a1-be34d35e9cd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440568976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2440568976
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3256000167
Short name T940
Test name
Test status
Simulation time 58638068 ps
CPU time 3.3 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 221880 kb
Host smart-3606af82-9ce4-419e-8470-ed54fa3a87ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256000167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3256000167
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.586764280
Short name T486
Test name
Test status
Simulation time 218352070 ps
CPU time 2.69 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 221680 kb
Host smart-e12de225-6f72-4202-a60b-cd568847adb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586764280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.586764280
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1766046178
Short name T1046
Test name
Test status
Simulation time 441403035 ps
CPU time 29.65 seconds
Started Mar 19 03:15:30 PM PDT 24
Finished Mar 19 03:16:00 PM PDT 24
Peak memory 217708 kb
Host smart-61900633-fb3c-4f57-b275-74c6103bde1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766046178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1766046178
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.4132940883
Short name T548
Test name
Test status
Simulation time 194149827 ps
CPU time 13.94 seconds
Started Mar 19 03:19:03 PM PDT 24
Finished Mar 19 03:19:17 PM PDT 24
Peak memory 214244 kb
Host smart-22110598-0ee2-413e-bbb4-8cc6f6bf17c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132940883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.4132940883
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3136327920
Short name T49
Test name
Test status
Simulation time 265973362 ps
CPU time 39.97 seconds
Started Mar 19 03:19:06 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 282404 kb
Host smart-d9e8ea25-3a0f-4c53-89aa-320cb3502d17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136327920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3136327920
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3428925085
Short name T85
Test name
Test status
Simulation time 1878196399 ps
CPU time 20.92 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:56 PM PDT 24
Peak memory 269256 kb
Host smart-642caf80-8d00-4503-bfba-12f3097ad7b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428925085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3428925085
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1882253870
Short name T1547
Test name
Test status
Simulation time 1247092104 ps
CPU time 9.94 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 217928 kb
Host smart-49e8c8af-8e57-4540-b74e-11c8b05575ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882253870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1882253870
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2725765649
Short name T1232
Test name
Test status
Simulation time 1329015704 ps
CPU time 12.1 seconds
Started Mar 19 03:15:36 PM PDT 24
Finished Mar 19 03:15:48 PM PDT 24
Peak memory 218920 kb
Host smart-fc127576-9763-4427-a257-c1cce49921cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725765649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2725765649
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2637814437
Short name T991
Test name
Test status
Simulation time 1040288104 ps
CPU time 8.72 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 217888 kb
Host smart-5cd992d0-ef41-4b99-b463-c1f9b2c64fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637814437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2637814437
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3153957752
Short name T981
Test name
Test status
Simulation time 638084410 ps
CPU time 8.58 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 217856 kb
Host smart-3dbd3ef8-d2aa-4d5f-b19d-8dc8cb726ca0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153957752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3153957752
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1318194605
Short name T1228
Test name
Test status
Simulation time 2027044330 ps
CPU time 8.43 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 217880 kb
Host smart-148b2ae0-cbd8-4042-aac0-388bcaa98b9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318194605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
318194605
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2993326966
Short name T1109
Test name
Test status
Simulation time 364570370 ps
CPU time 10.41 seconds
Started Mar 19 03:19:03 PM PDT 24
Finished Mar 19 03:19:14 PM PDT 24
Peak memory 217900 kb
Host smart-e74eedeb-9cfb-49cd-a0fc-7d206343035a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993326966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
993326966
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2320743628
Short name T1528
Test name
Test status
Simulation time 960055226 ps
CPU time 6.74 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:38 PM PDT 24
Peak memory 224080 kb
Host smart-6a6ec289-3377-4cb7-a45b-d4995eedd537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320743628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2320743628
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4029484336
Short name T1334
Test name
Test status
Simulation time 121713902 ps
CPU time 3.91 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 214596 kb
Host smart-c1f57591-f75a-4b3d-88a3-13ee219ed44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029484336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4029484336
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.487711792
Short name T1624
Test name
Test status
Simulation time 300296458 ps
CPU time 2.96 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:03 PM PDT 24
Peak memory 217668 kb
Host smart-3becc2a5-290b-48ea-ab33-6b7870c3c456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487711792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.487711792
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3061730293
Short name T1408
Test name
Test status
Simulation time 1360396774 ps
CPU time 29.36 seconds
Started Mar 19 03:15:38 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 250432 kb
Host smart-76fcac76-35a0-41f6-87a5-059b2a274c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061730293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3061730293
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.876423021
Short name T285
Test name
Test status
Simulation time 404060025 ps
CPU time 29.56 seconds
Started Mar 19 03:19:05 PM PDT 24
Finished Mar 19 03:19:35 PM PDT 24
Peak memory 250744 kb
Host smart-8b909b87-f54a-4169-a91e-af6184a8e9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876423021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.876423021
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2765855906
Short name T1000
Test name
Test status
Simulation time 88593212 ps
CPU time 6.86 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:05 PM PDT 24
Peak memory 250340 kb
Host smart-f10e472e-121c-4fe5-bff8-833738bef111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765855906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2765855906
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3256801713
Short name T553
Test name
Test status
Simulation time 62985097 ps
CPU time 8.72 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 250944 kb
Host smart-0cd4140a-8c03-42bd-a707-c0dc4957ff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256801713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3256801713
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1917018928
Short name T518
Test name
Test status
Simulation time 17211707063 ps
CPU time 78.76 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:20:19 PM PDT 24
Peak memory 278192 kb
Host smart-0518ddbc-4440-4e20-a1eb-aca558d83d27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917018928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1917018928
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2464381634
Short name T657
Test name
Test status
Simulation time 1925116150 ps
CPU time 16.2 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:50 PM PDT 24
Peak memory 217848 kb
Host smart-fbd10c04-b10a-462d-86a4-28d3a342570f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464381634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2464381634
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3735640301
Short name T175
Test name
Test status
Simulation time 70038351720 ps
CPU time 673.75 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:26:48 PM PDT 24
Peak memory 373092 kb
Host smart-74f02335-7ee4-4cf9-9981-2c898fbdecd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3735640301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3735640301
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3077418353
Short name T703
Test name
Test status
Simulation time 14171618 ps
CPU time 1.09 seconds
Started Mar 19 03:19:16 PM PDT 24
Finished Mar 19 03:19:17 PM PDT 24
Peak memory 211616 kb
Host smart-86d67c51-7a3b-4693-9c2b-34e956ed7ff9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077418353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3077418353
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.598934623
Short name T1510
Test name
Test status
Simulation time 12811140 ps
CPU time 0.85 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:36 PM PDT 24
Peak memory 211636 kb
Host smart-95d0dacb-f190-441c-9d51-9850849f59c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598934623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.598934623
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2010899310
Short name T1438
Test name
Test status
Simulation time 22010243 ps
CPU time 0.96 seconds
Started Mar 19 03:16:34 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 209576 kb
Host smart-e1745c12-1e18-48a7-a5e0-4135a39c8b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010899310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2010899310
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.539922891
Short name T1243
Test name
Test status
Simulation time 62702036 ps
CPU time 1.07 seconds
Started Mar 19 03:20:04 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 209696 kb
Host smart-883a5399-54ad-4bc6-9d44-7e5d3f124736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539922891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.539922891
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3772273704
Short name T611
Test name
Test status
Simulation time 679684559 ps
CPU time 16.36 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:54 PM PDT 24
Peak memory 226052 kb
Host smart-78f8cfa1-24bd-4137-b325-2fa2e012fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772273704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3772273704
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.744313744
Short name T690
Test name
Test status
Simulation time 539109973 ps
CPU time 12.29 seconds
Started Mar 19 03:20:01 PM PDT 24
Finished Mar 19 03:20:14 PM PDT 24
Peak memory 217732 kb
Host smart-863b4c6c-13b3-4ffe-ad6f-e5d36460ff5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744313744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.744313744
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1022184732
Short name T1580
Test name
Test status
Simulation time 515785048 ps
CPU time 3.58 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:40 PM PDT 24
Peak memory 216732 kb
Host smart-5a2c9b29-9758-4c42-8f41-ba801320cf67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022184732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1022184732
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4170275357
Short name T1111
Test name
Test status
Simulation time 371651363 ps
CPU time 2.44 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:01 PM PDT 24
Peak memory 216804 kb
Host smart-8f80fb4f-7995-44e7-a034-f1c4808989fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170275357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4170275357
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1281672926
Short name T1558
Test name
Test status
Simulation time 58048382 ps
CPU time 3.26 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:02 PM PDT 24
Peak memory 221876 kb
Host smart-2adbe432-2f43-435b-97c9-be83e530de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281672926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1281672926
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2177851893
Short name T743
Test name
Test status
Simulation time 327843588 ps
CPU time 2.86 seconds
Started Mar 19 03:16:33 PM PDT 24
Finished Mar 19 03:16:36 PM PDT 24
Peak memory 218000 kb
Host smart-fb701fd1-e8aa-4a81-8a0a-64dff68ad41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177851893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2177851893
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1375170304
Short name T951
Test name
Test status
Simulation time 314598323 ps
CPU time 15.36 seconds
Started Mar 19 03:19:55 PM PDT 24
Finished Mar 19 03:20:10 PM PDT 24
Peak memory 218908 kb
Host smart-987d8388-5e04-462d-ac47-623e7e67f74b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375170304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1375170304
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2823428223
Short name T1634
Test name
Test status
Simulation time 1513221769 ps
CPU time 11.76 seconds
Started Mar 19 03:16:36 PM PDT 24
Finished Mar 19 03:16:48 PM PDT 24
Peak memory 218060 kb
Host smart-4a3acc03-6bc0-4673-8c4a-acfdc83dfd60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823428223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2823428223
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2266462493
Short name T575
Test name
Test status
Simulation time 1259225826 ps
CPU time 13.25 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:13 PM PDT 24
Peak memory 217956 kb
Host smart-fe28ed12-dd6a-4f85-9e8d-3da6f319175e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266462493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2266462493
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3137470632
Short name T762
Test name
Test status
Simulation time 1090953547 ps
CPU time 7.57 seconds
Started Mar 19 03:16:33 PM PDT 24
Finished Mar 19 03:16:41 PM PDT 24
Peak memory 217880 kb
Host smart-5af7ad36-da83-48bd-a723-bad5be057668
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137470632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3137470632
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1593723271
Short name T509
Test name
Test status
Simulation time 856789187 ps
CPU time 10.35 seconds
Started Mar 19 03:19:55 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 217936 kb
Host smart-cf9b1e76-b9e2-449c-907f-fc94034d9dd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593723271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1593723271
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.510136258
Short name T935
Test name
Test status
Simulation time 665020681 ps
CPU time 8.27 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:46 PM PDT 24
Peak memory 217844 kb
Host smart-47ca2e01-1f5e-460b-94b8-daf1d689edcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510136258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.510136258
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.294860570
Short name T1104
Test name
Test status
Simulation time 716839268 ps
CPU time 9.56 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:47 PM PDT 24
Peak memory 225148 kb
Host smart-51b502ee-2c5c-42fc-a72c-46c73e991186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294860570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.294860570
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3897595219
Short name T715
Test name
Test status
Simulation time 1202846681 ps
CPU time 7.78 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 224464 kb
Host smart-d423cdbd-7bfa-475b-ba5f-206f1e1eb147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897595219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3897595219
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1033123034
Short name T590
Test name
Test status
Simulation time 197385208 ps
CPU time 4.76 seconds
Started Mar 19 03:20:00 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 214612 kb
Host smart-dbe7df0f-fc23-4c72-981a-9fd2da774e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033123034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1033123034
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3814598922
Short name T462
Test name
Test status
Simulation time 144305319 ps
CPU time 2.96 seconds
Started Mar 19 03:16:34 PM PDT 24
Finished Mar 19 03:16:37 PM PDT 24
Peak memory 214148 kb
Host smart-48c6d9f5-863d-4ffb-b76a-78d43cfd4fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814598922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3814598922
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2593159933
Short name T992
Test name
Test status
Simulation time 1191843741 ps
CPU time 24.04 seconds
Started Mar 19 03:16:41 PM PDT 24
Finished Mar 19 03:17:05 PM PDT 24
Peak memory 251020 kb
Host smart-15ec1eba-d0d7-4ff2-85c3-d9c7a1fa12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593159933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2593159933
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.4170679421
Short name T695
Test name
Test status
Simulation time 996624380 ps
CPU time 30.31 seconds
Started Mar 19 03:19:57 PM PDT 24
Finished Mar 19 03:20:28 PM PDT 24
Peak memory 245444 kb
Host smart-285c7433-a862-4f7f-9de1-45238f48c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170679421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.4170679421
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2364157674
Short name T821
Test name
Test status
Simulation time 133484127 ps
CPU time 8.68 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 246084 kb
Host smart-c65c2708-e05b-49c2-b03f-f0f5e67d26a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364157674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2364157674
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4228723790
Short name T1093
Test name
Test status
Simulation time 91312843 ps
CPU time 4.43 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:20:00 PM PDT 24
Peak memory 222384 kb
Host smart-7e3582e7-967f-4966-b114-d30f7b3be776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228723790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4228723790
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1907512713
Short name T114
Test name
Test status
Simulation time 17953579693 ps
CPU time 167.26 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:22:46 PM PDT 24
Peak memory 273340 kb
Host smart-494a713c-ff24-48a1-b80e-e44a54a4f380
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907512713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1907512713
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2063453072
Short name T322
Test name
Test status
Simulation time 23696822385 ps
CPU time 143.53 seconds
Started Mar 19 03:16:36 PM PDT 24
Finished Mar 19 03:18:59 PM PDT 24
Peak memory 277032 kb
Host smart-e204a924-7e5e-4509-ad18-6bbcd9c6a9af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063453072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2063453072
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2228655263
Short name T23
Test name
Test status
Simulation time 45295141 ps
CPU time 0.93 seconds
Started Mar 19 03:16:38 PM PDT 24
Finished Mar 19 03:16:39 PM PDT 24
Peak memory 212656 kb
Host smart-e31f4057-6337-4a02-a8e0-dc51e6555a80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228655263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2228655263
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2807072775
Short name T1586
Test name
Test status
Simulation time 13299761 ps
CPU time 0.97 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:00 PM PDT 24
Peak memory 211592 kb
Host smart-7baa6b45-f4bf-4d09-9b16-e983d357bed8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807072775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2807072775
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1291810458
Short name T1154
Test name
Test status
Simulation time 80411432 ps
CPU time 1.01 seconds
Started Mar 19 03:20:09 PM PDT 24
Finished Mar 19 03:20:10 PM PDT 24
Peak memory 209600 kb
Host smart-a8c27247-6b9a-4498-ae89-2978c092e096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291810458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1291810458
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2728394527
Short name T646
Test name
Test status
Simulation time 34851140 ps
CPU time 0.9 seconds
Started Mar 19 03:16:46 PM PDT 24
Finished Mar 19 03:16:47 PM PDT 24
Peak memory 209596 kb
Host smart-03ea7ef9-0a0b-49ea-9524-a4a0e6eee4c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728394527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2728394527
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1801652480
Short name T1310
Test name
Test status
Simulation time 277259760 ps
CPU time 10.8 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:46 PM PDT 24
Peak memory 217956 kb
Host smart-8cae7ea1-710d-45ce-bdc7-aac41516734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801652480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1801652480
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4076560912
Short name T510
Test name
Test status
Simulation time 451002910 ps
CPU time 11.7 seconds
Started Mar 19 03:19:55 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 217932 kb
Host smart-77bb6002-c70b-4992-83f3-5ffa753765a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076560912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4076560912
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1468047832
Short name T1479
Test name
Test status
Simulation time 92081003 ps
CPU time 1.88 seconds
Started Mar 19 03:19:57 PM PDT 24
Finished Mar 19 03:19:59 PM PDT 24
Peak memory 209488 kb
Host smart-475f46ae-2914-4542-8fe9-4aed5a93d4d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468047832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1468047832
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4226882276
Short name T1336
Test name
Test status
Simulation time 149730511 ps
CPU time 2.7 seconds
Started Mar 19 03:16:41 PM PDT 24
Finished Mar 19 03:16:44 PM PDT 24
Peak memory 209496 kb
Host smart-5be136af-f862-4246-b133-1e117d3d6580
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226882276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4226882276
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2167075573
Short name T581
Test name
Test status
Simulation time 30141997 ps
CPU time 1.44 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:01 PM PDT 24
Peak memory 221152 kb
Host smart-e1af920b-154d-4640-9a0d-888079fe86c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167075573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2167075573
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4026728519
Short name T1056
Test name
Test status
Simulation time 343054160 ps
CPU time 2.44 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:37 PM PDT 24
Peak memory 221816 kb
Host smart-b28ce743-e221-420e-b6e3-e406a87f29d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026728519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4026728519
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1052984778
Short name T1412
Test name
Test status
Simulation time 339863603 ps
CPU time 10.54 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:09 PM PDT 24
Peak memory 226068 kb
Host smart-89b5a70b-0178-48d7-9ecb-75d76a831968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052984778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1052984778
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.746818118
Short name T452
Test name
Test status
Simulation time 1310283422 ps
CPU time 17.81 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:53 PM PDT 24
Peak memory 218852 kb
Host smart-8923e9d5-618b-41ef-86b6-01ddd34a266f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746818118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.746818118
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1971401631
Short name T765
Test name
Test status
Simulation time 671509950 ps
CPU time 11.11 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:16:46 PM PDT 24
Peak memory 217852 kb
Host smart-79548af2-d23a-4b15-a29f-43e166824371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971401631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1971401631
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.861339563
Short name T595
Test name
Test status
Simulation time 240434062 ps
CPU time 9.67 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:20:06 PM PDT 24
Peak memory 217884 kb
Host smart-e97c3b13-2029-4b12-8f5b-f5fb65f6c11e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861339563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.861339563
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2823792081
Short name T823
Test name
Test status
Simulation time 256133313 ps
CPU time 5.83 seconds
Started Mar 19 03:16:36 PM PDT 24
Finished Mar 19 03:16:42 PM PDT 24
Peak memory 217900 kb
Host smart-77a201e4-ae0d-4a95-8ba3-783dcaa4185d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823792081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2823792081
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.872086705
Short name T605
Test name
Test status
Simulation time 1159773335 ps
CPU time 11.32 seconds
Started Mar 19 03:20:02 PM PDT 24
Finished Mar 19 03:20:13 PM PDT 24
Peak memory 217864 kb
Host smart-3ead8119-6ece-404e-9e61-7d98be83501c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872086705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.872086705
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.4127895461
Short name T1640
Test name
Test status
Simulation time 656096597 ps
CPU time 8.32 seconds
Started Mar 19 03:19:54 PM PDT 24
Finished Mar 19 03:20:03 PM PDT 24
Peak memory 224632 kb
Host smart-8c838178-7714-4d13-bce2-0ceef961b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127895461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.4127895461
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1943313158
Short name T355
Test name
Test status
Simulation time 690040724 ps
CPU time 5.34 seconds
Started Mar 19 03:19:58 PM PDT 24
Finished Mar 19 03:20:04 PM PDT 24
Peak memory 223112 kb
Host smart-0d1f6d88-b02a-44c0-b646-9dcaa5f8850e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943313158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1943313158
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4064166529
Short name T529
Test name
Test status
Simulation time 534634427 ps
CPU time 2.65 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:40 PM PDT 24
Peak memory 217800 kb
Host smart-3eace80e-b0d9-4dd0-84ee-3c66bfac326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064166529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4064166529
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1240002516
Short name T1364
Test name
Test status
Simulation time 1488403365 ps
CPU time 27.35 seconds
Started Mar 19 03:19:59 PM PDT 24
Finished Mar 19 03:20:27 PM PDT 24
Peak memory 249672 kb
Host smart-bbff2d2a-60e9-4049-9ba3-c5898555e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240002516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1240002516
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1960051920
Short name T584
Test name
Test status
Simulation time 400355356 ps
CPU time 20.78 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:58 PM PDT 24
Peak memory 246288 kb
Host smart-25f8e0b3-054f-400d-82d8-d8a9d0474d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960051920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1960051920
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.280719316
Short name T1272
Test name
Test status
Simulation time 298279358 ps
CPU time 7.08 seconds
Started Mar 19 03:16:36 PM PDT 24
Finished Mar 19 03:16:43 PM PDT 24
Peak memory 250912 kb
Host smart-07924d1b-eed5-4e0d-85d4-96ae4482c9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280719316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.280719316
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3853670519
Short name T1449
Test name
Test status
Simulation time 98095612 ps
CPU time 7.88 seconds
Started Mar 19 03:19:56 PM PDT 24
Finished Mar 19 03:20:04 PM PDT 24
Peak memory 248336 kb
Host smart-9dd5dded-da62-4c6b-9662-d408901a8f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853670519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3853670519
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1878923060
Short name T193
Test name
Test status
Simulation time 10316519299 ps
CPU time 208.64 seconds
Started Mar 19 03:16:41 PM PDT 24
Finished Mar 19 03:20:10 PM PDT 24
Peak memory 496832 kb
Host smart-ec8d70ee-6a57-406b-9401-499769f3715e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878923060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1878923060
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2448538409
Short name T716
Test name
Test status
Simulation time 13061534471 ps
CPU time 340.83 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:25:53 PM PDT 24
Peak memory 274560 kb
Host smart-35f0c545-8eec-46d2-aa6a-1e246c373876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448538409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2448538409
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1368225024
Short name T697
Test name
Test status
Simulation time 119099794989 ps
CPU time 670.67 seconds
Started Mar 19 03:16:35 PM PDT 24
Finished Mar 19 03:27:46 PM PDT 24
Peak memory 358588 kb
Host smart-dd26afa8-d9f2-4fc8-8875-47dc21a9a4d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1368225024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1368225024
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2490579429
Short name T1472
Test name
Test status
Simulation time 83920493 ps
CPU time 0.97 seconds
Started Mar 19 03:20:05 PM PDT 24
Finished Mar 19 03:20:06 PM PDT 24
Peak memory 211652 kb
Host smart-cccf8fb5-2069-4f75-af13-d3a3238b4f87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490579429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2490579429
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.932257159
Short name T652
Test name
Test status
Simulation time 14922690 ps
CPU time 1.14 seconds
Started Mar 19 03:16:37 PM PDT 24
Finished Mar 19 03:16:38 PM PDT 24
Peak memory 212692 kb
Host smart-53a74486-5af9-44f0-aa23-e758277a26a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932257159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.932257159
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.154920318
Short name T748
Test name
Test status
Simulation time 34815933 ps
CPU time 1.17 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:14 PM PDT 24
Peak memory 209584 kb
Host smart-957b25c8-1686-4db9-95e3-39555df7dce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154920318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.154920318
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.549882409
Short name T1504
Test name
Test status
Simulation time 17593255 ps
CPU time 1.06 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 209588 kb
Host smart-0bda5f31-28bf-4f78-8ae0-f7d48cefc3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549882409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.549882409
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1192267034
Short name T1388
Test name
Test status
Simulation time 618646483 ps
CPU time 11.51 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:00 PM PDT 24
Peak memory 217936 kb
Host smart-a4c7fd5f-1053-4804-af5a-df182f26b5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192267034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1192267034
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.567070843
Short name T931
Test name
Test status
Simulation time 473875811 ps
CPU time 14.23 seconds
Started Mar 19 03:20:15 PM PDT 24
Finished Mar 19 03:20:29 PM PDT 24
Peak memory 217952 kb
Host smart-fc4f7cfe-8c87-4a25-912f-408188fecb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567070843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.567070843
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.669643759
Short name T1625
Test name
Test status
Simulation time 1448795660 ps
CPU time 18.19 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 209464 kb
Host smart-ff055590-22be-4dfc-a087-0196f4a25d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669643759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.669643759
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.815277748
Short name T1257
Test name
Test status
Simulation time 302332062 ps
CPU time 8.71 seconds
Started Mar 19 03:20:19 PM PDT 24
Finished Mar 19 03:20:29 PM PDT 24
Peak memory 216964 kb
Host smart-663ef669-47a9-4a64-81b5-64ef3808744b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815277748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.815277748
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1528902627
Short name T269
Test name
Test status
Simulation time 13709308 ps
CPU time 1.44 seconds
Started Mar 19 03:16:47 PM PDT 24
Finished Mar 19 03:16:48 PM PDT 24
Peak memory 217860 kb
Host smart-14cf709b-246f-427d-94a4-13eabf53a275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528902627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1528902627
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2083385288
Short name T314
Test name
Test status
Simulation time 217767883 ps
CPU time 2.33 seconds
Started Mar 19 03:20:09 PM PDT 24
Finished Mar 19 03:20:12 PM PDT 24
Peak memory 217992 kb
Host smart-aed233e2-4e80-4bb7-9833-5da8c6cdc5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083385288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2083385288
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1618209045
Short name T1386
Test name
Test status
Simulation time 241101687 ps
CPU time 10.87 seconds
Started Mar 19 03:20:15 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 225864 kb
Host smart-38e13e22-71fd-456e-85eb-58e4d804d0a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618209045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1618209045
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2696828492
Short name T1667
Test name
Test status
Simulation time 2337154160 ps
CPU time 10.99 seconds
Started Mar 19 03:16:51 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 226108 kb
Host smart-caa0c337-9d0b-4fee-ba96-07ad9c81f518
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696828492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2696828492
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.434492031
Short name T126
Test name
Test status
Simulation time 1029858365 ps
CPU time 12.62 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 217972 kb
Host smart-6d5a762c-cff7-4c1a-a602-447cf21fca38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434492031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.434492031
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.838838183
Short name T1396
Test name
Test status
Simulation time 281570839 ps
CPU time 11.36 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 217880 kb
Host smart-ce0c220b-7b19-47ad-bd3c-d5bab904ee64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838838183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.838838183
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2280621882
Short name T833
Test name
Test status
Simulation time 205491947 ps
CPU time 8.42 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:20 PM PDT 24
Peak memory 217888 kb
Host smart-648e79b9-b41c-4426-b205-d878b4e24475
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280621882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2280621882
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.37842429
Short name T315
Test name
Test status
Simulation time 189051447 ps
CPU time 6.03 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:16:58 PM PDT 24
Peak memory 217884 kb
Host smart-d8c4d06a-6d7d-4502-a26f-3d162067cca5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37842429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.37842429
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3747680824
Short name T767
Test name
Test status
Simulation time 220738240 ps
CPU time 9.51 seconds
Started Mar 19 03:20:09 PM PDT 24
Finished Mar 19 03:20:20 PM PDT 24
Peak memory 226032 kb
Host smart-c3de8b6e-5814-434f-aa28-28e66ac9976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747680824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3747680824
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.680124109
Short name T98
Test name
Test status
Simulation time 318515624 ps
CPU time 11.89 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:01 PM PDT 24
Peak memory 224692 kb
Host smart-53725be9-4417-4b7c-8554-90ea3ff104a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680124109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.680124109
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2706553253
Short name T958
Test name
Test status
Simulation time 39185370 ps
CPU time 2.33 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:16 PM PDT 24
Peak memory 217812 kb
Host smart-152359b1-ea63-43c7-bc93-6690d0dba923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706553253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2706553253
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.824857723
Short name T632
Test name
Test status
Simulation time 65284639 ps
CPU time 1.18 seconds
Started Mar 19 03:16:47 PM PDT 24
Finished Mar 19 03:16:48 PM PDT 24
Peak memory 213288 kb
Host smart-3e855372-9c2d-4c9b-b118-876176ac6e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824857723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.824857723
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.107627165
Short name T1410
Test name
Test status
Simulation time 742298543 ps
CPU time 36.25 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 249400 kb
Host smart-0a645415-b124-4ec7-a994-5474e69d0d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107627165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.107627165
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.99336983
Short name T846
Test name
Test status
Simulation time 209842141 ps
CPU time 23.75 seconds
Started Mar 19 03:16:45 PM PDT 24
Finished Mar 19 03:17:09 PM PDT 24
Peak memory 250860 kb
Host smart-cb575716-8e93-4db7-920b-1ce7e98b9da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99336983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.99336983
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1316902802
Short name T626
Test name
Test status
Simulation time 88352696 ps
CPU time 7.89 seconds
Started Mar 19 03:20:09 PM PDT 24
Finished Mar 19 03:20:17 PM PDT 24
Peak memory 242772 kb
Host smart-ea1a0d85-2026-4503-a8c5-52b9b8dcf93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316902802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1316902802
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1375435078
Short name T363
Test name
Test status
Simulation time 1015507494 ps
CPU time 2.65 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:16:52 PM PDT 24
Peak memory 217792 kb
Host smart-bbbd430c-6bb6-43de-b2f0-40e0b164bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375435078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1375435078
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2961286672
Short name T1195
Test name
Test status
Simulation time 4501312405 ps
CPU time 156.09 seconds
Started Mar 19 03:20:10 PM PDT 24
Finished Mar 19 03:22:47 PM PDT 24
Peak memory 267424 kb
Host smart-7d06d92b-ba76-4b2a-9a4d-023c5755e0bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961286672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2961286672
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3960153761
Short name T463
Test name
Test status
Simulation time 922344193 ps
CPU time 53.97 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 267688 kb
Host smart-6f93c4c4-0bd6-4ea8-bcc8-9d3af01f0804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960153761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3960153761
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1432354225
Short name T817
Test name
Test status
Simulation time 14849848 ps
CPU time 0.95 seconds
Started Mar 19 03:20:10 PM PDT 24
Finished Mar 19 03:20:12 PM PDT 24
Peak memory 211468 kb
Host smart-2eeece74-ede6-4ffd-9344-63e62d1bdfb1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432354225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1432354225
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.457370820
Short name T919
Test name
Test status
Simulation time 33939769 ps
CPU time 0.93 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:16:50 PM PDT 24
Peak memory 211520 kb
Host smart-8d484bf6-8e75-421a-bc0b-1ee311fdc20d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457370820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.457370820
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1391918285
Short name T429
Test name
Test status
Simulation time 19480448 ps
CPU time 1.13 seconds
Started Mar 19 03:20:15 PM PDT 24
Finished Mar 19 03:20:16 PM PDT 24
Peak memory 209592 kb
Host smart-2f09aec0-19af-4954-a815-a0e74999fa64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391918285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1391918285
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3436897365
Short name T1321
Test name
Test status
Simulation time 21934501 ps
CPU time 0.97 seconds
Started Mar 19 03:16:51 PM PDT 24
Finished Mar 19 03:16:52 PM PDT 24
Peak memory 209624 kb
Host smart-63db2d3a-5e17-4946-992e-565e7aeeada9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436897365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3436897365
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1156680342
Short name T1019
Test name
Test status
Simulation time 9099118164 ps
CPU time 13.77 seconds
Started Mar 19 03:16:53 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 218416 kb
Host smart-7c936112-5302-44b7-a150-f7c0f1f492fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156680342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1156680342
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.4131285843
Short name T517
Test name
Test status
Simulation time 661128770 ps
CPU time 12.68 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 225476 kb
Host smart-9aa570ef-0d2f-45e4-b3cf-2fe3e6bf92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131285843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4131285843
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2914058868
Short name T497
Test name
Test status
Simulation time 1203505092 ps
CPU time 6.03 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:16:59 PM PDT 24
Peak memory 217152 kb
Host smart-6976a539-3cca-48c4-9341-d3fb622369fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914058868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2914058868
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.814123113
Short name T1200
Test name
Test status
Simulation time 2733752710 ps
CPU time 6.06 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:19 PM PDT 24
Peak memory 209532 kb
Host smart-6ea583f6-ddfb-400a-b542-a05ae0446e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814123113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.814123113
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2656820449
Short name T1486
Test name
Test status
Simulation time 69781656 ps
CPU time 3.01 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:51 PM PDT 24
Peak memory 217976 kb
Host smart-9177d81b-ccd7-42e0-8013-4b087bd685ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656820449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2656820449
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.857087133
Short name T187
Test name
Test status
Simulation time 30931747 ps
CPU time 2.05 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 221772 kb
Host smart-daf06128-c65d-4ebf-a50d-e372b294328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857087133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.857087133
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1099481968
Short name T638
Test name
Test status
Simulation time 526088749 ps
CPU time 15.95 seconds
Started Mar 19 03:16:51 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 226080 kb
Host smart-7015e93b-827d-4d18-ad64-626dbbe39a4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099481968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1099481968
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3699686012
Short name T386
Test name
Test status
Simulation time 1376871630 ps
CPU time 28.77 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 218888 kb
Host smart-9908282d-ac4c-4442-818e-e28a298289a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699686012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3699686012
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1808696416
Short name T616
Test name
Test status
Simulation time 395135917 ps
CPU time 10.57 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:00 PM PDT 24
Peak memory 217904 kb
Host smart-cebc199c-3c3a-4437-8a23-91af4d538e9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808696416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1808696416
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2392292601
Short name T1603
Test name
Test status
Simulation time 488256640 ps
CPU time 9.95 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:23 PM PDT 24
Peak memory 217888 kb
Host smart-3e16eb91-1563-4feb-b86c-583eae5cb9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392292601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2392292601
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2399222189
Short name T809
Test name
Test status
Simulation time 5255958858 ps
CPU time 7.27 seconds
Started Mar 19 03:16:50 PM PDT 24
Finished Mar 19 03:16:57 PM PDT 24
Peak memory 218068 kb
Host smart-efba4c7a-4efd-4e04-a8a9-2a055b501c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399222189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2399222189
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2401794117
Short name T1420
Test name
Test status
Simulation time 1409689238 ps
CPU time 10.04 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 217904 kb
Host smart-92264caa-027a-4def-91b0-692bb945b921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401794117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2401794117
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1795137903
Short name T1165
Test name
Test status
Simulation time 248559495 ps
CPU time 7.25 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:16:59 PM PDT 24
Peak memory 224632 kb
Host smart-b46e71bc-e6df-4380-b95f-3e5f616c5377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795137903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1795137903
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3498207343
Short name T725
Test name
Test status
Simulation time 1966796879 ps
CPU time 10.87 seconds
Started Mar 19 03:20:10 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 225444 kb
Host smart-9536fc41-babd-4845-859b-bd6a9b5e07b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498207343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3498207343
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2443178488
Short name T1550
Test name
Test status
Simulation time 47054971 ps
CPU time 2.88 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 214596 kb
Host smart-3657ed14-539d-41fd-ba42-e2758b8ddd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443178488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2443178488
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2754895511
Short name T1185
Test name
Test status
Simulation time 24468384 ps
CPU time 1.32 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:16:54 PM PDT 24
Peak memory 213240 kb
Host smart-c2509ac0-7fd6-4380-9244-b0d622d5411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754895511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2754895511
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2655770049
Short name T1253
Test name
Test status
Simulation time 228263617 ps
CPU time 24.41 seconds
Started Mar 19 03:16:50 PM PDT 24
Finished Mar 19 03:17:14 PM PDT 24
Peak memory 250880 kb
Host smart-25d7a359-56d5-4658-8378-ddc37e4e4267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655770049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2655770049
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.341808491
Short name T432
Test name
Test status
Simulation time 1278275273 ps
CPU time 32.15 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 250908 kb
Host smart-74a98a12-8ee6-4496-8c16-a77d01000314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341808491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.341808491
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3318098888
Short name T910
Test name
Test status
Simulation time 184171184 ps
CPU time 7.87 seconds
Started Mar 19 03:20:14 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 250764 kb
Host smart-6e998b11-6b27-40e9-8528-4751f06428da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318098888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3318098888
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.435047710
Short name T1166
Test name
Test status
Simulation time 334370096 ps
CPU time 3.36 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:51 PM PDT 24
Peak memory 217876 kb
Host smart-7729d47f-acfa-440d-b4c8-763a4eaf9e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435047710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.435047710
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2473851274
Short name T1668
Test name
Test status
Simulation time 12481609047 ps
CPU time 80.92 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:18:10 PM PDT 24
Peak memory 272624 kb
Host smart-ff79373e-9499-455d-adee-486af954e4aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473851274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2473851274
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3951502640
Short name T617
Test name
Test status
Simulation time 5031511607 ps
CPU time 82.06 seconds
Started Mar 19 03:20:14 PM PDT 24
Finished Mar 19 03:21:37 PM PDT 24
Peak memory 249188 kb
Host smart-24ffec17-fcc2-4697-9c2c-c3993b2fbe2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951502640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3951502640
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3911412192
Short name T119
Test name
Test status
Simulation time 54629988486 ps
CPU time 1672.81 seconds
Started Mar 19 03:16:47 PM PDT 24
Finished Mar 19 03:44:40 PM PDT 24
Peak memory 343624 kb
Host smart-5328b988-4288-464e-84e0-7ff519caec99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3911412192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3911412192
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2938079176
Short name T952
Test name
Test status
Simulation time 16806095 ps
CPU time 0.9 seconds
Started Mar 19 03:16:50 PM PDT 24
Finished Mar 19 03:16:51 PM PDT 24
Peak memory 212752 kb
Host smart-bbc96c6a-bc47-4bbe-b9b1-e5874a08c613
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938079176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2938079176
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3519696922
Short name T718
Test name
Test status
Simulation time 13557571 ps
CPU time 0.86 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:14 PM PDT 24
Peak memory 211512 kb
Host smart-2b294a74-2d0e-4807-94ae-6b0ea779ebc8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519696922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3519696922
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1066426495
Short name T979
Test name
Test status
Simulation time 49105370 ps
CPU time 0.95 seconds
Started Mar 19 03:20:14 PM PDT 24
Finished Mar 19 03:20:16 PM PDT 24
Peak memory 209608 kb
Host smart-413aab8a-9cae-4a41-8fa4-a4481612ce89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066426495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1066426495
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3044146763
Short name T421
Test name
Test status
Simulation time 81524649 ps
CPU time 0.92 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:16:50 PM PDT 24
Peak memory 209544 kb
Host smart-8e89e622-fecc-4893-8d5e-6b66dbb9694c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044146763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3044146763
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1000865080
Short name T505
Test name
Test status
Simulation time 398711398 ps
CPU time 11.36 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:24 PM PDT 24
Peak memory 217928 kb
Host smart-f8af2330-050d-413e-af91-d9ce8ca1f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000865080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1000865080
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3557801614
Short name T633
Test name
Test status
Simulation time 515173028 ps
CPU time 16.04 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:05 PM PDT 24
Peak memory 226060 kb
Host smart-ce6ad009-7a14-4760-b9d9-98a1218844d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557801614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3557801614
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1843922156
Short name T1127
Test name
Test status
Simulation time 798231974 ps
CPU time 8.79 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 209472 kb
Host smart-549c7267-d873-4591-8846-3af4c0f2b672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843922156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1843922156
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3355669790
Short name T31
Test name
Test status
Simulation time 1762768502 ps
CPU time 10.93 seconds
Started Mar 19 03:16:46 PM PDT 24
Finished Mar 19 03:16:57 PM PDT 24
Peak memory 209472 kb
Host smart-db53d5ff-fa6b-4ef5-b4a7-c033d2c3e392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355669790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3355669790
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2986185651
Short name T1609
Test name
Test status
Simulation time 189212103 ps
CPU time 2.17 seconds
Started Mar 19 03:16:50 PM PDT 24
Finished Mar 19 03:16:53 PM PDT 24
Peak memory 221664 kb
Host smart-778617ef-3f9d-4c99-90ef-263e505e9b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986185651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2986185651
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3663683626
Short name T985
Test name
Test status
Simulation time 56263387 ps
CPU time 2.23 seconds
Started Mar 19 03:20:16 PM PDT 24
Finished Mar 19 03:20:18 PM PDT 24
Peak memory 218120 kb
Host smart-81299c92-375d-430e-980b-85b5b0fc6614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663683626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3663683626
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3576362477
Short name T260
Test name
Test status
Simulation time 1058722607 ps
CPU time 9.27 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 218888 kb
Host smart-e1794aee-5ab7-4205-aee6-057c49db83db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576362477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3576362477
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3682930466
Short name T1052
Test name
Test status
Simulation time 1183611666 ps
CPU time 11.85 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:17:04 PM PDT 24
Peak memory 219128 kb
Host smart-21fdef58-2423-4971-88a9-75bcd1bee910
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682930466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3682930466
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1567627344
Short name T1260
Test name
Test status
Simulation time 1544001322 ps
CPU time 9.14 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:57 PM PDT 24
Peak memory 217868 kb
Host smart-d59a81ee-d27a-4abc-bf80-481e467f4900
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567627344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1567627344
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2398045903
Short name T1374
Test name
Test status
Simulation time 1791992731 ps
CPU time 15.68 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:30 PM PDT 24
Peak memory 217736 kb
Host smart-26e123ec-a3fb-4fb5-91ed-16692542b154
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398045903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2398045903
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1968361700
Short name T56
Test name
Test status
Simulation time 1599858843 ps
CPU time 14.32 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 217952 kb
Host smart-4543f656-8d19-4251-9fc6-b36000204a4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968361700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1968361700
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2581332308
Short name T1292
Test name
Test status
Simulation time 1672430317 ps
CPU time 13.99 seconds
Started Mar 19 03:16:46 PM PDT 24
Finished Mar 19 03:17:00 PM PDT 24
Peak memory 217908 kb
Host smart-bfb09d4e-5dd9-404f-a44b-262a80b6a03d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581332308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2581332308
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1414871762
Short name T776
Test name
Test status
Simulation time 3529354092 ps
CPU time 8.76 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 226132 kb
Host smart-d1ef09c0-8ecf-4d4f-b7f9-0081ecbed03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414871762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1414871762
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3891672345
Short name T1266
Test name
Test status
Simulation time 3800266136 ps
CPU time 9.13 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 226176 kb
Host smart-b485b1b8-ac10-4424-8791-fb341c64977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891672345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3891672345
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.278265857
Short name T1306
Test name
Test status
Simulation time 127478566 ps
CPU time 2.83 seconds
Started Mar 19 03:16:51 PM PDT 24
Finished Mar 19 03:16:54 PM PDT 24
Peak memory 214112 kb
Host smart-6bd8accf-1daa-486d-b130-c63824617323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278265857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.278265857
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2934968312
Short name T1191
Test name
Test status
Simulation time 24641744 ps
CPU time 1.33 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 213584 kb
Host smart-59ed9e20-175d-4c50-bb7e-8864071a2828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934968312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2934968312
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1305969140
Short name T1378
Test name
Test status
Simulation time 937101571 ps
CPU time 24.23 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 245748 kb
Host smart-cbb7b5eb-6d18-42fc-8c23-3c9f4fd42bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305969140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1305969140
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3685992683
Short name T1327
Test name
Test status
Simulation time 865190710 ps
CPU time 28.36 seconds
Started Mar 19 03:20:08 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 250912 kb
Host smart-ed77e0d6-fe8a-4415-a06b-76eb91d5d248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685992683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3685992683
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1378829719
Short name T1131
Test name
Test status
Simulation time 638091896 ps
CPU time 6.65 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:55 PM PDT 24
Peak memory 242708 kb
Host smart-f346df7e-19e1-4011-a3b2-c2a99e39825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378829719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1378829719
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3815333415
Short name T993
Test name
Test status
Simulation time 723158005 ps
CPU time 7.45 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:19 PM PDT 24
Peak memory 250324 kb
Host smart-464ee834-264a-4ac3-a797-86bc9e98e971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815333415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3815333415
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2112243682
Short name T1536
Test name
Test status
Simulation time 10359835285 ps
CPU time 80.64 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:21:33 PM PDT 24
Peak memory 251056 kb
Host smart-a02c88bd-0335-47d2-9198-4fd39abaa708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112243682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2112243682
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.4235338245
Short name T1239
Test name
Test status
Simulation time 6255724653 ps
CPU time 139.71 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:19:08 PM PDT 24
Peak memory 270416 kb
Host smart-1a891a07-4b44-43b3-ae25-230e1b0f02b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235338245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.4235338245
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1119645081
Short name T196
Test name
Test status
Simulation time 17957516962 ps
CPU time 638.03 seconds
Started Mar 19 03:20:08 PM PDT 24
Finished Mar 19 03:30:47 PM PDT 24
Peak memory 496872 kb
Host smart-b1cfaa24-3ad8-4fed-a35e-8e72b8d96893
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1119645081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1119645081
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2507523369
Short name T884
Test name
Test status
Simulation time 42956117 ps
CPU time 0.94 seconds
Started Mar 19 03:20:10 PM PDT 24
Finished Mar 19 03:20:12 PM PDT 24
Peak memory 212616 kb
Host smart-eebf7403-78c8-4c57-b295-09124a9a7ae8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507523369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2507523369
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.350296897
Short name T841
Test name
Test status
Simulation time 12120389 ps
CPU time 0.97 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 211564 kb
Host smart-86e75544-eda2-4f0b-9860-25753bbd9716
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350296897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.350296897
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1912260738
Short name T1566
Test name
Test status
Simulation time 23498966 ps
CPU time 1.04 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 209588 kb
Host smart-c1fa174e-3956-4772-b776-3b026ac1b1c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912260738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1912260738
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3398195975
Short name T576
Test name
Test status
Simulation time 38676826 ps
CPU time 0.96 seconds
Started Mar 19 03:20:14 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 209532 kb
Host smart-00f89408-d67c-41f6-89e3-ee26d9cfee8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398195975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3398195975
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1280592478
Short name T361
Test name
Test status
Simulation time 1949896474 ps
CPU time 10.79 seconds
Started Mar 19 03:16:47 PM PDT 24
Finished Mar 19 03:16:58 PM PDT 24
Peak memory 217872 kb
Host smart-6b781008-a209-4ec7-bcb1-c826395ac1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280592478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1280592478
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2509430168
Short name T1045
Test name
Test status
Simulation time 726993710 ps
CPU time 7.63 seconds
Started Mar 19 03:20:17 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 217892 kb
Host smart-9a3625e8-0dde-4a79-9c7a-0b739cc33f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509430168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2509430168
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1144010342
Short name T27
Test name
Test status
Simulation time 1580945338 ps
CPU time 3.98 seconds
Started Mar 19 03:16:51 PM PDT 24
Finished Mar 19 03:16:55 PM PDT 24
Peak memory 216732 kb
Host smart-b1911af1-7834-465f-a71d-393bd9ce3213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144010342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1144010342
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2985283516
Short name T1421
Test name
Test status
Simulation time 420085103 ps
CPU time 1.85 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:14 PM PDT 24
Peak memory 209480 kb
Host smart-ed8b5c5e-4587-483d-be84-ee3381e740a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985283516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2985283516
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3108021482
Short name T737
Test name
Test status
Simulation time 427606856 ps
CPU time 4.86 seconds
Started Mar 19 03:16:50 PM PDT 24
Finished Mar 19 03:16:55 PM PDT 24
Peak memory 222252 kb
Host smart-bda69824-f584-4b15-ae0d-6f37d58499b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108021482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3108021482
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.962569629
Short name T904
Test name
Test status
Simulation time 77574043 ps
CPU time 4.12 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 221888 kb
Host smart-02733ee1-19d2-49df-8c03-4e09c96cc1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962569629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.962569629
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1325338413
Short name T331
Test name
Test status
Simulation time 908473805 ps
CPU time 17.95 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:17:06 PM PDT 24
Peak memory 226036 kb
Host smart-928bea85-67f4-4435-8acc-62c0e66fa733
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325338413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1325338413
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1218213146
Short name T592
Test name
Test status
Simulation time 374965569 ps
CPU time 13.93 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:03 PM PDT 24
Peak memory 217872 kb
Host smart-5b579e0a-ddc4-4ca6-999a-f7580738cb98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218213146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1218213146
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2487178032
Short name T1241
Test name
Test status
Simulation time 289042198 ps
CPU time 9 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:23 PM PDT 24
Peak memory 217912 kb
Host smart-fb4be16a-3037-47fc-a4cb-61917db5e3c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487178032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2487178032
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.628678662
Short name T1376
Test name
Test status
Simulation time 1409832838 ps
CPU time 11.11 seconds
Started Mar 19 03:20:14 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 217748 kb
Host smart-0a5fb27f-2875-49f8-95a6-ecbaae25610c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628678662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.628678662
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.680362464
Short name T1629
Test name
Test status
Simulation time 390850649 ps
CPU time 10.37 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:16:59 PM PDT 24
Peak memory 217896 kb
Host smart-c57f3a19-081b-44c3-b37f-f5700bfad500
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680362464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.680362464
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1405746315
Short name T580
Test name
Test status
Simulation time 391219793 ps
CPU time 14.85 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:27 PM PDT 24
Peak memory 224768 kb
Host smart-64fde5c2-8f97-4321-a876-743ad0d2d032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405746315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1405746315
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1804324877
Short name T461
Test name
Test status
Simulation time 988462683 ps
CPU time 10.9 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:00 PM PDT 24
Peak memory 224884 kb
Host smart-014fdfc0-b90b-4d47-b3fd-a58c7af39343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804324877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1804324877
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1687148946
Short name T1105
Test name
Test status
Simulation time 117092832 ps
CPU time 3.52 seconds
Started Mar 19 03:20:18 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 217612 kb
Host smart-d13e6bad-5a75-4713-a2a2-49c6b98c3594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687148946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1687148946
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.635944877
Short name T71
Test name
Test status
Simulation time 292083228 ps
CPU time 3.16 seconds
Started Mar 19 03:16:50 PM PDT 24
Finished Mar 19 03:16:54 PM PDT 24
Peak memory 214172 kb
Host smart-b35b83e9-1515-48db-9d70-7f7d96c4caaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635944877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.635944877
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1663519039
Short name T289
Test name
Test status
Simulation time 638220182 ps
CPU time 25.95 seconds
Started Mar 19 03:16:50 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 250936 kb
Host smart-bfbfaa3a-876f-45c7-aa68-3ebc0178e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663519039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1663519039
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3501992119
Short name T380
Test name
Test status
Simulation time 208332837 ps
CPU time 21.13 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:34 PM PDT 24
Peak memory 250960 kb
Host smart-955ac346-9fff-4ff6-bc23-afbf8b246cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501992119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3501992119
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2640491419
Short name T742
Test name
Test status
Simulation time 1493993786 ps
CPU time 3.51 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:18 PM PDT 24
Peak memory 226216 kb
Host smart-e5bcf87c-3bd2-4cb5-9d2b-896cbf3fe896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640491419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2640491419
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3501331475
Short name T1384
Test name
Test status
Simulation time 259163548 ps
CPU time 8.3 seconds
Started Mar 19 03:16:46 PM PDT 24
Finished Mar 19 03:16:54 PM PDT 24
Peak memory 250500 kb
Host smart-8886083f-6883-4db5-b5d3-571e4e9bde73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501331475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3501331475
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1070839422
Short name T430
Test name
Test status
Simulation time 921910873 ps
CPU time 15.69 seconds
Started Mar 19 03:20:16 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 226060 kb
Host smart-7fd30fb7-6ccc-4eda-bc4e-1e7dbe7ff9db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070839422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1070839422
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1773278255
Short name T1653
Test name
Test status
Simulation time 9858420812 ps
CPU time 157.01 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:19:26 PM PDT 24
Peak memory 283940 kb
Host smart-14a9b485-c921-44f3-8394-91ab189a7fd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773278255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1773278255
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1408727629
Short name T1214
Test name
Test status
Simulation time 39721742 ps
CPU time 1.04 seconds
Started Mar 19 03:16:46 PM PDT 24
Finished Mar 19 03:16:47 PM PDT 24
Peak memory 211644 kb
Host smart-791adee7-d463-4094-bbbe-995fb5f8f1df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408727629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1408727629
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1858582125
Short name T658
Test name
Test status
Simulation time 51436832 ps
CPU time 0.95 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:13 PM PDT 24
Peak memory 212048 kb
Host smart-1795e2a4-129c-4b79-9813-cd85c413413e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858582125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1858582125
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1667102512
Short name T1295
Test name
Test status
Simulation time 16364179 ps
CPU time 0.89 seconds
Started Mar 19 03:20:16 PM PDT 24
Finished Mar 19 03:20:17 PM PDT 24
Peak memory 209596 kb
Host smart-be94ac4f-5069-4ad6-ac15-0027ded0bb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667102512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1667102512
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1852820091
Short name T582
Test name
Test status
Simulation time 25122510 ps
CPU time 1.32 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:16:50 PM PDT 24
Peak memory 209620 kb
Host smart-afc60a26-7836-4b1b-bb2d-1d1fa25f7184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852820091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1852820091
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1104626867
Short name T1660
Test name
Test status
Simulation time 2476483062 ps
CPU time 10.04 seconds
Started Mar 19 03:20:11 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 225292 kb
Host smart-238b2024-d029-40a8-96a9-723f001c5d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104626867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1104626867
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2009866378
Short name T535
Test name
Test status
Simulation time 243314883 ps
CPU time 11.23 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:59 PM PDT 24
Peak memory 217952 kb
Host smart-a64ebefa-c351-4f43-b791-48dedba6e34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009866378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2009866378
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1086590575
Short name T670
Test name
Test status
Simulation time 567689218 ps
CPU time 6.12 seconds
Started Mar 19 03:20:10 PM PDT 24
Finished Mar 19 03:20:17 PM PDT 24
Peak memory 209500 kb
Host smart-3378dd00-fe3f-4113-9ac2-469e18dae9b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086590575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1086590575
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1940337580
Short name T1658
Test name
Test status
Simulation time 962521823 ps
CPU time 9.99 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 216928 kb
Host smart-b80747ad-7e44-4bff-8b80-178d13b9c7a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940337580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1940337580
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2787316356
Short name T469
Test name
Test status
Simulation time 50057587 ps
CPU time 1.72 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 218024 kb
Host smart-c640db1d-d5fb-429d-b0cf-590a706ddeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787316356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2787316356
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2791829650
Short name T451
Test name
Test status
Simulation time 41736458 ps
CPU time 2.19 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:50 PM PDT 24
Peak memory 221712 kb
Host smart-d44551c0-3ffc-43c4-989a-599fd59b36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791829650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2791829650
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1523821710
Short name T94
Test name
Test status
Simulation time 1245936207 ps
CPU time 12.98 seconds
Started Mar 19 03:20:10 PM PDT 24
Finished Mar 19 03:20:24 PM PDT 24
Peak memory 225996 kb
Host smart-1985ebec-e72a-4bef-9b0a-7e1aa6692da2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523821710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1523821710
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1564108111
Short name T641
Test name
Test status
Simulation time 264354865 ps
CPU time 13.24 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 225868 kb
Host smart-ce69b2ff-6536-4c9b-ad9c-ad2da93acda3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564108111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1564108111
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2902256806
Short name T732
Test name
Test status
Simulation time 1365852043 ps
CPU time 10.45 seconds
Started Mar 19 03:16:53 PM PDT 24
Finished Mar 19 03:17:04 PM PDT 24
Peak memory 217928 kb
Host smart-b3d63f9f-ef3b-41a8-84ca-a321e5b87b14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902256806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2902256806
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.518022260
Short name T938
Test name
Test status
Simulation time 695356537 ps
CPU time 9.25 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:23 PM PDT 24
Peak memory 217880 kb
Host smart-351da06e-68b6-4c8c-876c-b0485226eed0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518022260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.518022260
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1862172150
Short name T1568
Test name
Test status
Simulation time 1685306700 ps
CPU time 11.23 seconds
Started Mar 19 03:16:53 PM PDT 24
Finished Mar 19 03:17:04 PM PDT 24
Peak memory 217904 kb
Host smart-e8349e66-1ded-4faf-80cf-e32327cc9108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862172150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1862172150
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.4044610648
Short name T1284
Test name
Test status
Simulation time 479090818 ps
CPU time 6.91 seconds
Started Mar 19 03:20:18 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 217788 kb
Host smart-7bd42929-da19-4e41-b3fe-2857adb5ebe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044610648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
4044610648
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1028622403
Short name T1115
Test name
Test status
Simulation time 258649850 ps
CPU time 9.2 seconds
Started Mar 19 03:16:53 PM PDT 24
Finished Mar 19 03:17:03 PM PDT 24
Peak memory 224752 kb
Host smart-6bf226b3-b128-468a-bf42-3a81fb52238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028622403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1028622403
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3458701118
Short name T520
Test name
Test status
Simulation time 315489179 ps
CPU time 10.06 seconds
Started Mar 19 03:20:14 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 226044 kb
Host smart-5ad5bea3-ba7d-4d9e-be7c-c56fb7fff8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458701118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3458701118
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1035414904
Short name T997
Test name
Test status
Simulation time 32691091 ps
CPU time 1.21 seconds
Started Mar 19 03:16:51 PM PDT 24
Finished Mar 19 03:16:52 PM PDT 24
Peak memory 213016 kb
Host smart-4ca0d346-43bd-40a4-af51-206a0ae08357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035414904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1035414904
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1836582860
Short name T1237
Test name
Test status
Simulation time 129156328 ps
CPU time 2.31 seconds
Started Mar 19 03:20:13 PM PDT 24
Finished Mar 19 03:20:16 PM PDT 24
Peak memory 213708 kb
Host smart-0aa77502-3276-47cb-8cb4-91bd3456842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836582860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1836582860
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.108788515
Short name T1639
Test name
Test status
Simulation time 1076792953 ps
CPU time 21.3 seconds
Started Mar 19 03:20:09 PM PDT 24
Finished Mar 19 03:20:31 PM PDT 24
Peak memory 250896 kb
Host smart-fc288f1d-2b5a-4c05-8ac6-9ff06f868d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108788515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.108788515
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1840717942
Short name T1121
Test name
Test status
Simulation time 166046689 ps
CPU time 27.75 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 248420 kb
Host smart-5c546ee8-b5a0-4f5c-839f-0cc0629616df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840717942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1840717942
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4091019965
Short name T1084
Test name
Test status
Simulation time 64040681 ps
CPU time 6.79 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:19 PM PDT 24
Peak memory 242764 kb
Host smart-b5f674bc-b922-42aa-b10c-7a349de9283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091019965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4091019965
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.42763062
Short name T1559
Test name
Test status
Simulation time 221448775 ps
CPU time 3.4 seconds
Started Mar 19 03:16:47 PM PDT 24
Finished Mar 19 03:16:51 PM PDT 24
Peak memory 222276 kb
Host smart-29448416-8345-4b06-a4cb-626da9f0e877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42763062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.42763062
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4234989171
Short name T1209
Test name
Test status
Simulation time 10370172556 ps
CPU time 425.76 seconds
Started Mar 19 03:16:53 PM PDT 24
Finished Mar 19 03:23:59 PM PDT 24
Peak memory 283740 kb
Host smart-de53ebcb-cf1d-46b5-9b8c-5da5e9f17ddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234989171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4234989171
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.31919572
Short name T1496
Test name
Test status
Simulation time 36190747 ps
CPU time 0.84 seconds
Started Mar 19 03:20:17 PM PDT 24
Finished Mar 19 03:20:18 PM PDT 24
Peak memory 211584 kb
Host smart-36986bfb-85cd-45c1-ad89-1cdb61f176cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31919572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctr
l_volatile_unlock_smoke.31919572
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.908295242
Short name T1213
Test name
Test status
Simulation time 39250251 ps
CPU time 0.96 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:16:50 PM PDT 24
Peak memory 212648 kb
Host smart-e05d1070-101b-4681-867c-62e1b95e1ae4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908295242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.908295242
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2921682995
Short name T1100
Test name
Test status
Simulation time 103759761 ps
CPU time 0.96 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:08 PM PDT 24
Peak memory 209624 kb
Host smart-518c646e-e486-4c7d-9679-592f8f020602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921682995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2921682995
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3625899742
Short name T1042
Test name
Test status
Simulation time 59686878 ps
CPU time 1.12 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 209624 kb
Host smart-abb16f0f-b36a-4097-9e94-8ca64be899e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625899742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3625899742
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1283586271
Short name T813
Test name
Test status
Simulation time 577352837 ps
CPU time 13.8 seconds
Started Mar 19 03:20:12 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 217892 kb
Host smart-187d1864-866d-46d3-8b6a-3759a317cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283586271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1283586271
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.4014792616
Short name T543
Test name
Test status
Simulation time 235029410 ps
CPU time 8.48 seconds
Started Mar 19 03:16:53 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 217976 kb
Host smart-76edb47a-2b06-4e05-a8c7-833c38e15b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014792616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.4014792616
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1208262550
Short name T1135
Test name
Test status
Simulation time 3107498364 ps
CPU time 7.76 seconds
Started Mar 19 03:20:18 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 209604 kb
Host smart-b8b14ac7-92a0-4dff-be8f-89571fafede0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208262550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1208262550
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3483059564
Short name T1399
Test name
Test status
Simulation time 3696803049 ps
CPU time 21.53 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:10 PM PDT 24
Peak memory 209640 kb
Host smart-63f96392-4138-427b-8fcf-e8f42b011148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483059564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3483059564
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2929971483
Short name T682
Test name
Test status
Simulation time 57692124 ps
CPU time 1.58 seconds
Started Mar 19 03:20:15 PM PDT 24
Finished Mar 19 03:20:17 PM PDT 24
Peak memory 218000 kb
Host smart-b76f3c33-8166-41b9-a757-9fd3731d747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929971483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2929971483
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4079619286
Short name T259
Test name
Test status
Simulation time 555161641 ps
CPU time 3.77 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:16:56 PM PDT 24
Peak memory 221916 kb
Host smart-1ca28537-82d8-42e1-8890-a4c598fe6d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079619286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4079619286
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3129485563
Short name T1075
Test name
Test status
Simulation time 460358297 ps
CPU time 17.57 seconds
Started Mar 19 03:20:18 PM PDT 24
Finished Mar 19 03:20:36 PM PDT 24
Peak memory 226060 kb
Host smart-6e5e0b19-6d7b-4593-92f0-f3ca0545f0ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129485563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3129485563
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.394665322
Short name T1339
Test name
Test status
Simulation time 958229211 ps
CPU time 8.89 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:17:02 PM PDT 24
Peak memory 217968 kb
Host smart-878db982-f3ff-4823-9f92-e34a99b39145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394665322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.394665322
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1655258331
Short name T1294
Test name
Test status
Simulation time 1559345140 ps
CPU time 11.07 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:19 PM PDT 24
Peak memory 217980 kb
Host smart-439b2379-49a9-452f-b466-fbf5ce956606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655258331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1655258331
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1945577186
Short name T1460
Test name
Test status
Simulation time 742423257 ps
CPU time 13.6 seconds
Started Mar 19 03:20:18 PM PDT 24
Finished Mar 19 03:20:31 PM PDT 24
Peak memory 217956 kb
Host smart-fca47cee-0fff-47b9-a892-ad8bcf544707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945577186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1945577186
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1056121032
Short name T1577
Test name
Test status
Simulation time 746775536 ps
CPU time 10.52 seconds
Started Mar 19 03:20:17 PM PDT 24
Finished Mar 19 03:20:28 PM PDT 24
Peak memory 217896 kb
Host smart-2d038147-dbf5-4343-b505-286a82855bdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056121032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1056121032
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1176387915
Short name T1035
Test name
Test status
Simulation time 250063885 ps
CPU time 9.68 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 217892 kb
Host smart-7c2eaa83-4eed-4b1f-9c79-b1a1e8c9c80a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176387915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1176387915
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3297904459
Short name T51
Test name
Test status
Simulation time 239752450 ps
CPU time 6.13 seconds
Started Mar 19 03:20:17 PM PDT 24
Finished Mar 19 03:20:24 PM PDT 24
Peak memory 224292 kb
Host smart-a732e2cd-d4e4-43c5-b47b-1495c9cbf0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297904459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3297904459
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4089256350
Short name T249
Test name
Test status
Simulation time 2034258923 ps
CPU time 14.68 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 224864 kb
Host smart-ce7eb807-d6eb-4ce3-ae5d-7d2e4d3112ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089256350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4089256350
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1179600211
Short name T1654
Test name
Test status
Simulation time 49179771 ps
CPU time 2.56 seconds
Started Mar 19 03:20:16 PM PDT 24
Finished Mar 19 03:20:18 PM PDT 24
Peak memory 214148 kb
Host smart-d8943093-a63f-43b7-b4b3-9725a41ad00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179600211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1179600211
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2807544425
Short name T73
Test name
Test status
Simulation time 173729258 ps
CPU time 3.09 seconds
Started Mar 19 03:16:53 PM PDT 24
Finished Mar 19 03:16:56 PM PDT 24
Peak memory 214124 kb
Host smart-7cd02b6f-3ce1-41bb-935f-1ecf2453a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807544425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2807544425
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1437391003
Short name T488
Test name
Test status
Simulation time 685062897 ps
CPU time 33.73 seconds
Started Mar 19 03:20:15 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 250932 kb
Host smart-2670f10e-779a-4371-a629-384758c83df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437391003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1437391003
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1891775580
Short name T415
Test name
Test status
Simulation time 1145181031 ps
CPU time 24.81 seconds
Started Mar 19 03:16:49 PM PDT 24
Finished Mar 19 03:17:14 PM PDT 24
Peak memory 250768 kb
Host smart-8bfbf9b5-8130-4658-b6b5-2912307bd0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891775580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1891775580
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3506207977
Short name T1439
Test name
Test status
Simulation time 91474044 ps
CPU time 8.01 seconds
Started Mar 19 03:20:15 PM PDT 24
Finished Mar 19 03:20:23 PM PDT 24
Peak memory 250940 kb
Host smart-e6c17913-b0c0-40c6-a484-10a0e501e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506207977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3506207977
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.4201044229
Short name T1350
Test name
Test status
Simulation time 153192216 ps
CPU time 6.06 seconds
Started Mar 19 03:16:52 PM PDT 24
Finished Mar 19 03:16:58 PM PDT 24
Peak memory 250936 kb
Host smart-5d4e358d-44a6-4beb-bc94-40daef5f84f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201044229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4201044229
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2371886666
Short name T1427
Test name
Test status
Simulation time 7104985506 ps
CPU time 72.3 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:18:22 PM PDT 24
Peak memory 268840 kb
Host smart-284cbd59-9d5b-4360-9b76-6cf91f323335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371886666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2371886666
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3666076537
Short name T106
Test name
Test status
Simulation time 1245589887 ps
CPU time 75.44 seconds
Started Mar 19 03:20:18 PM PDT 24
Finished Mar 19 03:21:34 PM PDT 24
Peak memory 254100 kb
Host smart-d2e0b837-c9bc-41be-9260-b6d8d6de13bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666076537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3666076537
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1203633775
Short name T1533
Test name
Test status
Simulation time 27406022786 ps
CPU time 778.62 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:30:02 PM PDT 24
Peak memory 277788 kb
Host smart-f3d08382-03df-4f75-80e3-a5b64eb40eb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1203633775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1203633775
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2963651391
Short name T552
Test name
Test status
Simulation time 12570248 ps
CPU time 0.97 seconds
Started Mar 19 03:20:15 PM PDT 24
Finished Mar 19 03:20:16 PM PDT 24
Peak memory 211556 kb
Host smart-ffc52ffc-10af-4f91-afe0-605a9f556ce2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963651391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2963651391
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4014322866
Short name T1670
Test name
Test status
Simulation time 14919682 ps
CPU time 1.11 seconds
Started Mar 19 03:16:48 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 211660 kb
Host smart-2c61e253-c77b-4371-9c1f-b974d98abaf4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014322866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4014322866
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2492090225
Short name T524
Test name
Test status
Simulation time 21069825 ps
CPU time 1.1 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:06 PM PDT 24
Peak memory 209656 kb
Host smart-92082670-054f-4ddd-b5f2-a8ff4008ced1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492090225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2492090225
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.961723011
Short name T1030
Test name
Test status
Simulation time 39527791 ps
CPU time 1.25 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:20:22 PM PDT 24
Peak memory 209612 kb
Host smart-82c02e39-e0cc-405c-b7bd-9294d1353a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961723011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.961723011
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.201853333
Short name T264
Test name
Test status
Simulation time 3889794153 ps
CPU time 13.55 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 218264 kb
Host smart-4174f5b3-804a-4fd4-8dce-a43b50c22f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201853333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.201853333
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3735562859
Short name T1356
Test name
Test status
Simulation time 408805743 ps
CPU time 9.1 seconds
Started Mar 19 03:17:03 PM PDT 24
Finished Mar 19 03:17:12 PM PDT 24
Peak memory 217976 kb
Host smart-7f5702ac-0999-4f3c-90a5-f6f808adddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735562859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3735562859
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1397497523
Short name T792
Test name
Test status
Simulation time 771715344 ps
CPU time 11.06 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:20:34 PM PDT 24
Peak memory 209464 kb
Host smart-af99e2f4-bf29-4bb0-ae6c-e0e940eeb449
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397497523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1397497523
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2309588937
Short name T369
Test name
Test status
Simulation time 239310543 ps
CPU time 2.56 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:31 PM PDT 24
Peak memory 221884 kb
Host smart-df558b4e-c8b1-49b2-9b71-fd3db8e2d559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309588937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2309588937
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.4137766413
Short name T1525
Test name
Test status
Simulation time 86692606 ps
CPU time 3.09 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:17:11 PM PDT 24
Peak memory 218072 kb
Host smart-5a268d5b-b057-4c6a-968d-151c98d155a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137766413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.4137766413
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1392846208
Short name T1199
Test name
Test status
Simulation time 1752784710 ps
CPU time 21.96 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:29 PM PDT 24
Peak memory 218920 kb
Host smart-a4e59ed3-f23a-4d6a-8c7d-f0717b9bbddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392846208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1392846208
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.20461036
Short name T1647
Test name
Test status
Simulation time 272295824 ps
CPU time 10.49 seconds
Started Mar 19 03:20:30 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 218924 kb
Host smart-b523fc92-2f50-48ba-9bb4-d7a83f6bd85c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20461036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.20461036
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1507808311
Short name T485
Test name
Test status
Simulation time 252979309 ps
CPU time 11.1 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 217900 kb
Host smart-ea3ffd66-98f6-47e3-8fe0-6e622a86637b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507808311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1507808311
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2094270687
Short name T738
Test name
Test status
Simulation time 299552917 ps
CPU time 12.42 seconds
Started Mar 19 03:20:28 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 217840 kb
Host smart-13a6ccfb-75a0-4a8b-8f09-b0df5e134445
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094270687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2094270687
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2944422477
Short name T704
Test name
Test status
Simulation time 2075975029 ps
CPU time 13.67 seconds
Started Mar 19 03:20:28 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 217892 kb
Host smart-dcca00b0-a803-441a-bc01-74ea97d95a78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944422477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2944422477
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3628707678
Short name T566
Test name
Test status
Simulation time 619034020 ps
CPU time 7.85 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 217840 kb
Host smart-ea70f831-058b-4e03-9e96-738f9b21d4df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628707678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3628707678
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2158723871
Short name T848
Test name
Test status
Simulation time 478533166 ps
CPU time 9.94 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 226036 kb
Host smart-a91bae7d-cbbb-4206-8162-84c090ecbf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158723871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2158723871
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.229564495
Short name T835
Test name
Test status
Simulation time 328737106 ps
CPU time 11.99 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:39 PM PDT 24
Peak memory 225252 kb
Host smart-7a59ae0b-31f7-479b-bffd-91cef4179c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229564495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.229564495
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2247185994
Short name T878
Test name
Test status
Simulation time 474570691 ps
CPU time 2.48 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 217652 kb
Host smart-21cd37b6-08be-492a-8bc2-05dac9939791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247185994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2247185994
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4197358483
Short name T70
Test name
Test status
Simulation time 276356533 ps
CPU time 1.56 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:06 PM PDT 24
Peak memory 213488 kb
Host smart-fe5553ba-9876-4bb3-baee-86ae20911a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197358483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4197358483
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1838464805
Short name T969
Test name
Test status
Simulation time 1169196660 ps
CPU time 34.39 seconds
Started Mar 19 03:17:03 PM PDT 24
Finished Mar 19 03:17:38 PM PDT 24
Peak memory 250932 kb
Host smart-81d0c018-1820-43ce-9bfc-86e0cfc70799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838464805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1838464805
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.369807734
Short name T973
Test name
Test status
Simulation time 707583537 ps
CPU time 31.01 seconds
Started Mar 19 03:20:20 PM PDT 24
Finished Mar 19 03:20:52 PM PDT 24
Peak memory 250704 kb
Host smart-0dc1f80b-4d39-4f37-a716-a54ea1af2605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369807734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.369807734
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1900274932
Short name T1198
Test name
Test status
Simulation time 599321739 ps
CPU time 8.5 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 250840 kb
Host smart-6c3d84ea-1313-4d16-a95d-e453f86d174f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900274932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1900274932
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.246326629
Short name T779
Test name
Test status
Simulation time 577627238 ps
CPU time 7.92 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:20:30 PM PDT 24
Peak memory 247000 kb
Host smart-9bbbb477-5b79-40a4-a49b-50eb43d3eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246326629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.246326629
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3528607791
Short name T1348
Test name
Test status
Simulation time 24620886479 ps
CPU time 198.65 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:20:28 PM PDT 24
Peak memory 251084 kb
Host smart-b64b79cd-3c62-4a24-8bf9-4a100a5779ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528607791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3528607791
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3658160187
Short name T40
Test name
Test status
Simulation time 47825237755 ps
CPU time 120.91 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 251192 kb
Host smart-9fe5636c-0e65-4b1a-a438-d9bb4ade4c2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658160187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3658160187
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1666386673
Short name T185
Test name
Test status
Simulation time 21819115356 ps
CPU time 427.68 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:27:29 PM PDT 24
Peak memory 259412 kb
Host smart-8c061a19-d350-44fc-ac6c-9bd6b0d302a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1666386673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1666386673
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.106367280
Short name T702
Test name
Test status
Simulation time 42322800 ps
CPU time 0.97 seconds
Started Mar 19 03:17:03 PM PDT 24
Finished Mar 19 03:17:04 PM PDT 24
Peak memory 211648 kb
Host smart-429ea9dd-3c71-474d-8ce9-b89176ae6013
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106367280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.106367280
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2842004461
Short name T1080
Test name
Test status
Simulation time 45940108 ps
CPU time 0.88 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:20:23 PM PDT 24
Peak memory 212524 kb
Host smart-21114600-9446-483e-8e93-55e4bbd259a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842004461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2842004461
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2732388618
Short name T86
Test name
Test status
Simulation time 59929397 ps
CPU time 0.91 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 209592 kb
Host smart-b01ad2bd-a1db-4230-9ba5-f4af2bda1029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732388618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2732388618
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3947058854
Short name T1307
Test name
Test status
Simulation time 290854628 ps
CPU time 1.17 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:09 PM PDT 24
Peak memory 209584 kb
Host smart-f6ea927e-6ca1-4806-8be3-84ffbee3a320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947058854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3947058854
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.215488696
Short name T441
Test name
Test status
Simulation time 499623307 ps
CPU time 12.21 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 217928 kb
Host smart-6ee0d1b6-2df6-45b0-8c44-74d86daa09dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215488696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.215488696
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3497397577
Short name T1212
Test name
Test status
Simulation time 292930924 ps
CPU time 13.17 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:47 PM PDT 24
Peak memory 217948 kb
Host smart-89409e10-b6f0-46f7-9a2d-fb05a27e7c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497397577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3497397577
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2181819715
Short name T1542
Test name
Test status
Simulation time 178069602 ps
CPU time 2.99 seconds
Started Mar 19 03:20:25 PM PDT 24
Finished Mar 19 03:20:28 PM PDT 24
Peak memory 209460 kb
Host smart-004247e0-f98d-4ccb-8546-a6bc30320701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181819715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2181819715
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.607467494
Short name T1323
Test name
Test status
Simulation time 449416239 ps
CPU time 10.75 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:17:19 PM PDT 24
Peak memory 216868 kb
Host smart-2d6b7759-f8bc-4105-b68d-391471e4d84c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607467494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.607467494
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3999938240
Short name T1179
Test name
Test status
Simulation time 58458954 ps
CPU time 2.33 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:09 PM PDT 24
Peak memory 221712 kb
Host smart-b5fb96aa-085b-46ec-a1ef-d40ad6cfdfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999938240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3999938240
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4169719738
Short name T172
Test name
Test status
Simulation time 60986344 ps
CPU time 2.47 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:34 PM PDT 24
Peak memory 221792 kb
Host smart-bdfef5c4-dfc3-4ac5-a6e1-270a433fbf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169719738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4169719738
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.151809037
Short name T290
Test name
Test status
Simulation time 4988986372 ps
CPU time 16.32 seconds
Started Mar 19 03:20:24 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 226160 kb
Host smart-6b882bd6-b041-410d-8435-3282ac4005e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151809037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.151809037
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1989885145
Short name T389
Test name
Test status
Simulation time 403385087 ps
CPU time 17.16 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:25 PM PDT 24
Peak memory 226076 kb
Host smart-cb6a3e5a-354e-47ed-b382-2112a5e4a3ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989885145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1989885145
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.140954058
Short name T680
Test name
Test status
Simulation time 320984565 ps
CPU time 9.72 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:17 PM PDT 24
Peak memory 217916 kb
Host smart-58719c68-8145-400b-9159-7b9d36fe5a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140954058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.140954058
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.648365460
Short name T903
Test name
Test status
Simulation time 529849303 ps
CPU time 12.13 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:39 PM PDT 24
Peak memory 217868 kb
Host smart-c96c41d1-5317-4e9f-aaf9-0eb1114cb524
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648365460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.648365460
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1640987768
Short name T1555
Test name
Test status
Simulation time 1591682369 ps
CPU time 8.62 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:14 PM PDT 24
Peak memory 217864 kb
Host smart-4141e631-9547-4316-947f-a10aec04b47f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640987768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1640987768
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3069010889
Short name T1675
Test name
Test status
Simulation time 823844427 ps
CPU time 7.92 seconds
Started Mar 19 03:20:20 PM PDT 24
Finished Mar 19 03:20:28 PM PDT 24
Peak memory 217940 kb
Host smart-899e5c08-c8f1-4c23-ba04-850aa854ce5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069010889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3069010889
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3029116664
Short name T1362
Test name
Test status
Simulation time 990858424 ps
CPU time 9.43 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:14 PM PDT 24
Peak memory 224948 kb
Host smart-c2c5439e-ec4d-4814-9e70-8f69c10caac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029116664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3029116664
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.804995637
Short name T46
Test name
Test status
Simulation time 729915712 ps
CPU time 13.78 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:20:36 PM PDT 24
Peak memory 224808 kb
Host smart-23b2c659-c26b-49f0-abaf-16524c507828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804995637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.804995637
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1136267051
Short name T494
Test name
Test status
Simulation time 147180401 ps
CPU time 8.56 seconds
Started Mar 19 03:20:27 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 217800 kb
Host smart-23d5c8b2-7d7a-4035-95b4-df710d0ef759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136267051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1136267051
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1952827502
Short name T1358
Test name
Test status
Simulation time 44796517 ps
CPU time 2.26 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:08 PM PDT 24
Peak memory 213832 kb
Host smart-080a6674-ef89-4020-ab29-0baa5551f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952827502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1952827502
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1427769721
Short name T1406
Test name
Test status
Simulation time 273495256 ps
CPU time 23.83 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 251012 kb
Host smart-54b01dd0-f22a-41ee-97cc-3326e4b2d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427769721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1427769721
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2914521421
Short name T1570
Test name
Test status
Simulation time 321004513 ps
CPU time 24.93 seconds
Started Mar 19 03:17:09 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 250900 kb
Host smart-4301eb87-d11e-4966-99fd-e152c23c28d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914521421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2914521421
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2659871382
Short name T775
Test name
Test status
Simulation time 324633527 ps
CPU time 6.82 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:14 PM PDT 24
Peak memory 245888 kb
Host smart-fd8fb72b-b033-4939-8858-02595e168a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659871382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2659871382
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2816337549
Short name T1498
Test name
Test status
Simulation time 77923764 ps
CPU time 8.19 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 245808 kb
Host smart-044ff885-7c97-47ee-9021-6e37b4223f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816337549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2816337549
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.299155439
Short name T1269
Test name
Test status
Simulation time 559556064 ps
CPU time 17.82 seconds
Started Mar 19 03:20:28 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 226036 kb
Host smart-f4f013a6-5afb-48d3-a96b-d3f0be6d6c4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299155439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.299155439
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.413738805
Short name T1415
Test name
Test status
Simulation time 48419916635 ps
CPU time 323.97 seconds
Started Mar 19 03:17:03 PM PDT 24
Finished Mar 19 03:22:27 PM PDT 24
Peak memory 267440 kb
Host smart-ee6bece7-912b-49df-92e7-c650e0c86127
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413738805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.413738805
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3009127365
Short name T173
Test name
Test status
Simulation time 29801333729 ps
CPU time 1092.78 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:38:34 PM PDT 24
Peak memory 496912 kb
Host smart-0c14dd5d-6d55-4988-9086-1bff5fc46db8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3009127365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3009127365
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1071251418
Short name T456
Test name
Test status
Simulation time 12136488 ps
CPU time 0.85 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:27 PM PDT 24
Peak memory 211540 kb
Host smart-81c83b8b-ce4c-4f00-a165-f951f8123d35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071251418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1071251418
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4163355977
Short name T1312
Test name
Test status
Simulation time 13731394 ps
CPU time 1.04 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 211556 kb
Host smart-5bf6698b-0f68-483b-a13f-e59c72963971
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163355977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4163355977
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3160236223
Short name T1119
Test name
Test status
Simulation time 32335903 ps
CPU time 0.99 seconds
Started Mar 19 03:19:07 PM PDT 24
Finished Mar 19 03:19:08 PM PDT 24
Peak memory 209688 kb
Host smart-60556583-36f6-49d1-b1e0-cff1524db511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160236223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3160236223
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3361198674
Short name T872
Test name
Test status
Simulation time 98450071 ps
CPU time 0.93 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 209584 kb
Host smart-7fbe8d64-cc83-4b8b-8a5c-70c19dac0c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361198674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3361198674
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2910146686
Short name T731
Test name
Test status
Simulation time 13288298 ps
CPU time 0.81 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:32 PM PDT 24
Peak memory 209392 kb
Host smart-8a2e5f40-7ab0-40b3-b549-653b4e716ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910146686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2910146686
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.776325566
Short name T238
Test name
Test status
Simulation time 33282499 ps
CPU time 0.91 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:18:59 PM PDT 24
Peak memory 209464 kb
Host smart-bf712e90-d840-489c-81fc-e57f1097e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776325566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.776325566
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.741292796
Short name T999
Test name
Test status
Simulation time 1059901515 ps
CPU time 9.1 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:42 PM PDT 24
Peak memory 226040 kb
Host smart-84d03429-d68a-41e1-9e44-f558cdcd62b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741292796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.741292796
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3579148913
Short name T32
Test name
Test status
Simulation time 285086838 ps
CPU time 8.08 seconds
Started Mar 19 03:19:01 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 216852 kb
Host smart-02a8b181-fddb-4ecf-b67a-a740b333fad0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579148913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3579148913
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.996287993
Short name T1484
Test name
Test status
Simulation time 313333349 ps
CPU time 4.09 seconds
Started Mar 19 03:15:35 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 216612 kb
Host smart-310f8ccd-1157-4fad-a422-26c913722258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996287993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.996287993
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1799563384
Short name T1473
Test name
Test status
Simulation time 4133461303 ps
CPU time 59.52 seconds
Started Mar 19 03:19:12 PM PDT 24
Finished Mar 19 03:20:11 PM PDT 24
Peak memory 219064 kb
Host smart-66f37a02-fa82-4e89-9f98-8e6aad141ba7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799563384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1799563384
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.603525709
Short name T882
Test name
Test status
Simulation time 28270274798 ps
CPU time 26.37 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:16:00 PM PDT 24
Peak memory 217988 kb
Host smart-9f1c2098-d172-4b36-a32c-66b7aa901eea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603525709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.603525709
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1397501446
Short name T699
Test name
Test status
Simulation time 886532321 ps
CPU time 17.06 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:15 PM PDT 24
Peak memory 217352 kb
Host smart-9ae8635a-a26f-4a94-99a2-fa72814c70ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397501446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
397501446
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1974846744
Short name T1076
Test name
Test status
Simulation time 273478403 ps
CPU time 3.91 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:38 PM PDT 24
Peak memory 209560 kb
Host smart-a2f96e5b-8aa9-4d06-95b5-a6733741f4e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974846744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
974846744
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1921299281
Short name T1029
Test name
Test status
Simulation time 137332174 ps
CPU time 2.88 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:18 PM PDT 24
Peak memory 217996 kb
Host smart-a6bcb4f1-b471-458d-ab8e-1d1f50ee199d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921299281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1921299281
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4173875766
Short name T370
Test name
Test status
Simulation time 2320854297 ps
CPU time 7 seconds
Started Mar 19 03:15:38 PM PDT 24
Finished Mar 19 03:15:45 PM PDT 24
Peak memory 217976 kb
Host smart-fbb3e141-f6af-445e-8e00-67e563a2039d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173875766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4173875766
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1553901318
Short name T1039
Test name
Test status
Simulation time 1220999923 ps
CPU time 13.96 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:49 PM PDT 24
Peak memory 213124 kb
Host smart-c0ba266a-4cce-4e9f-95a3-0bfc490590c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553901318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1553901318
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3576374938
Short name T5
Test name
Test status
Simulation time 1091165645 ps
CPU time 27.88 seconds
Started Mar 19 03:19:16 PM PDT 24
Finished Mar 19 03:19:44 PM PDT 24
Peak memory 213288 kb
Host smart-25ec3a81-66da-4097-bf2d-80f3b64bd77c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576374938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3576374938
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2870375578
Short name T745
Test name
Test status
Simulation time 705761373 ps
CPU time 5.04 seconds
Started Mar 19 03:18:59 PM PDT 24
Finished Mar 19 03:19:04 PM PDT 24
Peak memory 213488 kb
Host smart-118a0059-eb7d-4960-bda9-35b8ef080629
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870375578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2870375578
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3532725454
Short name T375
Test name
Test status
Simulation time 5278250193 ps
CPU time 10.87 seconds
Started Mar 19 03:15:30 PM PDT 24
Finished Mar 19 03:15:41 PM PDT 24
Peak memory 214456 kb
Host smart-2d45ed9f-5b37-4eaa-8f31-1f95a190f6bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532725454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3532725454
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1892579952
Short name T194
Test name
Test status
Simulation time 2151948507 ps
CPU time 34.22 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 251364 kb
Host smart-8eb44cf3-24b2-4213-bcf9-d3d297c1f9be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892579952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1892579952
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.733994907
Short name T1328
Test name
Test status
Simulation time 991437722 ps
CPU time 46.07 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:16:18 PM PDT 24
Peak memory 251492 kb
Host smart-c2738c6a-36db-41dd-a1b6-26d6c7398585
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733994907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.733994907
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3314448604
Short name T437
Test name
Test status
Simulation time 1046970358 ps
CPU time 10.91 seconds
Started Mar 19 03:15:30 PM PDT 24
Finished Mar 19 03:15:41 PM PDT 24
Peak memory 250416 kb
Host smart-53d9450f-14f0-41f4-8fc5-82ce16f72ee8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314448604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3314448604
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.676071223
Short name T1437
Test name
Test status
Simulation time 4251154443 ps
CPU time 11.05 seconds
Started Mar 19 03:19:03 PM PDT 24
Finished Mar 19 03:19:14 PM PDT 24
Peak memory 250532 kb
Host smart-b477d20c-5f52-4b3d-810c-a671fa67be1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676071223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.676071223
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3561606361
Short name T874
Test name
Test status
Simulation time 500903158 ps
CPU time 2.03 seconds
Started Mar 19 03:18:59 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 218020 kb
Host smart-90fe5c86-2d8c-455c-a649-504fa3deadd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561606361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3561606361
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.787972050
Short name T1278
Test name
Test status
Simulation time 54601365 ps
CPU time 2.58 seconds
Started Mar 19 03:15:38 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 221584 kb
Host smart-4d1e3e95-518f-4c34-bcc0-43f6903fce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787972050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.787972050
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3165073775
Short name T995
Test name
Test status
Simulation time 244210371 ps
CPU time 9.16 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:09 PM PDT 24
Peak memory 217848 kb
Host smart-42b1850a-932a-4f4c-b724-bec4bfe7b6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165073775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3165073775
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.344797560
Short name T367
Test name
Test status
Simulation time 801888189 ps
CPU time 9.12 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 214368 kb
Host smart-fa20373e-9ff6-4196-8b6c-d2cc13b3f5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344797560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.344797560
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2010281041
Short name T100
Test name
Test status
Simulation time 2238418202 ps
CPU time 37.2 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:16:12 PM PDT 24
Peak memory 268936 kb
Host smart-11a98493-38e2-489e-911b-397f78a25462
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010281041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2010281041
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2484042554
Short name T101
Test name
Test status
Simulation time 214656694 ps
CPU time 26.1 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 281696 kb
Host smart-82cba4d3-0c3d-4cb7-9fa5-57471bde0f43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484042554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2484042554
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1853980283
Short name T602
Test name
Test status
Simulation time 621541600 ps
CPU time 16.35 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:17 PM PDT 24
Peak memory 218740 kb
Host smart-08804cf7-c47b-4c12-ac17-f6927add9a65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853980283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1853980283
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3884817983
Short name T555
Test name
Test status
Simulation time 476607643 ps
CPU time 9.49 seconds
Started Mar 19 03:15:35 PM PDT 24
Finished Mar 19 03:15:45 PM PDT 24
Peak memory 218688 kb
Host smart-40fa5cbb-af0a-42cc-9a86-450067cbec72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884817983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3884817983
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3191407742
Short name T1569
Test name
Test status
Simulation time 2458611053 ps
CPU time 10.43 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 217964 kb
Host smart-47470785-3c34-43ca-9121-d5f7e8018526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191407742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3191407742
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.820183140
Short name T558
Test name
Test status
Simulation time 353065994 ps
CPU time 10.6 seconds
Started Mar 19 03:19:12 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 217916 kb
Host smart-d9af4b84-d8bf-48fc-a54b-d9602dab608a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820183140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.820183140
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.285359043
Short name T1432
Test name
Test status
Simulation time 307902325 ps
CPU time 12.73 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:47 PM PDT 24
Peak memory 217868 kb
Host smart-93a4659b-4b0c-4465-8503-203491bc653f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285359043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.285359043
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4270112683
Short name T1005
Test name
Test status
Simulation time 392451429 ps
CPU time 9.87 seconds
Started Mar 19 03:19:12 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 217880 kb
Host smart-3d6a3035-e0b7-4529-9ea7-d3f1040f9b52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270112683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
270112683
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.236169018
Short name T800
Test name
Test status
Simulation time 578451099 ps
CPU time 20.49 seconds
Started Mar 19 03:15:31 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 225992 kb
Host smart-f2a92c7e-4df8-46f6-b4e8-e059503c2060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236169018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.236169018
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.974447528
Short name T532
Test name
Test status
Simulation time 387032998 ps
CPU time 10.78 seconds
Started Mar 19 03:19:04 PM PDT 24
Finished Mar 19 03:19:15 PM PDT 24
Peak memory 225836 kb
Host smart-05b40e98-b95f-4624-ace0-8bd5261179c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974447528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.974447528
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3660879654
Short name T1017
Test name
Test status
Simulation time 24504602 ps
CPU time 1.88 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 213644 kb
Host smart-a7a969e0-c724-4591-8ea4-23f813d8fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660879654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3660879654
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.694747882
Short name T700
Test name
Test status
Simulation time 108712316 ps
CPU time 3.52 seconds
Started Mar 19 03:18:59 PM PDT 24
Finished Mar 19 03:19:03 PM PDT 24
Peak memory 214196 kb
Host smart-96c78a78-3883-48ab-9ada-40331e34757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694747882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.694747882
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1158270783
Short name T527
Test name
Test status
Simulation time 285578375 ps
CPU time 33.05 seconds
Started Mar 19 03:15:30 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 250860 kb
Host smart-cdf904a9-b196-4df8-adc2-84d8d3084f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158270783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1158270783
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3050747975
Short name T1082
Test name
Test status
Simulation time 1093365252 ps
CPU time 23.36 seconds
Started Mar 19 03:18:59 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 249148 kb
Host smart-a9e14b4d-d230-4fae-b8f6-3b45ad6c90ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050747975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3050747975
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1206265493
Short name T320
Test name
Test status
Simulation time 159688861 ps
CPU time 10.26 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:11 PM PDT 24
Peak memory 250928 kb
Host smart-e05576ef-d940-4ced-ab96-825d50b4b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206265493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1206265493
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1288292229
Short name T1522
Test name
Test status
Simulation time 3199104509 ps
CPU time 71.34 seconds
Started Mar 19 03:15:38 PM PDT 24
Finished Mar 19 03:16:50 PM PDT 24
Peak memory 283216 kb
Host smart-9ee7295f-0ddf-46ea-ae98-aa29ea802eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288292229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1288292229
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.840595101
Short name T514
Test name
Test status
Simulation time 2843607428 ps
CPU time 46.31 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:46 PM PDT 24
Peak memory 246912 kb
Host smart-c5281548-ff26-4e72-929e-ce2de9bebee0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840595101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.840595101
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2195758252
Short name T177
Test name
Test status
Simulation time 51813784317 ps
CPU time 2063.95 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:50:02 PM PDT 24
Peak memory 1562836 kb
Host smart-95e10124-9cb2-4689-a2b1-ad56303dabb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2195758252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2195758252
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1393072899
Short name T1434
Test name
Test status
Simulation time 14391825 ps
CPU time 0.92 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:34 PM PDT 24
Peak memory 211564 kb
Host smart-cdafcf92-2aa9-4776-bfbc-3dd9934cdd68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393072899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1393072899
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2106655140
Short name T781
Test name
Test status
Simulation time 47759232 ps
CPU time 1.18 seconds
Started Mar 19 03:19:08 PM PDT 24
Finished Mar 19 03:19:09 PM PDT 24
Peak memory 212928 kb
Host smart-70194c31-d982-4977-bf81-887457d2df10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106655140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2106655140
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.220029898
Short name T1454
Test name
Test status
Simulation time 42096122 ps
CPU time 0.97 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 209612 kb
Host smart-136bfaa4-a9e9-43eb-a280-7d7a38b37b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220029898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.220029898
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3844982533
Short name T1034
Test name
Test status
Simulation time 56899228 ps
CPU time 1.14 seconds
Started Mar 19 03:20:23 PM PDT 24
Finished Mar 19 03:20:24 PM PDT 24
Peak memory 209600 kb
Host smart-ae442199-f373-4d1f-b790-de98eb89271d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844982533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3844982533
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3150931962
Short name T502
Test name
Test status
Simulation time 565796834 ps
CPU time 22.61 seconds
Started Mar 19 03:20:25 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 225724 kb
Host smart-02ba7ee3-47fe-4971-8672-e8936f1e35d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150931962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3150931962
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4011849348
Short name T1501
Test name
Test status
Simulation time 235899344 ps
CPU time 11.33 seconds
Started Mar 19 03:17:03 PM PDT 24
Finished Mar 19 03:17:15 PM PDT 24
Peak memory 225500 kb
Host smart-72bbc8ab-dc60-4102-a422-06c56d17947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011849348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4011849348
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2899206453
Short name T1463
Test name
Test status
Simulation time 2428570342 ps
CPU time 7.55 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 209676 kb
Host smart-86f44374-245a-4d82-bb00-6aff4140c52b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899206453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2899206453
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3275760597
Short name T1216
Test name
Test status
Simulation time 1381636754 ps
CPU time 7.17 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 216860 kb
Host smart-a5b8272f-4450-44b8-a490-8c175792b614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275760597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3275760597
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.644224784
Short name T368
Test name
Test status
Simulation time 63895309 ps
CPU time 1.5 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 217968 kb
Host smart-0ff7d9cc-720f-420b-a81c-4f21791248b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644224784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.644224784
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.877753870
Short name T1098
Test name
Test status
Simulation time 128172593 ps
CPU time 1.82 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:31 PM PDT 24
Peak memory 218048 kb
Host smart-c6e32815-623e-4644-81a5-cdc45c382d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877753870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.877753870
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1013433598
Short name T805
Test name
Test status
Simulation time 1251788634 ps
CPU time 16.17 seconds
Started Mar 19 03:20:25 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 218892 kb
Host smart-09abad76-5565-4f54-ab44-9015942b1db0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013433598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1013433598
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4193357973
Short name T1413
Test name
Test status
Simulation time 1097353051 ps
CPU time 13.1 seconds
Started Mar 19 03:17:09 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 226060 kb
Host smart-5bceec90-ac60-4582-ad5b-9ffdad6be6aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193357973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4193357973
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1871594920
Short name T1066
Test name
Test status
Simulation time 1542905665 ps
CPU time 14.66 seconds
Started Mar 19 03:20:23 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 217976 kb
Host smart-fb1c7a45-a1b2-4268-b819-f8e0ba0beb3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871594920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1871594920
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3590315320
Short name T1370
Test name
Test status
Simulation time 1386410435 ps
CPU time 14.19 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:17:23 PM PDT 24
Peak memory 217980 kb
Host smart-8029e056-2dc5-4721-a71c-2a9e83b1c346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590315320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3590315320
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2260553808
Short name T1683
Test name
Test status
Simulation time 1233146185 ps
CPU time 7.55 seconds
Started Mar 19 03:20:24 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 217904 kb
Host smart-a2e5f89d-0de0-4d09-bd5e-6588b9b1786e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260553808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2260553808
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.908557093
Short name T1341
Test name
Test status
Simulation time 1023909479 ps
CPU time 9.78 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 217880 kb
Host smart-05697291-81bf-4bc1-9395-d59840b233d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908557093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.908557093
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1533472324
Short name T1697
Test name
Test status
Simulation time 607423966 ps
CPU time 8.14 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:14 PM PDT 24
Peak memory 224512 kb
Host smart-255abf94-28cc-4b00-a2c6-a99dd003db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533472324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1533472324
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.911561341
Short name T691
Test name
Test status
Simulation time 296847550 ps
CPU time 10.59 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:20:33 PM PDT 24
Peak memory 226024 kb
Host smart-4c6f0246-0e7c-45e0-8e7c-16badc5fa9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911561341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.911561341
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1765994594
Short name T746
Test name
Test status
Simulation time 39071890 ps
CPU time 2.95 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 214260 kb
Host smart-4f116d2d-6424-4a58-bb54-65f98362489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765994594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1765994594
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.4002331555
Short name T455
Test name
Test status
Simulation time 77503453 ps
CPU time 3.08 seconds
Started Mar 19 03:20:20 PM PDT 24
Finished Mar 19 03:20:24 PM PDT 24
Peak memory 213916 kb
Host smart-10dd6aa7-5ec6-44db-a5e5-7b5dc89ad8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002331555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.4002331555
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1925606769
Short name T406
Test name
Test status
Simulation time 498777786 ps
CPU time 29.75 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:20:52 PM PDT 24
Peak memory 250904 kb
Host smart-794c7023-a448-402c-912d-4e3c10a0cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925606769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1925606769
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.702955765
Short name T1377
Test name
Test status
Simulation time 1514873736 ps
CPU time 25.42 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:30 PM PDT 24
Peak memory 246640 kb
Host smart-87b0b338-ba06-453b-b643-c4b6d199878a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702955765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.702955765
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2864577222
Short name T336
Test name
Test status
Simulation time 312007609 ps
CPU time 6.65 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:12 PM PDT 24
Peak memory 250940 kb
Host smart-14ddb067-5f7f-45aa-ba87-031cc0721485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864577222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2864577222
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3551540594
Short name T810
Test name
Test status
Simulation time 365510579 ps
CPU time 8.17 seconds
Started Mar 19 03:20:28 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 250484 kb
Host smart-63af3b64-da20-4bb3-a612-384323c8ccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551540594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3551540594
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2750268480
Short name T829
Test name
Test status
Simulation time 17964370184 ps
CPU time 86.35 seconds
Started Mar 19 03:20:24 PM PDT 24
Finished Mar 19 03:21:51 PM PDT 24
Peak memory 254412 kb
Host smart-972389e6-c470-49e8-8e9a-19fb5c41ba12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750268480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2750268480
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3191992901
Short name T1024
Test name
Test status
Simulation time 18467666199 ps
CPU time 619.58 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:27:28 PM PDT 24
Peak memory 283848 kb
Host smart-b40a08ff-65ab-43e4-bcdf-33162b829131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191992901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3191992901
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1956523039
Short name T1604
Test name
Test status
Simulation time 13749063 ps
CPU time 0.9 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:09 PM PDT 24
Peak memory 211608 kb
Host smart-b1f34a8c-6824-4df0-a63a-52615cf6802c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956523039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1956523039
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2933528052
Short name T1346
Test name
Test status
Simulation time 14121999 ps
CPU time 1.1 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:28 PM PDT 24
Peak memory 211560 kb
Host smart-01210936-61c3-4fb3-b7bc-8d23c7d901d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933528052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2933528052
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2888316597
Short name T796
Test name
Test status
Simulation time 15937406 ps
CPU time 0.89 seconds
Started Mar 19 03:17:09 PM PDT 24
Finished Mar 19 03:17:10 PM PDT 24
Peak memory 209588 kb
Host smart-a11850c9-1688-4a18-9c06-3bf9fccf5512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888316597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2888316597
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.512566825
Short name T67
Test name
Test status
Simulation time 39301417 ps
CPU time 0.96 seconds
Started Mar 19 03:20:25 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 209608 kb
Host smart-38ba83f4-1436-4c7c-9125-73b98fbaba0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512566825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.512566825
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2653888096
Short name T786
Test name
Test status
Simulation time 990288625 ps
CPU time 12.56 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:20 PM PDT 24
Peak memory 217960 kb
Host smart-014d80b5-4e93-48af-a277-c63704c0e123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653888096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2653888096
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3484092314
Short name T1235
Test name
Test status
Simulation time 1745747242 ps
CPU time 12.48 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:39 PM PDT 24
Peak memory 217932 kb
Host smart-cb2b69fe-db15-4c00-8b30-7bd866c38287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484092314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3484092314
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3709888225
Short name T1357
Test name
Test status
Simulation time 759794340 ps
CPU time 4.16 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:08 PM PDT 24
Peak memory 216792 kb
Host smart-203e434c-2913-4ecc-8286-0aeaee4952f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709888225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3709888225
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4141259867
Short name T6
Test name
Test status
Simulation time 170969539 ps
CPU time 4.95 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 216828 kb
Host smart-743cdf23-1986-47f2-846e-1b099608d833
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141259867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.4141259867
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.262129363
Short name T250
Test name
Test status
Simulation time 346297577 ps
CPU time 4.04 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:11 PM PDT 24
Peak memory 221960 kb
Host smart-3e77c85a-b596-44b0-b15b-334c662720b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262129363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.262129363
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.939391442
Short name T899
Test name
Test status
Simulation time 31049905 ps
CPU time 1.86 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:20:24 PM PDT 24
Peak memory 221584 kb
Host smart-b00b22e4-308c-4572-a9ec-96a921028022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939391442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.939391442
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2720037370
Short name T998
Test name
Test status
Simulation time 1657523560 ps
CPU time 23.7 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:30 PM PDT 24
Peak memory 217928 kb
Host smart-20bdeb0a-038d-41b6-adee-eac1be02c949
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720037370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2720037370
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.835531627
Short name T105
Test name
Test status
Simulation time 1917487525 ps
CPU time 14.06 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 218884 kb
Host smart-4cb639dc-e8e1-4e8f-8cc4-5df3c80ebf6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835531627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.835531627
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2728166765
Short name T281
Test name
Test status
Simulation time 3233204387 ps
CPU time 11.02 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:15 PM PDT 24
Peak memory 218812 kb
Host smart-df250371-f08a-4066-a0eb-2160e7660280
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728166765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2728166765
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2953574544
Short name T1490
Test name
Test status
Simulation time 335991736 ps
CPU time 14.15 seconds
Started Mar 19 03:20:30 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 217896 kb
Host smart-9e60d16d-5f32-4f51-aafe-db8b15381071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953574544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2953574544
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2814288074
Short name T356
Test name
Test status
Simulation time 911801046 ps
CPU time 9.2 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:17:19 PM PDT 24
Peak memory 217904 kb
Host smart-75dd1765-32e3-4a52-bc05-0b330c95b120
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814288074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2814288074
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.961108941
Short name T826
Test name
Test status
Simulation time 1355459943 ps
CPU time 10.05 seconds
Started Mar 19 03:20:25 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 218084 kb
Host smart-1f8d4675-2523-4e40-8179-28c323ad74d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961108941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.961108941
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3839739941
Short name T1659
Test name
Test status
Simulation time 1346082944 ps
CPU time 9.55 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:15 PM PDT 24
Peak memory 225204 kb
Host smart-34207b4b-6349-450e-b246-e2f761a0ef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839739941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3839739941
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.825739008
Short name T245
Test name
Test status
Simulation time 351519641 ps
CPU time 12.04 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 224580 kb
Host smart-9c73f92e-b2ea-4839-88de-40e304142d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825739008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.825739008
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1864505339
Short name T600
Test name
Test status
Simulation time 22601247 ps
CPU time 2.02 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:36 PM PDT 24
Peak memory 213860 kb
Host smart-7488cee5-5e9f-42e5-be58-756648c76eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864505339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1864505339
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3094358993
Short name T939
Test name
Test status
Simulation time 95768817 ps
CPU time 2.16 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:17:10 PM PDT 24
Peak memory 214128 kb
Host smart-5fb733d0-e9ca-4949-98db-1ad47f4237eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094358993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3094358993
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2505074
Short name T594
Test name
Test status
Simulation time 4000312646 ps
CPU time 23.77 seconds
Started Mar 19 03:17:03 PM PDT 24
Finished Mar 19 03:17:27 PM PDT 24
Peak memory 251068 kb
Host smart-95a8e1dc-a831-4a76-86a6-85320962d75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2505074
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3183742365
Short name T1033
Test name
Test status
Simulation time 198027152 ps
CPU time 13.71 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 243852 kb
Host smart-dacc671a-a3b5-441c-b84e-59ebd5470efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183742365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3183742365
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1735674552
Short name T1649
Test name
Test status
Simulation time 50821539 ps
CPU time 7.84 seconds
Started Mar 19 03:17:03 PM PDT 24
Finished Mar 19 03:17:11 PM PDT 24
Peak memory 247532 kb
Host smart-4b3e249e-4608-4631-b851-fdc914c32f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735674552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1735674552
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.4133904504
Short name T1193
Test name
Test status
Simulation time 305112748 ps
CPU time 3.07 seconds
Started Mar 19 03:20:23 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 217860 kb
Host smart-04ed30ee-824a-42ea-929a-be6a8fbb92ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133904504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.4133904504
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1845361538
Short name T976
Test name
Test status
Simulation time 8641773916 ps
CPU time 54.67 seconds
Started Mar 19 03:20:28 PM PDT 24
Finished Mar 19 03:21:23 PM PDT 24
Peak memory 267388 kb
Host smart-3435fa6b-5188-4108-8f10-e34021579f2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845361538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1845361538
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2733735828
Short name T1499
Test name
Test status
Simulation time 41635046563 ps
CPU time 202.67 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:20:27 PM PDT 24
Peak memory 251068 kb
Host smart-2ef8c0bb-460c-448b-bdbe-282db7208b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733735828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2733735828
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1967864847
Short name T174
Test name
Test status
Simulation time 37711778411 ps
CPU time 1210.25 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:40:33 PM PDT 24
Peak memory 267560 kb
Host smart-9a8972d1-b7e0-4bf8-b937-62e3d112f528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1967864847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1967864847
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1356503295
Short name T352
Test name
Test status
Simulation time 11912266 ps
CPU time 0.91 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:08 PM PDT 24
Peak memory 211544 kb
Host smart-0a69e137-2e92-421c-9248-d37c86ae2a77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356503295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1356503295
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2263700189
Short name T1556
Test name
Test status
Simulation time 47228747 ps
CPU time 1.07 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 212900 kb
Host smart-2e42d609-7674-496d-8653-e153adc45118
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263700189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2263700189
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1261346063
Short name T403
Test name
Test status
Simulation time 20720437 ps
CPU time 0.94 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:30 PM PDT 24
Peak memory 209620 kb
Host smart-548b6d59-4eb5-45f9-b960-a5b1d3a1410a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261346063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1261346063
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3280901672
Short name T257
Test name
Test status
Simulation time 32916105 ps
CPU time 0.96 seconds
Started Mar 19 03:17:12 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 209644 kb
Host smart-7827d835-1c1d-44bf-9009-6a481043b31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280901672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3280901672
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1955728310
Short name T950
Test name
Test status
Simulation time 515705711 ps
CPU time 10.97 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 217892 kb
Host smart-1f45c5f3-cbbb-4840-a023-954324a58a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955728310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1955728310
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2835434770
Short name T560
Test name
Test status
Simulation time 328468837 ps
CPU time 8.76 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:17 PM PDT 24
Peak memory 226120 kb
Host smart-30814a2b-fa2f-45ef-a834-3a720cba391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835434770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2835434770
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1245687070
Short name T506
Test name
Test status
Simulation time 353874572 ps
CPU time 9.47 seconds
Started Mar 19 03:17:07 PM PDT 24
Finished Mar 19 03:17:18 PM PDT 24
Peak memory 217172 kb
Host smart-6308a896-bf8a-4fc9-b9cb-7676cb584417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245687070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1245687070
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2374435045
Short name T1407
Test name
Test status
Simulation time 150565362 ps
CPU time 1.64 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 216808 kb
Host smart-1ce2f09e-ac4e-4949-a5bf-042b0e7ef596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374435045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2374435045
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3900083721
Short name T433
Test name
Test status
Simulation time 72451659 ps
CPU time 1.63 seconds
Started Mar 19 03:17:05 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 217996 kb
Host smart-2fafd5e2-bda9-4e3f-9bff-866d83e03358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900083721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3900083721
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.522758822
Short name T272
Test name
Test status
Simulation time 290181593 ps
CPU time 3.84 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:33 PM PDT 24
Peak memory 218016 kb
Host smart-e52ce900-efc3-4939-91d0-cd213c49ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522758822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.522758822
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4264759879
Short name T947
Test name
Test status
Simulation time 2100089908 ps
CPU time 20.56 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 226068 kb
Host smart-05ed5584-6c27-4ff8-bb3c-d5fa99b780af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264759879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4264759879
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.629118639
Short name T771
Test name
Test status
Simulation time 372910333 ps
CPU time 12.27 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 218844 kb
Host smart-184cea8e-0cc6-454d-93e2-4ba0ceec449a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629118639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.629118639
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2280264608
Short name T1382
Test name
Test status
Simulation time 614768757 ps
CPU time 11.63 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 217888 kb
Host smart-6f1f270f-a351-46c7-95c1-10cdba87008f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280264608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2280264608
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3014606029
Short name T1643
Test name
Test status
Simulation time 370998952 ps
CPU time 10.81 seconds
Started Mar 19 03:17:11 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 217848 kb
Host smart-026e1de7-91b3-4ddc-aec8-5c016f13ea49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014606029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3014606029
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1890817362
Short name T1186
Test name
Test status
Simulation time 480413100 ps
CPU time 7.07 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:38 PM PDT 24
Peak memory 217908 kb
Host smart-03cc384c-a413-418c-a668-7f9dc5c98414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890817362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1890817362
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.556372113
Short name T1416
Test name
Test status
Simulation time 1771585982 ps
CPU time 7.83 seconds
Started Mar 19 03:17:11 PM PDT 24
Finished Mar 19 03:17:19 PM PDT 24
Peak memory 217884 kb
Host smart-3adef54c-8ea2-43d4-b8e2-1108c7993e59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556372113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.556372113
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1859822062
Short name T1009
Test name
Test status
Simulation time 407202619 ps
CPU time 7.57 seconds
Started Mar 19 03:17:04 PM PDT 24
Finished Mar 19 03:17:12 PM PDT 24
Peak memory 225260 kb
Host smart-20146cf4-309c-4bfa-85aa-c16a3af7e5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859822062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1859822062
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3037376927
Short name T24
Test name
Test status
Simulation time 277882879 ps
CPU time 10.99 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 224632 kb
Host smart-0fb64f33-6298-4f98-9887-a0a6eb88701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037376927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3037376927
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3434435636
Short name T426
Test name
Test status
Simulation time 154433917 ps
CPU time 2.19 seconds
Started Mar 19 03:20:22 PM PDT 24
Finished Mar 19 03:20:24 PM PDT 24
Peak memory 213472 kb
Host smart-1d2c9c7c-2d12-41de-ac3b-1c6373c73331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434435636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3434435636
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.56560742
Short name T256
Test name
Test status
Simulation time 73286493 ps
CPU time 5.32 seconds
Started Mar 19 03:17:08 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 214272 kb
Host smart-4b686b97-fc13-41b9-9d33-380777b98d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56560742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.56560742
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2505647582
Short name T479
Test name
Test status
Simulation time 441033555 ps
CPU time 20.15 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:27 PM PDT 24
Peak memory 249504 kb
Host smart-8c4799b6-3a37-4364-a4a8-76d25f518305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505647582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2505647582
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3310042984
Short name T917
Test name
Test status
Simulation time 265747799 ps
CPU time 33.52 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:21:00 PM PDT 24
Peak memory 247272 kb
Host smart-2005306d-65a2-40c6-a096-b2e1f22174b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310042984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3310042984
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1531296131
Short name T376
Test name
Test status
Simulation time 395650328 ps
CPU time 6.46 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:17:17 PM PDT 24
Peak memory 250924 kb
Host smart-a63e3107-fb34-43fa-997b-31073798c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531296131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1531296131
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2987558788
Short name T2
Test name
Test status
Simulation time 379414739 ps
CPU time 8.8 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 250868 kb
Host smart-99964a23-820c-4908-9123-42eb86d57830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987558788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2987558788
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.260619444
Short name T740
Test name
Test status
Simulation time 2150484406 ps
CPU time 91.74 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:22:03 PM PDT 24
Peak memory 270080 kb
Host smart-ff34c678-6862-4394-b2dd-8ac21be661df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260619444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.260619444
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.624388440
Short name T1541
Test name
Test status
Simulation time 47606955885 ps
CPU time 164.96 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 268824 kb
Host smart-86b347d7-3966-4d42-8eac-e471e3e5d4fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624388440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.624388440
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2404250461
Short name T1462
Test name
Test status
Simulation time 31326130 ps
CPU time 0.84 seconds
Started Mar 19 03:17:06 PM PDT 24
Finished Mar 19 03:17:08 PM PDT 24
Peak memory 208028 kb
Host smart-130a1d24-74e1-43a6-b6b2-6f8f6f9d0b58
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404250461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2404250461
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4050766587
Short name T1505
Test name
Test status
Simulation time 56293757 ps
CPU time 0.84 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:27 PM PDT 24
Peak memory 211516 kb
Host smart-c6a03156-57d7-45fe-8938-5f1b5a63d70f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050766587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.4050766587
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1086997411
Short name T659
Test name
Test status
Simulation time 58235588 ps
CPU time 1.16 seconds
Started Mar 19 03:17:12 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 209588 kb
Host smart-638cdfba-9ce6-4e43-ae7f-b3f629ce9966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086997411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1086997411
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1567074587
Short name T1371
Test name
Test status
Simulation time 39099613 ps
CPU time 0.96 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 209624 kb
Host smart-34240b7a-582e-4019-9631-b42c00fc71bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567074587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1567074587
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2293780194
Short name T303
Test name
Test status
Simulation time 639420734 ps
CPU time 25.01 seconds
Started Mar 19 03:17:11 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 217868 kb
Host smart-e514481f-8bf9-4159-899b-952ba2e0f312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293780194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2293780194
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3850672345
Short name T883
Test name
Test status
Simulation time 300183191 ps
CPU time 12.56 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:47 PM PDT 24
Peak memory 217972 kb
Host smart-f5877dea-29ab-44e5-bdc9-766ea9388175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850672345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3850672345
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2200987747
Short name T603
Test name
Test status
Simulation time 219696536 ps
CPU time 2.09 seconds
Started Mar 19 03:20:30 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 216808 kb
Host smart-4dca2a43-f52d-4d48-ba67-165f62f77211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200987747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2200987747
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3609452925
Short name T358
Test name
Test status
Simulation time 56737786 ps
CPU time 1.36 seconds
Started Mar 19 03:17:16 PM PDT 24
Finished Mar 19 03:17:17 PM PDT 24
Peak memory 209324 kb
Host smart-c1b9cdb9-9779-4d85-9c47-d78d835d713c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609452925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3609452925
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3049240029
Short name T967
Test name
Test status
Simulation time 116350445 ps
CPU time 3.03 seconds
Started Mar 19 03:17:12 PM PDT 24
Finished Mar 19 03:17:15 PM PDT 24
Peak memory 218040 kb
Host smart-b7c66731-41d6-4edd-9271-8efe835b2799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049240029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3049240029
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3774212363
Short name T1148
Test name
Test status
Simulation time 798227406 ps
CPU time 2.65 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 217884 kb
Host smart-0657bc6b-da2e-44f1-9507-c802e6fb9f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774212363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3774212363
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.215792679
Short name T353
Test name
Test status
Simulation time 478034575 ps
CPU time 12.39 seconds
Started Mar 19 03:17:11 PM PDT 24
Finished Mar 19 03:17:24 PM PDT 24
Peak memory 226008 kb
Host smart-37208667-1d7d-41d4-955b-a49559344c1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215792679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.215792679
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.4268501210
Short name T198
Test name
Test status
Simulation time 959339214 ps
CPU time 10.74 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:46 PM PDT 24
Peak memory 226060 kb
Host smart-301d1b72-4afa-48f7-9347-af9e759af78e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268501210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.4268501210
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1833048959
Short name T1508
Test name
Test status
Simulation time 291682358 ps
CPU time 8.81 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:17:19 PM PDT 24
Peak memory 217880 kb
Host smart-2bb92076-fe23-4fe5-803f-03384979cbb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833048959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1833048959
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3560420551
Short name T270
Test name
Test status
Simulation time 1117852196 ps
CPU time 8.5 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 217888 kb
Host smart-f33884e2-5249-458a-8abd-c256acd33544
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560420551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3560420551
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1391914977
Short name T1493
Test name
Test status
Simulation time 407483094 ps
CPU time 12.35 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 217964 kb
Host smart-942505c2-ba05-4b8a-b262-adeb80e20a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391914977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1391914977
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.4219827381
Short name T824
Test name
Test status
Simulation time 489195601 ps
CPU time 16.97 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:38 PM PDT 24
Peak memory 217932 kb
Host smart-58f0878c-97cf-4ad5-8fca-0ff5b443e87b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219827381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
4219827381
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2609680468
Short name T1107
Test name
Test status
Simulation time 184354157 ps
CPU time 6.32 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:19 PM PDT 24
Peak memory 224296 kb
Host smart-57deb0c1-7f8e-4786-b075-6006a5cd17ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609680468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2609680468
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.947519867
Short name T1063
Test name
Test status
Simulation time 418418598 ps
CPU time 6.29 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 224380 kb
Host smart-ac72c830-47dd-4121-bc67-398cae0cc445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947519867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.947519867
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1602928081
Short name T893
Test name
Test status
Simulation time 63554231 ps
CPU time 2.7 seconds
Started Mar 19 03:20:21 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 217672 kb
Host smart-e2972828-435f-467d-bcc3-5cbfb3c2f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602928081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1602928081
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2745090220
Short name T619
Test name
Test status
Simulation time 27275558 ps
CPU time 1.84 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:17:12 PM PDT 24
Peak memory 213632 kb
Host smart-8d562bc8-077f-41b5-9791-cd2d5c089a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745090220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2745090220
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1505463134
Short name T1262
Test name
Test status
Simulation time 312568228 ps
CPU time 32.68 seconds
Started Mar 19 03:20:30 PM PDT 24
Finished Mar 19 03:21:03 PM PDT 24
Peak memory 250804 kb
Host smart-3c3d4f67-5a84-49e4-a32e-f5cfa34fac31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505463134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1505463134
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3965464388
Short name T525
Test name
Test status
Simulation time 573859413 ps
CPU time 21.58 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:17:36 PM PDT 24
Peak memory 250944 kb
Host smart-55c85104-16aa-439e-9c48-be659519fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965464388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3965464388
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.181992791
Short name T798
Test name
Test status
Simulation time 368097140 ps
CPU time 6.95 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 250380 kb
Host smart-d66b1542-c7df-4bdf-bc85-347d257b0525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181992791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.181992791
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2567639525
Short name T880
Test name
Test status
Simulation time 322660885 ps
CPU time 9.01 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 250708 kb
Host smart-04cf79b2-5c3f-435d-a7ee-75d85f7129bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567639525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2567639525
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2277726475
Short name T1571
Test name
Test status
Simulation time 11054424411 ps
CPU time 147.72 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 283872 kb
Host smart-db9e4886-b484-4a96-9b0d-27cb8d85b847
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277726475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2277726475
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.670146077
Short name T1201
Test name
Test status
Simulation time 41290112429 ps
CPU time 110.97 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 277644 kb
Host smart-0538d7d8-c2be-4961-a3d9-4abdc5448132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670146077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.670146077
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3009742740
Short name T183
Test name
Test status
Simulation time 52320700947 ps
CPU time 1812.07 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:47:22 PM PDT 24
Peak memory 513340 kb
Host smart-c1b18175-266b-4b2e-a7a1-d5d762ea54f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3009742740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3009742740
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.114398633
Short name T91
Test name
Test status
Simulation time 13641881 ps
CPU time 0.92 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 211500 kb
Host smart-756ea661-f430-4d9a-9696-ec639791196f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114398633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.114398633
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2251506344
Short name T200
Test name
Test status
Simulation time 36140492 ps
CPU time 0.91 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 211456 kb
Host smart-d957136f-13c8-4067-8a63-7d92c34da903
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251506344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2251506344
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3261426996
Short name T1488
Test name
Test status
Simulation time 61368118 ps
CPU time 1.05 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:17:12 PM PDT 24
Peak memory 209592 kb
Host smart-2ffa6659-deba-4196-aea9-202bd0dcdd04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261426996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3261426996
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.361998375
Short name T95
Test name
Test status
Simulation time 67895647 ps
CPU time 0.97 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 209560 kb
Host smart-878d12df-b390-4498-b07b-b2d99a55b93f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361998375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.361998375
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3328878402
Short name T853
Test name
Test status
Simulation time 1341818124 ps
CPU time 10.54 seconds
Started Mar 19 03:17:16 PM PDT 24
Finished Mar 19 03:17:27 PM PDT 24
Peak memory 217828 kb
Host smart-f3ab7044-8687-4e5a-9548-98d793fad537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328878402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3328878402
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.615824234
Short name T1071
Test name
Test status
Simulation time 484886876 ps
CPU time 17.13 seconds
Started Mar 19 03:20:26 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 217936 kb
Host smart-a8f6a258-261b-42b6-9b6d-1d2878227de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615824234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.615824234
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2844636816
Short name T29
Test name
Test status
Simulation time 461903724 ps
CPU time 11.99 seconds
Started Mar 19 03:20:29 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 209540 kb
Host smart-1f5aa373-2272-4cac-b24e-cbc31c4eaa6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844636816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2844636816
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.852081032
Short name T902
Test name
Test status
Simulation time 447907896 ps
CPU time 3 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 209480 kb
Host smart-6a8151bb-04cd-43e9-b1d2-22a2be2db4ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852081032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.852081032
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2764006155
Short name T310
Test name
Test status
Simulation time 21848886 ps
CPU time 1.56 seconds
Started Mar 19 03:17:12 PM PDT 24
Finished Mar 19 03:17:14 PM PDT 24
Peak memory 221444 kb
Host smart-0451ffe0-1328-4c76-a1ff-4d194890201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764006155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2764006155
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3012793197
Short name T604
Test name
Test status
Simulation time 329314789 ps
CPU time 2.67 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 218060 kb
Host smart-9b05e104-c72b-4d59-b7ba-a41834003523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012793197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3012793197
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1076746938
Short name T844
Test name
Test status
Simulation time 1642178819 ps
CPU time 14.46 seconds
Started Mar 19 03:17:16 PM PDT 24
Finished Mar 19 03:17:31 PM PDT 24
Peak memory 225932 kb
Host smart-1c0a7467-9268-46f8-bb55-4b25a742986f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076746938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1076746938
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3214766634
Short name T1451
Test name
Test status
Simulation time 221167611 ps
CPU time 10.49 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 217916 kb
Host smart-bf2ae90a-4572-46da-84af-12ffcc619b6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214766634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3214766634
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3658784929
Short name T788
Test name
Test status
Simulation time 824646699 ps
CPU time 8.05 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:29 PM PDT 24
Peak memory 217928 kb
Host smart-d6240e26-3548-4fb2-b4ab-3d480772ec69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658784929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3658784929
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.4043534984
Short name T916
Test name
Test status
Simulation time 240308558 ps
CPU time 9.28 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 217928 kb
Host smart-caf27ef1-2a4e-4db3-b032-1781dfd21965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043534984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.4043534984
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2094744683
Short name T371
Test name
Test status
Simulation time 1275869791 ps
CPU time 11.04 seconds
Started Mar 19 03:20:24 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 217832 kb
Host smart-f333d6d8-1d6b-400a-9ee6-2444d5a14269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094744683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2094744683
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.570668382
Short name T1022
Test name
Test status
Simulation time 460076582 ps
CPU time 10.64 seconds
Started Mar 19 03:17:16 PM PDT 24
Finished Mar 19 03:17:27 PM PDT 24
Peak memory 217824 kb
Host smart-10327fd9-fdbf-47ca-a124-614d6ef7de0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570668382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.570668382
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1353307898
Short name T248
Test name
Test status
Simulation time 799888281 ps
CPU time 13.67 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 225008 kb
Host smart-69a99007-8301-4c92-8550-01c74e607825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353307898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1353307898
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.219137710
Short name T943
Test name
Test status
Simulation time 1856318227 ps
CPU time 10.82 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 224944 kb
Host smart-d131779b-4dc0-48a2-9b96-9c29a177473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219137710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.219137710
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3265946630
Short name T1588
Test name
Test status
Simulation time 161179842 ps
CPU time 2.43 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 213788 kb
Host smart-a8613898-4603-49d4-acfb-5359ec8ee39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265946630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3265946630
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.397243423
Short name T819
Test name
Test status
Simulation time 440439630 ps
CPU time 3.44 seconds
Started Mar 19 03:20:25 PM PDT 24
Finished Mar 19 03:20:29 PM PDT 24
Peak memory 214264 kb
Host smart-a7ecf27e-8628-451c-8a9a-a72040d29eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397243423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.397243423
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2112646593
Short name T782
Test name
Test status
Simulation time 1097522608 ps
CPU time 22.49 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 245676 kb
Host smart-025174d9-7427-4ef9-a103-22d53cb9e469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112646593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2112646593
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2460884859
Short name T1026
Test name
Test status
Simulation time 197705928 ps
CPU time 23.77 seconds
Started Mar 19 03:20:24 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 248664 kb
Host smart-00691dae-475d-451e-bf50-bf50cc672761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460884859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2460884859
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1686118916
Short name T871
Test name
Test status
Simulation time 1342354435 ps
CPU time 3.87 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:25 PM PDT 24
Peak memory 217952 kb
Host smart-c6b294aa-8e2b-4150-ba64-435e88eb75ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686118916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1686118916
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3094322503
Short name T346
Test name
Test status
Simulation time 97263952 ps
CPU time 6.64 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 242768 kb
Host smart-b1a3ff54-838e-4019-ac81-cc1112b7a940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094322503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3094322503
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1099267484
Short name T202
Test name
Test status
Simulation time 3168904095 ps
CPU time 89.77 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 269944 kb
Host smart-c90160dc-b4f6-4083-9d9f-04542594b28f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099267484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1099267484
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4018923444
Short name T1440
Test name
Test status
Simulation time 16039666989 ps
CPU time 174.97 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:20:10 PM PDT 24
Peak memory 282928 kb
Host smart-62b4a876-9c95-4d6a-8cb3-0c69edd19b12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018923444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4018923444
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.231124892
Short name T424
Test name
Test status
Simulation time 11467010 ps
CPU time 0.88 seconds
Started Mar 19 03:20:31 PM PDT 24
Finished Mar 19 03:20:32 PM PDT 24
Peak memory 211564 kb
Host smart-fcc494aa-7238-48b0-849d-7ba90e7f17ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231124892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.231124892
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4134993671
Short name T1539
Test name
Test status
Simulation time 41265162 ps
CPU time 0.94 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 211496 kb
Host smart-390a473f-92a3-47b2-885a-421d4f18e832
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134993671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4134993671
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3774516377
Short name T1593
Test name
Test status
Simulation time 34844796 ps
CPU time 0.91 seconds
Started Mar 19 03:17:14 PM PDT 24
Finished Mar 19 03:17:15 PM PDT 24
Peak memory 209620 kb
Host smart-58a450e5-4985-4f52-aca9-2d095054cdb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774516377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3774516377
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4240939679
Short name T556
Test name
Test status
Simulation time 29088859 ps
CPU time 1.34 seconds
Started Mar 19 03:20:36 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 209616 kb
Host smart-fa593a1c-6503-4fb5-bc03-a6074560a203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240939679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4240939679
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1363242913
Short name T335
Test name
Test status
Simulation time 555472336 ps
CPU time 23.75 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 226056 kb
Host smart-be0b194e-2954-4869-aa52-6b2db17b8cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363242913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1363242913
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3368847925
Short name T615
Test name
Test status
Simulation time 545246841 ps
CPU time 10.81 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:32 PM PDT 24
Peak memory 217956 kb
Host smart-77d64053-ca21-4902-a3e5-1f907e913b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368847925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3368847925
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2068260504
Short name T1156
Test name
Test status
Simulation time 2026001598 ps
CPU time 11.54 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 217700 kb
Host smart-b8199a7f-d876-4275-98b5-9e27387653e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068260504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2068260504
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3631600180
Short name T1519
Test name
Test status
Simulation time 1439562201 ps
CPU time 4.97 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:18 PM PDT 24
Peak memory 209508 kb
Host smart-b668a550-d542-4020-bdfa-712d5b39caa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631600180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3631600180
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3898949929
Short name T1592
Test name
Test status
Simulation time 94207940 ps
CPU time 4.33 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 222316 kb
Host smart-d8028152-9a7d-45ac-8ddb-f1bcff441f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898949929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3898949929
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4161345009
Short name T1614
Test name
Test status
Simulation time 112588030 ps
CPU time 2.45 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 221680 kb
Host smart-d4e8542c-4212-4d27-b319-b8fea0ad7177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161345009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4161345009
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2342927109
Short name T342
Test name
Test status
Simulation time 1922144863 ps
CPU time 11.26 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 217968 kb
Host smart-7b20e687-ea92-416b-82b2-6dc21a4ba6ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342927109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2342927109
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2672921320
Short name T793
Test name
Test status
Simulation time 350117638 ps
CPU time 12.08 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:47 PM PDT 24
Peak memory 218900 kb
Host smart-502b9be4-1b34-48ac-9df8-b1356d39ee3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672921320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2672921320
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2213610998
Short name T1099
Test name
Test status
Simulation time 320554637 ps
CPU time 12.45 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:17:27 PM PDT 24
Peak memory 217968 kb
Host smart-77bf7321-b389-4d23-b2db-c0b18c1dddec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213610998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2213610998
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3530109166
Short name T730
Test name
Test status
Simulation time 963784609 ps
CPU time 9.82 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 217884 kb
Host smart-da6ea314-0e7d-4378-9078-a15e99a3aac5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530109166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3530109166
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3134357472
Short name T1152
Test name
Test status
Simulation time 824650549 ps
CPU time 8.62 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 217892 kb
Host smart-3bc252da-c738-4f35-99e6-1031eeb054c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134357472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3134357472
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4023777241
Short name T1190
Test name
Test status
Simulation time 214686642 ps
CPU time 7.36 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:17:32 PM PDT 24
Peak memory 217480 kb
Host smart-7abde033-0d45-42e4-9df9-13e0b9831268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023777241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4023777241
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1752494785
Short name T568
Test name
Test status
Simulation time 604694963 ps
CPU time 9.79 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:23 PM PDT 24
Peak memory 224808 kb
Host smart-d20a5016-bc66-4701-9302-713aff736bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752494785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1752494785
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2529914387
Short name T736
Test name
Test status
Simulation time 1091149748 ps
CPU time 8.15 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 225116 kb
Host smart-d75eeb2e-045a-4222-8e57-150986c9ffbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529914387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2529914387
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3128914001
Short name T1688
Test name
Test status
Simulation time 269831778 ps
CPU time 3.44 seconds
Started Mar 19 03:17:09 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 214516 kb
Host smart-7f9fca70-5792-48aa-a9ae-69693f48d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128914001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3128914001
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3165658971
Short name T381
Test name
Test status
Simulation time 77556994 ps
CPU time 2.99 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 217080 kb
Host smart-82f7703b-9382-4cbc-8c5f-c325d780449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165658971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3165658971
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1030160917
Short name T44
Test name
Test status
Simulation time 373538279 ps
CPU time 24.32 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 250712 kb
Host smart-6ac9fb50-c021-4369-a27f-bb574a441244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030160917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1030160917
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1605465328
Short name T1552
Test name
Test status
Simulation time 557390231 ps
CPU time 18.4 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:52 PM PDT 24
Peak memory 250912 kb
Host smart-6af144b2-d204-4401-9054-8549249e33c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605465328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1605465328
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.120461235
Short name T698
Test name
Test status
Simulation time 82149368 ps
CPU time 6.75 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 246652 kb
Host smart-5d67844a-c774-4d34-bc72-a6dbe2584b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120461235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.120461235
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3430299324
Short name T1521
Test name
Test status
Simulation time 776502862 ps
CPU time 7.18 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:28 PM PDT 24
Peak memory 250608 kb
Host smart-4bd7bcd1-227e-4617-8c5c-9b9a0eef784f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430299324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3430299324
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2183170613
Short name T80
Test name
Test status
Simulation time 5025460657 ps
CPU time 25.98 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:46 PM PDT 24
Peak memory 226164 kb
Host smart-beef63f1-6f5c-4cba-b9df-e8b44bdebdf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183170613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2183170613
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3466930299
Short name T1601
Test name
Test status
Simulation time 2050056218 ps
CPU time 68.04 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 246088 kb
Host smart-fea4c4b0-10ce-4c13-b691-add23d6cda04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466930299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3466930299
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1839336741
Short name T120
Test name
Test status
Simulation time 48834114990 ps
CPU time 1701.86 seconds
Started Mar 19 03:17:17 PM PDT 24
Finished Mar 19 03:45:39 PM PDT 24
Peak memory 283976 kb
Host smart-f37e1f9b-e4a2-449e-a5dd-add600dc0f6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1839336741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1839336741
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2346681243
Short name T442
Test name
Test status
Simulation time 43060613 ps
CPU time 0.87 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 212568 kb
Host smart-0ebbf9b9-8fe0-4a4e-a4af-940f0ba275c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346681243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2346681243
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.762533497
Short name T339
Test name
Test status
Simulation time 14407144 ps
CPU time 0.97 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 211556 kb
Host smart-2ebcbb44-1311-4825-959b-237b8dae3d28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762533497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.762533497
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1594729207
Short name T908
Test name
Test status
Simulation time 17191565 ps
CPU time 1.06 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:36 PM PDT 24
Peak memory 209620 kb
Host smart-71bd25c4-4f68-458e-91b5-79a9bfb32ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594729207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1594729207
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2463751846
Short name T608
Test name
Test status
Simulation time 22323325 ps
CPU time 1.2 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 209656 kb
Host smart-39b8e7c0-503d-4db5-b9fb-2351c59adcd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463751846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2463751846
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3143066196
Short name T519
Test name
Test status
Simulation time 496025830 ps
CPU time 11.97 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 225912 kb
Host smart-f305de4c-cbdd-436e-9a7f-024f3265297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143066196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3143066196
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3928310287
Short name T1079
Test name
Test status
Simulation time 255779713 ps
CPU time 9.45 seconds
Started Mar 19 03:17:17 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 225824 kb
Host smart-4d00cd45-e6f3-42d5-b617-3d9c0553484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928310287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3928310287
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1646590433
Short name T8
Test name
Test status
Simulation time 266701800 ps
CPU time 3.89 seconds
Started Mar 19 03:17:17 PM PDT 24
Finished Mar 19 03:17:21 PM PDT 24
Peak memory 209480 kb
Host smart-cedf5e0c-8d42-4f6c-b18c-99698206df7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646590433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1646590433
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2428257717
Short name T3
Test name
Test status
Simulation time 339449328 ps
CPU time 3.06 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:38 PM PDT 24
Peak memory 209464 kb
Host smart-30740589-9011-402a-a4ef-c572de5026a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428257717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2428257717
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2877308757
Short name T763
Test name
Test status
Simulation time 378634362 ps
CPU time 4.17 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:37 PM PDT 24
Peak memory 222024 kb
Host smart-0534fec3-1172-498d-aa0a-a7c221c11828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877308757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2877308757
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3875859070
Short name T623
Test name
Test status
Simulation time 244745294 ps
CPU time 1.93 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 218060 kb
Host smart-d915dc2d-aa7a-4a02-8bcd-f64c86192b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875859070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3875859070
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4082905545
Short name T1309
Test name
Test status
Simulation time 770328573 ps
CPU time 12.47 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 217876 kb
Host smart-7d26d005-db8a-45eb-8e9c-98c036f68e63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082905545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4082905545
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.692314664
Short name T1600
Test name
Test status
Simulation time 730290922 ps
CPU time 13.34 seconds
Started Mar 19 03:20:40 PM PDT 24
Finished Mar 19 03:20:53 PM PDT 24
Peak memory 226076 kb
Host smart-341b1e3f-2654-4e13-8ffd-7c45c814f3b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692314664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.692314664
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.4094258277
Short name T446
Test name
Test status
Simulation time 292604982 ps
CPU time 7.69 seconds
Started Mar 19 03:17:17 PM PDT 24
Finished Mar 19 03:17:25 PM PDT 24
Peak memory 217892 kb
Host smart-99046a83-b41d-45c4-9cb4-2ed4d7a8bb87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094258277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.4094258277
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.84805421
Short name T1304
Test name
Test status
Simulation time 2415128023 ps
CPU time 16.92 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:51 PM PDT 24
Peak memory 218080 kb
Host smart-e0b19e23-12a7-4bd3-b8a7-602bfe0dbec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84805421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_dig
est.84805421
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1153699230
Short name T1456
Test name
Test status
Simulation time 933764550 ps
CPU time 7.26 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 217860 kb
Host smart-b85c13c5-655e-476f-b97f-e9503d8deaaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153699230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1153699230
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3194614797
Short name T1175
Test name
Test status
Simulation time 2053639831 ps
CPU time 10.57 seconds
Started Mar 19 03:17:11 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 217888 kb
Host smart-a0e4f80f-7d01-4780-bb2a-0e01db86ef8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194614797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3194614797
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1678321210
Short name T1635
Test name
Test status
Simulation time 358051393 ps
CPU time 13.29 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:17:38 PM PDT 24
Peak memory 224212 kb
Host smart-95181152-6161-4bc9-9e5f-a27b1e88b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678321210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1678321210
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3285905665
Short name T867
Test name
Test status
Simulation time 915124489 ps
CPU time 8.39 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 224224 kb
Host smart-886979bc-40cd-4171-919e-70cca8d15c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285905665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3285905665
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1220587438
Short name T63
Test name
Test status
Simulation time 93176776 ps
CPU time 1.13 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:17:16 PM PDT 24
Peak memory 217676 kb
Host smart-f5e62361-f3d0-4f81-a9ab-73f090d006f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220587438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1220587438
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.427028717
Short name T487
Test name
Test status
Simulation time 60695479 ps
CPU time 1.33 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:35 PM PDT 24
Peak memory 217612 kb
Host smart-021b9691-97aa-4801-8b54-2f38b982933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427028717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.427028717
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1997733675
Short name T621
Test name
Test status
Simulation time 1186914781 ps
CPU time 29.36 seconds
Started Mar 19 03:17:14 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 248512 kb
Host smart-5179d35a-df78-4917-8e8d-13776a89a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997733675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1997733675
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2381540942
Short name T531
Test name
Test status
Simulation time 345522372 ps
CPU time 29.53 seconds
Started Mar 19 03:20:38 PM PDT 24
Finished Mar 19 03:21:08 PM PDT 24
Peak memory 250892 kb
Host smart-9a9f9f37-d6c2-4163-a25c-2e98da8bfe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381540942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2381540942
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1796393973
Short name T881
Test name
Test status
Simulation time 137420411 ps
CPU time 6.49 seconds
Started Mar 19 03:17:14 PM PDT 24
Finished Mar 19 03:17:20 PM PDT 24
Peak memory 250380 kb
Host smart-bbb62af2-1b80-4157-80ea-c17443b653d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796393973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1796393973
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.494092388
Short name T676
Test name
Test status
Simulation time 78581981 ps
CPU time 6.3 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 250796 kb
Host smart-62ff3888-b21f-448c-9ac3-65f49b183d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494092388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.494092388
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1808704411
Short name T464
Test name
Test status
Simulation time 2392423012 ps
CPU time 68.46 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:21:41 PM PDT 24
Peak memory 272892 kb
Host smart-097c7f93-2bc6-4bac-a48b-34050ce8e46a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808704411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1808704411
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3971738000
Short name T688
Test name
Test status
Simulation time 5164398064 ps
CPU time 128.17 seconds
Started Mar 19 03:17:10 PM PDT 24
Finished Mar 19 03:19:18 PM PDT 24
Peak memory 226140 kb
Host smart-3979795c-e0f6-4df9-aa75-d6bc468924df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971738000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3971738000
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.4034035801
Short name T184
Test name
Test status
Simulation time 32971323534 ps
CPU time 505.1 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:25:38 PM PDT 24
Peak memory 446748 kb
Host smart-ecd5adc9-91b8-4d6d-a937-3aebf98f61ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4034035801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.4034035801
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2039899812
Short name T435
Test name
Test status
Simulation time 12631139 ps
CPU time 0.94 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:22 PM PDT 24
Peak memory 211632 kb
Host smart-1f75461b-ac83-4023-8825-d22668ff9ebb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039899812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2039899812
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.512380936
Short name T1618
Test name
Test status
Simulation time 13452086 ps
CPU time 0.88 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 211532 kb
Host smart-c2ca99bb-6f06-4660-9773-b71ca1eaaf13
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512380936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.512380936
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2214988566
Short name T1453
Test name
Test status
Simulation time 93940707 ps
CPU time 1.18 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:38 PM PDT 24
Peak memory 209572 kb
Host smart-fdd2a638-f8f6-4e43-a844-dfab21e0daf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214988566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2214988566
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.320229952
Short name T192
Test name
Test status
Simulation time 19782680 ps
CPU time 1 seconds
Started Mar 19 03:17:18 PM PDT 24
Finished Mar 19 03:17:19 PM PDT 24
Peak memory 209580 kb
Host smart-68c49bd4-3f8d-4cbe-a073-8820b875dcb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320229952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.320229952
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1114467325
Short name T897
Test name
Test status
Simulation time 1633997851 ps
CPU time 18.03 seconds
Started Mar 19 03:20:38 PM PDT 24
Finished Mar 19 03:20:56 PM PDT 24
Peak memory 217904 kb
Host smart-aea7138e-8f93-4234-9660-c30a07cd0a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114467325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1114467325
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.414009315
Short name T1506
Test name
Test status
Simulation time 1608265467 ps
CPU time 12.13 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 217952 kb
Host smart-982d3ee0-f391-4b27-bacd-f71d5aded3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414009315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.414009315
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3270433842
Short name T1276
Test name
Test status
Simulation time 1422683984 ps
CPU time 8.62 seconds
Started Mar 19 03:20:33 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 209496 kb
Host smart-73cc0eb7-522c-4045-a438-4d4758abd1da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270433842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3270433842
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3614180316
Short name T33
Test name
Test status
Simulation time 924087273 ps
CPU time 4.12 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:17 PM PDT 24
Peak memory 209412 kb
Host smart-3d2cb0e4-b7d2-46cc-82e7-56e7813afa19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614180316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3614180316
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1029290331
Short name T914
Test name
Test status
Simulation time 59474077 ps
CPU time 2.2 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:36 PM PDT 24
Peak memory 221636 kb
Host smart-f888e58e-d605-4da3-8098-3712a94acb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029290331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1029290331
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2600955424
Short name T1626
Test name
Test status
Simulation time 21317809 ps
CPU time 1.54 seconds
Started Mar 19 03:17:15 PM PDT 24
Finished Mar 19 03:17:17 PM PDT 24
Peak memory 221260 kb
Host smart-bae92901-7851-4b01-825a-7b5fbf35b1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600955424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2600955424
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1278094578
Short name T1375
Test name
Test status
Simulation time 676410863 ps
CPU time 18.24 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:56 PM PDT 24
Peak memory 218088 kb
Host smart-a80d6995-2fac-4a5a-8c8f-588ba2e20209
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278094578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1278094578
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1461967917
Short name T1395
Test name
Test status
Simulation time 901288826 ps
CPU time 9.8 seconds
Started Mar 19 03:17:18 PM PDT 24
Finished Mar 19 03:17:28 PM PDT 24
Peak memory 217972 kb
Host smart-04b1fda1-7569-43d9-b937-62991c30930d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461967917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1461967917
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1719126014
Short name T1611
Test name
Test status
Simulation time 2497051599 ps
CPU time 13.95 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 218048 kb
Host smart-556c28f1-9230-4916-a0cf-d655dd766895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719126014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1719126014
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3495348830
Short name T189
Test name
Test status
Simulation time 452820206 ps
CPU time 10.07 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:39 PM PDT 24
Peak memory 217916 kb
Host smart-3c75e915-2ae9-4fe0-9e8c-3bf3d26face2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495348830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3495348830
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2619063139
Short name T1222
Test name
Test status
Simulation time 328400158 ps
CPU time 8.09 seconds
Started Mar 19 03:20:38 PM PDT 24
Finished Mar 19 03:20:46 PM PDT 24
Peak memory 217892 kb
Host smart-8f11e9f3-3036-4064-8386-03b52e3d7077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619063139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2619063139
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3803872351
Short name T1050
Test name
Test status
Simulation time 290691983 ps
CPU time 7.32 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:27 PM PDT 24
Peak memory 217828 kb
Host smart-c1c1bd65-0760-462d-aef7-0020bcf94f2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803872351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3803872351
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2722573833
Short name T1561
Test name
Test status
Simulation time 202209858 ps
CPU time 7.74 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:21 PM PDT 24
Peak memory 224336 kb
Host smart-f7ffe816-6b1e-4ddd-bd3b-00e02afa9d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722573833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2722573833
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.679494408
Short name T895
Test name
Test status
Simulation time 487675148 ps
CPU time 7.71 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 224556 kb
Host smart-f6780059-b1a1-44b7-8d62-381cc980db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679494408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.679494408
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2044128223
Short name T1044
Test name
Test status
Simulation time 48724156 ps
CPU time 1.86 seconds
Started Mar 19 03:20:38 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 217852 kb
Host smart-6802608f-fb8d-4ddc-af0a-e1a0b81ee22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044128223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2044128223
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.51239211
Short name T577
Test name
Test status
Simulation time 2501194872 ps
CPU time 4.1 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:18 PM PDT 24
Peak memory 214584 kb
Host smart-088da423-f261-4482-9db5-84f0cdc55cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51239211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.51239211
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1851054100
Short name T283
Test name
Test status
Simulation time 588476916 ps
CPU time 30.95 seconds
Started Mar 19 03:20:36 PM PDT 24
Finished Mar 19 03:21:07 PM PDT 24
Peak memory 250888 kb
Host smart-7ed0fceb-7c98-4ced-b080-e3fb42c87e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851054100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1851054100
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3591707017
Short name T749
Test name
Test status
Simulation time 671786879 ps
CPU time 27.48 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:49 PM PDT 24
Peak memory 250748 kb
Host smart-3780414b-77c5-4ed8-ba79-51c553ea5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591707017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3591707017
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1619345646
Short name T856
Test name
Test status
Simulation time 198165999 ps
CPU time 7.95 seconds
Started Mar 19 03:17:13 PM PDT 24
Finished Mar 19 03:17:21 PM PDT 24
Peak memory 250916 kb
Host smart-aa531d09-0ae2-4a2b-9328-fa71a2453e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619345646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1619345646
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3108748806
Short name T1535
Test name
Test status
Simulation time 69749302 ps
CPU time 6.3 seconds
Started Mar 19 03:20:36 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 250944 kb
Host smart-aa2d0e4a-d2db-4c5c-90da-5431a492b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108748806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3108748806
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2583551178
Short name T852
Test name
Test status
Simulation time 18977271431 ps
CPU time 149.01 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 283780 kb
Host smart-238b795b-d5cf-41c7-9c5a-b187392a4865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583551178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2583551178
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2611410006
Short name T945
Test name
Test status
Simulation time 3720986128 ps
CPU time 124.5 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:19:26 PM PDT 24
Peak memory 251564 kb
Host smart-9fa29339-a75e-4927-b9fb-7b85dccb3782
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611410006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2611410006
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.784693036
Short name T1636
Test name
Test status
Simulation time 15238847 ps
CPU time 0.83 seconds
Started Mar 19 03:17:12 PM PDT 24
Finished Mar 19 03:17:13 PM PDT 24
Peak memory 211536 kb
Host smart-d2c16d0d-6092-4758-8283-6d011b6a0138
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784693036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.784693036
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.811936291
Short name T345
Test name
Test status
Simulation time 11675266 ps
CPU time 1.01 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:38 PM PDT 24
Peak memory 211500 kb
Host smart-e70b0ce7-8583-484b-bcb6-715aa911b7fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811936291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.811936291
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3794523598
Short name T62
Test name
Test status
Simulation time 32243564 ps
CPU time 1.46 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:21 PM PDT 24
Peak memory 209588 kb
Host smart-ec9e4aca-fefa-4785-b3aa-3e8328e85396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794523598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3794523598
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.662274132
Short name T1615
Test name
Test status
Simulation time 66938175 ps
CPU time 1.15 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 209556 kb
Host smart-ae0242c4-0163-4591-9228-b553982909a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662274132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.662274132
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1955989316
Short name T954
Test name
Test status
Simulation time 1033421179 ps
CPU time 26.74 seconds
Started Mar 19 03:17:18 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 217936 kb
Host smart-251edbd1-1cd2-4d0e-a192-8f9f08a56c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955989316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1955989316
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.4095976536
Short name T727
Test name
Test status
Simulation time 1393849869 ps
CPU time 15.83 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:21:01 PM PDT 24
Peak memory 226080 kb
Host smart-b2f65c42-24de-4bb6-bda2-b80ed333bc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095976536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.4095976536
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1238409358
Short name T656
Test name
Test status
Simulation time 3842600282 ps
CPU time 21.85 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:40 PM PDT 24
Peak memory 209580 kb
Host smart-e5c32be9-cd63-4af1-b800-784a96d7b060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238409358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1238409358
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.171966713
Short name T1481
Test name
Test status
Simulation time 57820068 ps
CPU time 2 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:39 PM PDT 24
Peak memory 209484 kb
Host smart-b062a051-561c-4170-a03b-ee44178f882e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171966713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.171966713
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1907232044
Short name T1
Test name
Test status
Simulation time 84861877 ps
CPU time 2.75 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 217980 kb
Host smart-4b898268-161b-4113-884f-64f5a189162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907232044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1907232044
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.752033948
Short name T1442
Test name
Test status
Simulation time 217769682 ps
CPU time 1.91 seconds
Started Mar 19 03:17:27 PM PDT 24
Finished Mar 19 03:17:29 PM PDT 24
Peak memory 221660 kb
Host smart-fd905830-aaf7-413b-802f-6b52784b9f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752033948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.752033948
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2694880854
Short name T675
Test name
Test status
Simulation time 308212902 ps
CPU time 14.98 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 218860 kb
Host smart-96b11fe2-5b77-4eeb-a517-2c5432123ab1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694880854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2694880854
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3942954042
Short name T1085
Test name
Test status
Simulation time 341360810 ps
CPU time 14.93 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:38 PM PDT 24
Peak memory 225912 kb
Host smart-111d9110-7e08-4353-b3db-a37952179086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942954042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3942954042
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3060348706
Short name T1682
Test name
Test status
Simulation time 508983771 ps
CPU time 10.7 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 217964 kb
Host smart-b692b2f4-acca-442b-b14a-91c1bbe0da3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060348706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3060348706
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.448887893
Short name T251
Test name
Test status
Simulation time 1272536862 ps
CPU time 13.21 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 217832 kb
Host smart-9e46498f-c836-4700-ac75-f6e1caa6f346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448887893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.448887893
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3356690851
Short name T499
Test name
Test status
Simulation time 324304266 ps
CPU time 8.24 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:31 PM PDT 24
Peak memory 217944 kb
Host smart-90aaa254-2c0a-4616-be09-07cbd1e92bc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356690851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3356690851
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3895960424
Short name T402
Test name
Test status
Simulation time 709972776 ps
CPU time 9.47 seconds
Started Mar 19 03:20:35 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 217972 kb
Host smart-2d09b585-ad94-42ec-b0c5-e7a7a441c198
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895960424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3895960424
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3222019929
Short name T1485
Test name
Test status
Simulation time 1012495277 ps
CPU time 12.73 seconds
Started Mar 19 03:20:40 PM PDT 24
Finished Mar 19 03:20:53 PM PDT 24
Peak memory 224884 kb
Host smart-b6d4c36a-72ec-416e-af4c-17d7e34f05ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222019929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3222019929
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4261543778
Short name T1128
Test name
Test status
Simulation time 400766038 ps
CPU time 10.35 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:32 PM PDT 24
Peak memory 224892 kb
Host smart-b412c0bf-f663-4fe0-b7d8-6cd8d25f696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261543778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4261543778
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2278726438
Short name T77
Test name
Test status
Simulation time 26495997 ps
CPU time 1.34 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:24 PM PDT 24
Peak memory 213376 kb
Host smart-83fa2fb1-bd86-46b9-bec9-be43c2f07fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278726438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2278726438
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.724154644
Short name T1068
Test name
Test status
Simulation time 28611564 ps
CPU time 1.89 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:39 PM PDT 24
Peak memory 217828 kb
Host smart-1152784e-31e2-4f79-9e51-aa74a5a2d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724154644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.724154644
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3642315036
Short name T1436
Test name
Test status
Simulation time 450683358 ps
CPU time 22.46 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:21:02 PM PDT 24
Peak memory 250148 kb
Host smart-1a9a7f83-a518-445b-a543-1e66472bcbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642315036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3642315036
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3976822712
Short name T92
Test name
Test status
Simulation time 286803716 ps
CPU time 35.03 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:59 PM PDT 24
Peak memory 250944 kb
Host smart-237d4ef7-efde-4344-8569-39343cdb0e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976822712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3976822712
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2474613793
Short name T1468
Test name
Test status
Simulation time 91585478 ps
CPU time 4.59 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 222208 kb
Host smart-d9426740-bd12-4bcb-a82a-a16ea60a7f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474613793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2474613793
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2830959031
Short name T1699
Test name
Test status
Simulation time 243344439 ps
CPU time 6.86 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 242924 kb
Host smart-c31581ff-b013-4620-ad0b-e82ddaddc556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830959031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2830959031
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.790163851
Short name T713
Test name
Test status
Simulation time 3800867632 ps
CPU time 86.79 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:18:49 PM PDT 24
Peak memory 283820 kb
Host smart-d5df3fca-a0b2-4edd-9b58-70821f4bba69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790163851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.790163851
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.866865539
Short name T377
Test name
Test status
Simulation time 1392510193 ps
CPU time 24.18 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:21:03 PM PDT 24
Peak memory 246680 kb
Host smart-b504c5d7-71ad-4d96-97da-ecb443c7d0d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866865539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.866865539
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1796926706
Short name T66
Test name
Test status
Simulation time 56202214285 ps
CPU time 494.5 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:28:53 PM PDT 24
Peak memory 300304 kb
Host smart-5302d526-4ee0-474d-ab6e-d8b57e47b6c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1796926706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1796926706
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3111672380
Short name T941
Test name
Test status
Simulation time 18931985551 ps
CPU time 712.31 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:29:15 PM PDT 24
Peak memory 373116 kb
Host smart-477c6550-2551-4abd-976b-2158ca2132fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3111672380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3111672380
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.127859480
Short name T1226
Test name
Test status
Simulation time 10957449 ps
CPU time 0.86 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:23 PM PDT 24
Peak memory 211552 kb
Host smart-a6e7f97e-63d5-43b6-93b9-5ee427337c4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127859480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.127859480
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2056194700
Short name T574
Test name
Test status
Simulation time 13745087 ps
CPU time 0.86 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:38 PM PDT 24
Peak memory 211528 kb
Host smart-3ac17eb9-e5ce-4ca7-a7a7-66855ff91c75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056194700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2056194700
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1943340466
Short name T660
Test name
Test status
Simulation time 23449921 ps
CPU time 0.95 seconds
Started Mar 19 03:20:38 PM PDT 24
Finished Mar 19 03:20:39 PM PDT 24
Peak memory 209620 kb
Host smart-3e25e9cb-c79a-4b8e-817f-edbef61e9342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943340466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1943340466
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.4069729910
Short name T1094
Test name
Test status
Simulation time 35413887 ps
CPU time 0.92 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:20 PM PDT 24
Peak memory 209608 kb
Host smart-56f0dc42-bb97-4c17-a831-f6ba65d05782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069729910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4069729910
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1047818851
Short name T1497
Test name
Test status
Simulation time 3367927669 ps
CPU time 22.72 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 219032 kb
Host smart-8fabdc5a-1b2b-42ba-9778-8edb1f217694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047818851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1047818851
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.634155227
Short name T1299
Test name
Test status
Simulation time 1069962164 ps
CPU time 13.51 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 217876 kb
Host smart-6bd3ec66-a422-4a3a-8344-dfa6f24e294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634155227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.634155227
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2658418013
Short name T636
Test name
Test status
Simulation time 816720941 ps
CPU time 11.11 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:30 PM PDT 24
Peak memory 209436 kb
Host smart-fb6c8fb6-fd6d-42f9-999c-29311e737341
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658418013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2658418013
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.359850687
Short name T1293
Test name
Test status
Simulation time 344979132 ps
CPU time 5.12 seconds
Started Mar 19 03:20:36 PM PDT 24
Finished Mar 19 03:20:41 PM PDT 24
Peak memory 209428 kb
Host smart-a3bbbc13-9442-4c66-8778-ab87fe8eea0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359850687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.359850687
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2655581078
Short name T360
Test name
Test status
Simulation time 77946621 ps
CPU time 2.75 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:25 PM PDT 24
Peak memory 221716 kb
Host smart-22e57a21-371c-4c22-8a25-813c9f7efda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655581078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2655581078
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3728911907
Short name T1038
Test name
Test status
Simulation time 586429889 ps
CPU time 2.99 seconds
Started Mar 19 03:20:40 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 222052 kb
Host smart-1ed384e5-9564-4796-9054-51e6599a9ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728911907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3728911907
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1336000847
Short name T366
Test name
Test status
Simulation time 718715214 ps
CPU time 9.06 seconds
Started Mar 19 03:20:36 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 217932 kb
Host smart-e36c556c-9315-4af2-b48a-869273477575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336000847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1336000847
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1398431019
Short name T1120
Test name
Test status
Simulation time 11342133249 ps
CPU time 19.34 seconds
Started Mar 19 03:17:19 PM PDT 24
Finished Mar 19 03:17:39 PM PDT 24
Peak memory 226168 kb
Host smart-3dc7c591-2eb8-4b17-9a6b-2c4559c3d974
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398431019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1398431019
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.119463043
Short name T418
Test name
Test status
Simulation time 912939432 ps
CPU time 7.63 seconds
Started Mar 19 03:20:37 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 217940 kb
Host smart-ffc5531e-dcf6-4c4d-a4b1-381d4af79408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119463043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.119463043
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.600321556
Short name T854
Test name
Test status
Simulation time 214055157 ps
CPU time 8.2 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:30 PM PDT 24
Peak memory 217908 kb
Host smart-4f4bd8f3-51fe-4ffa-903e-949693741ab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600321556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.600321556
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2750131357
Short name T1689
Test name
Test status
Simulation time 296605397 ps
CPU time 10.73 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 217804 kb
Host smart-0a011b78-910a-4487-9cf1-2dc58d031a39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750131357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2750131357
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3924690319
Short name T1692
Test name
Test status
Simulation time 279066727 ps
CPU time 8.6 seconds
Started Mar 19 03:20:34 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 217872 kb
Host smart-fb600066-e140-4b32-a477-1bd5ea8042e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924690319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3924690319
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2476610857
Short name T1608
Test name
Test status
Simulation time 4872089819 ps
CPU time 7.65 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:30 PM PDT 24
Peak memory 225604 kb
Host smart-c0f89dbc-924d-4f86-9699-e064cd615c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476610857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2476610857
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1506585131
Short name T1398
Test name
Test status
Simulation time 45378076 ps
CPU time 2.53 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 213948 kb
Host smart-04253011-b665-413a-bd9e-cf7213b44c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506585131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1506585131
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3125170300
Short name T76
Test name
Test status
Simulation time 16609213 ps
CPU time 1.09 seconds
Started Mar 19 03:17:17 PM PDT 24
Finished Mar 19 03:17:18 PM PDT 24
Peak memory 213124 kb
Host smart-65835794-eb5f-456f-ab8d-f268e69a5bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125170300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3125170300
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2293225787
Short name T1021
Test name
Test status
Simulation time 2432198925 ps
CPU time 29.03 seconds
Started Mar 19 03:20:38 PM PDT 24
Finished Mar 19 03:21:07 PM PDT 24
Peak memory 250844 kb
Host smart-3adc972d-76aa-4cf6-8e81-00e1314d0e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293225787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2293225787
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3181021328
Short name T1144
Test name
Test status
Simulation time 3315377371 ps
CPU time 25.36 seconds
Started Mar 19 03:17:26 PM PDT 24
Finished Mar 19 03:17:51 PM PDT 24
Peak memory 250868 kb
Host smart-722e5b9b-419a-4891-a422-639ee30e5ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181021328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3181021328
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2723857111
Short name T83
Test name
Test status
Simulation time 127591381 ps
CPU time 4.35 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 226384 kb
Host smart-0ef461a1-128c-458e-a2d2-bb47486aa993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723857111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2723857111
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3261824476
Short name T96
Test name
Test status
Simulation time 130260977 ps
CPU time 3.68 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 217956 kb
Host smart-b9e2dd37-004c-4305-b7a6-c5a7e0156b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261824476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3261824476
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1991002005
Short name T1344
Test name
Test status
Simulation time 7879056991 ps
CPU time 199.12 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:23:59 PM PDT 24
Peak memory 273376 kb
Host smart-9f782169-642b-47d8-9129-45ee096ddbff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991002005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1991002005
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2714896813
Short name T1332
Test name
Test status
Simulation time 828061025 ps
CPU time 32.65 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:55 PM PDT 24
Peak memory 216388 kb
Host smart-93a2de9e-e504-48fa-91a8-708c9fc40d10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714896813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2714896813
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1147772651
Short name T522
Test name
Test status
Simulation time 55760819 ps
CPU time 0.84 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:21 PM PDT 24
Peak memory 211584 kb
Host smart-77693a77-b8f6-41f6-9fe1-b0c9bed3e23b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147772651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1147772651
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4137353786
Short name T393
Test name
Test status
Simulation time 76916996 ps
CPU time 0.84 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:20:40 PM PDT 24
Peak memory 211492 kb
Host smart-138a92a5-7543-4748-8cef-813f1ed28dba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137353786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4137353786
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2238670979
Short name T571
Test name
Test status
Simulation time 161045930 ps
CPU time 0.94 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 209620 kb
Host smart-1c4fdfad-bb62-44c3-9a19-42e696550031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238670979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2238670979
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3745567343
Short name T471
Test name
Test status
Simulation time 315484711 ps
CPU time 1.07 seconds
Started Mar 19 03:15:47 PM PDT 24
Finished Mar 19 03:15:48 PM PDT 24
Peak memory 209612 kb
Host smart-d58a2daf-783d-4d07-a33e-d63d87871800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745567343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3745567343
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3261624034
Short name T235
Test name
Test status
Simulation time 14551160 ps
CPU time 0.8 seconds
Started Mar 19 03:19:05 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 209336 kb
Host smart-83de0695-6696-47bb-b094-89e6c7da8838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261624034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3261624034
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3141762974
Short name T892
Test name
Test status
Simulation time 308522298 ps
CPU time 11.57 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:28 PM PDT 24
Peak memory 217960 kb
Host smart-d335dcac-623f-42ba-a5a1-9b873c618475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141762974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3141762974
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3208409434
Short name T722
Test name
Test status
Simulation time 1147976854 ps
CPU time 10.59 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 217972 kb
Host smart-512970be-1e6c-4f1f-95c3-a7d76f9172d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208409434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3208409434
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1033791387
Short name T569
Test name
Test status
Simulation time 843576124 ps
CPU time 3.5 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:15:41 PM PDT 24
Peak memory 209452 kb
Host smart-88c4eea8-f137-4633-b1a5-4671cf8f5fce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033791387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1033791387
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3695097720
Short name T815
Test name
Test status
Simulation time 383949866 ps
CPU time 9.28 seconds
Started Mar 19 03:18:59 PM PDT 24
Finished Mar 19 03:19:08 PM PDT 24
Peak memory 209452 kb
Host smart-779704a4-8bf2-465d-bc24-a034a8848362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695097720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3695097720
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4001628150
Short name T610
Test name
Test status
Simulation time 8052965686 ps
CPU time 58.04 seconds
Started Mar 19 03:19:03 PM PDT 24
Finished Mar 19 03:20:01 PM PDT 24
Peak memory 218972 kb
Host smart-1c8a5b9d-eaca-4c01-baf3-a39e6c8a84a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001628150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4001628150
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.694735889
Short name T1132
Test name
Test status
Simulation time 6231754260 ps
CPU time 29 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 218512 kb
Host smart-b02a2266-7e5e-4227-ab61-ea9eb377b26e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694735889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.694735889
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1826722034
Short name T681
Test name
Test status
Simulation time 1124639328 ps
CPU time 11.87 seconds
Started Mar 19 03:19:04 PM PDT 24
Finished Mar 19 03:19:16 PM PDT 24
Peak memory 217280 kb
Host smart-3aabd475-387d-4a60-b89c-ef708ff52f41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826722034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
826722034
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.437583634
Short name T1147
Test name
Test status
Simulation time 706975837 ps
CPU time 9.54 seconds
Started Mar 19 03:15:38 PM PDT 24
Finished Mar 19 03:15:48 PM PDT 24
Peak memory 217700 kb
Host smart-f0bbd5ad-7c0f-47ec-8ed0-1c9cc6147d62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437583634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.437583634
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1570073108
Short name T827
Test name
Test status
Simulation time 217374080 ps
CPU time 7.26 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 217820 kb
Host smart-82257301-d546-48bd-936f-1e49a1d4af18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570073108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1570073108
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3118430905
Short name T877
Test name
Test status
Simulation time 269826805 ps
CPU time 8.87 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 217936 kb
Host smart-d0f14a59-32d5-4219-a166-a3407678dd5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118430905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3118430905
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3904596584
Short name T760
Test name
Test status
Simulation time 3778852424 ps
CPU time 14.13 seconds
Started Mar 19 03:19:08 PM PDT 24
Finished Mar 19 03:19:23 PM PDT 24
Peak memory 213816 kb
Host smart-6f9fd029-7d8c-4fa7-ae82-9955e8c92576
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904596584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3904596584
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.773310849
Short name T1623
Test name
Test status
Simulation time 4590945168 ps
CPU time 23.04 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:16:00 PM PDT 24
Peak memory 213892 kb
Host smart-fc2f67bc-c765-4c6b-98ee-21c52ec160f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773310849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.773310849
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1431221633
Short name T1172
Test name
Test status
Simulation time 1335555003 ps
CPU time 5.53 seconds
Started Mar 19 03:19:05 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 213400 kb
Host smart-39ac8ded-76c8-4366-a156-95e9d25a2df8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431221633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1431221633
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2369584333
Short name T1301
Test name
Test status
Simulation time 1719962269 ps
CPU time 6.54 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:41 PM PDT 24
Peak memory 213592 kb
Host smart-1377001f-2162-4350-b29d-653ab906f680
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369584333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2369584333
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4001334280
Short name T287
Test name
Test status
Simulation time 2454368459 ps
CPU time 42.82 seconds
Started Mar 19 03:19:16 PM PDT 24
Finished Mar 19 03:19:59 PM PDT 24
Peak memory 246804 kb
Host smart-fcfad435-ff43-4cc1-92b0-e9733f657c8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001334280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.4001334280
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.63187460
Short name T1251
Test name
Test status
Simulation time 2030407635 ps
CPU time 32.74 seconds
Started Mar 19 03:15:32 PM PDT 24
Finished Mar 19 03:16:05 PM PDT 24
Peak memory 251284 kb
Host smart-d626b3ef-648a-4332-afc2-9f7f91c4a8e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63187460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
state_failure.63187460
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3551457918
Short name T90
Test name
Test status
Simulation time 287034223 ps
CPU time 9.78 seconds
Started Mar 19 03:19:01 PM PDT 24
Finished Mar 19 03:19:11 PM PDT 24
Peak memory 221708 kb
Host smart-0c0c52a1-6bf4-4e16-b2b7-8aca822a2379
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551457918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3551457918
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.929957270
Short name T687
Test name
Test status
Simulation time 1028069912 ps
CPU time 19.02 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:53 PM PDT 24
Peak memory 250956 kb
Host smart-d24eaf0c-e6a3-47f6-9682-d8c5399a26ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929957270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.929957270
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2908860267
Short name T263
Test name
Test status
Simulation time 85775595 ps
CPU time 2.5 seconds
Started Mar 19 03:15:33 PM PDT 24
Finished Mar 19 03:15:36 PM PDT 24
Peak memory 221864 kb
Host smart-5afe95c2-13db-4d4a-84d6-38847c5e6aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908860267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2908860267
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3754527257
Short name T444
Test name
Test status
Simulation time 40207023 ps
CPU time 2.21 seconds
Started Mar 19 03:19:13 PM PDT 24
Finished Mar 19 03:19:16 PM PDT 24
Peak memory 221784 kb
Host smart-a59c1c84-6d80-4001-909a-b4d7f9d04736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754527257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3754527257
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2387999607
Short name T843
Test name
Test status
Simulation time 1555994470 ps
CPU time 26.5 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 214488 kb
Host smart-dac141b1-17b9-40b4-8358-8346c7e591ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387999607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2387999607
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4222505693
Short name T201
Test name
Test status
Simulation time 356954095 ps
CPU time 12.91 seconds
Started Mar 19 03:15:35 PM PDT 24
Finished Mar 19 03:15:48 PM PDT 24
Peak memory 214364 kb
Host smart-7a04b115-ed4f-478a-a9de-ccaf16e8f896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222505693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4222505693
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.136129507
Short name T48
Test name
Test status
Simulation time 1086630800 ps
CPU time 24.45 seconds
Started Mar 19 03:19:05 PM PDT 24
Finished Mar 19 03:19:29 PM PDT 24
Peak memory 269332 kb
Host smart-58201d22-becf-4d7a-a1c0-c4314d9d4148
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136129507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.136129507
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.374521752
Short name T103
Test name
Test status
Simulation time 493440180 ps
CPU time 24.87 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:14 PM PDT 24
Peak memory 269600 kb
Host smart-1eaf418a-54a1-4db0-9e3a-dabae5e81623
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374521752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.374521752
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.111273517
Short name T277
Test name
Test status
Simulation time 1812200799 ps
CPU time 13.26 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:15:50 PM PDT 24
Peak memory 226064 kb
Host smart-07103662-6850-4726-b877-1b1ce5df3780
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111273517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.111273517
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3045274267
Short name T1686
Test name
Test status
Simulation time 3671907249 ps
CPU time 22.39 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:19:32 PM PDT 24
Peak memory 226192 kb
Host smart-032e13ef-e0ca-4e11-98c0-7923bc7a429e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045274267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3045274267
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1826312266
Short name T831
Test name
Test status
Simulation time 1002776021 ps
CPU time 11.32 seconds
Started Mar 19 03:15:48 PM PDT 24
Finished Mar 19 03:16:00 PM PDT 24
Peak memory 217972 kb
Host smart-1767a24e-0744-428b-972b-c6122f15fae2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826312266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1826312266
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2170458930
Short name T927
Test name
Test status
Simulation time 388362659 ps
CPU time 10.59 seconds
Started Mar 19 03:19:11 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 217928 kb
Host smart-abc854b7-705f-4e81-91a4-6efdae86beb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170458930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2170458930
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3377503044
Short name T578
Test name
Test status
Simulation time 490674351 ps
CPU time 10.78 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:19:13 PM PDT 24
Peak memory 217940 kb
Host smart-d6938e6e-1317-4d2b-bc0d-e61afa8bd08d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377503044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
377503044
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3290388058
Short name T1619
Test name
Test status
Simulation time 241617310 ps
CPU time 9.44 seconds
Started Mar 19 03:15:34 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 226072 kb
Host smart-2a75f755-ec23-47f8-a554-4c621c0e73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290388058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3290388058
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3853013811
Short name T1117
Test name
Test status
Simulation time 228503076 ps
CPU time 9.38 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:19:13 PM PDT 24
Peak memory 224816 kb
Host smart-d6e6552d-e1c6-42e0-a838-e03da0f504a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853013811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3853013811
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3411693972
Short name T534
Test name
Test status
Simulation time 26328138 ps
CPU time 1.88 seconds
Started Mar 19 03:18:58 PM PDT 24
Finished Mar 19 03:19:00 PM PDT 24
Peak memory 213636 kb
Host smart-9c1e1a2f-2a3a-439c-81d7-03d3e45381d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411693972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3411693972
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3455661115
Short name T834
Test name
Test status
Simulation time 176144308 ps
CPU time 3.04 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:15:40 PM PDT 24
Peak memory 217800 kb
Host smart-e3da850e-4cb9-42e4-855d-754102c0a74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455661115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3455661115
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3032137114
Short name T750
Test name
Test status
Simulation time 266577947 ps
CPU time 25.6 seconds
Started Mar 19 03:19:01 PM PDT 24
Finished Mar 19 03:19:28 PM PDT 24
Peak memory 250916 kb
Host smart-a1a383be-fc60-4ff3-a1af-938daa6b6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032137114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3032137114
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.369059583
Short name T876
Test name
Test status
Simulation time 820847313 ps
CPU time 35.24 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:16:12 PM PDT 24
Peak memory 250948 kb
Host smart-37bb1cce-d564-42fd-a6aa-556741154416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369059583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.369059583
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.46169387
Short name T624
Test name
Test status
Simulation time 114414714 ps
CPU time 7.52 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:15:45 PM PDT 24
Peak memory 250424 kb
Host smart-68fddbfa-3998-41f8-825b-bc8288b43631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46169387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.46169387
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.584061358
Short name T1329
Test name
Test status
Simulation time 986386220 ps
CPU time 8.4 seconds
Started Mar 19 03:19:12 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 242768 kb
Host smart-c1cbf93c-da63-418d-a931-6cbd1a1dba94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584061358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.584061358
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.125731854
Short name T1431
Test name
Test status
Simulation time 3080185800 ps
CPU time 49.13 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:16:40 PM PDT 24
Peak memory 250972 kb
Host smart-1b5e18e1-6e80-4913-9d48-02bad6797fd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125731854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.125731854
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1741673150
Short name T450
Test name
Test status
Simulation time 2887823170 ps
CPU time 89.81 seconds
Started Mar 19 03:19:12 PM PDT 24
Finished Mar 19 03:20:42 PM PDT 24
Peak memory 271508 kb
Host smart-b0e9bab1-4d9a-40ea-bbb4-25d29a3fb185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741673150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1741673150
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.289799776
Short name T34
Test name
Test status
Simulation time 535410519904 ps
CPU time 1044.93 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:33:16 PM PDT 24
Peak memory 710052 kb
Host smart-de68b4fe-a5ce-4b79-8db3-edbfb2b049d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=289799776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.289799776
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.526606736
Short name T167
Test name
Test status
Simulation time 41399799290 ps
CPU time 396.91 seconds
Started Mar 19 03:19:06 PM PDT 24
Finished Mar 19 03:25:43 PM PDT 24
Peak memory 279448 kb
Host smart-da2c7de6-273c-4d1d-b54f-f40bdccb0747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=526606736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.526606736
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.367020153
Short name T706
Test name
Test status
Simulation time 38958810 ps
CPU time 0.87 seconds
Started Mar 19 03:19:04 PM PDT 24
Finished Mar 19 03:19:05 PM PDT 24
Peak memory 212568 kb
Host smart-88b6c04f-3528-4baa-b358-4c5c4c4df397
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367020153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.367020153
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4254704849
Short name T909
Test name
Test status
Simulation time 12010398 ps
CPU time 0.88 seconds
Started Mar 19 03:15:37 PM PDT 24
Finished Mar 19 03:15:38 PM PDT 24
Peak memory 211572 kb
Host smart-794b1dd7-d6df-4239-84b9-7a15c29febab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254704849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4254704849
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1090329897
Short name T986
Test name
Test status
Simulation time 191927649 ps
CPU time 0.86 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:23 PM PDT 24
Peak memory 209560 kb
Host smart-730fd006-d153-42bb-9f38-07cbe98ad137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090329897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1090329897
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2772707768
Short name T1246
Test name
Test status
Simulation time 40727889 ps
CPU time 0.97 seconds
Started Mar 19 03:20:55 PM PDT 24
Finished Mar 19 03:20:56 PM PDT 24
Peak memory 209556 kb
Host smart-ba6d1478-fa5a-466e-8954-183221e1141b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772707768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2772707768
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1077575712
Short name T36
Test name
Test status
Simulation time 1644283836 ps
CPU time 14.57 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 226040 kb
Host smart-4f0fa9f6-ea8f-4d94-83a6-701eb9f4821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077575712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1077575712
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.227866215
Short name T13
Test name
Test status
Simulation time 553900021 ps
CPU time 12.27 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:56 PM PDT 24
Peak memory 217936 kb
Host smart-ed493bb6-2da4-4706-8417-4294a8d7fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227866215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.227866215
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1227350118
Short name T61
Test name
Test status
Simulation time 177038612 ps
CPU time 1.7 seconds
Started Mar 19 03:20:43 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 209484 kb
Host smart-3ec48693-3897-46e5-8400-578c872de512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227350118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1227350118
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.743214559
Short name T1520
Test name
Test status
Simulation time 230095152 ps
CPU time 6.28 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:29 PM PDT 24
Peak memory 209464 kb
Host smart-19d80ce2-3977-4998-8b25-69c0eb07f38a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743214559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.743214559
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3875027610
Short name T988
Test name
Test status
Simulation time 179937643 ps
CPU time 4.15 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:36 PM PDT 24
Peak memory 222068 kb
Host smart-10a4b420-7834-43c9-aec0-9fa25ffdb892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875027610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3875027610
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.4259447490
Short name T1663
Test name
Test status
Simulation time 126047005 ps
CPU time 2.91 seconds
Started Mar 19 03:20:49 PM PDT 24
Finished Mar 19 03:20:52 PM PDT 24
Peak memory 221824 kb
Host smart-9360c576-b868-49f0-b1df-c7cf3c490cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259447490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.4259447490
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2980561898
Short name T607
Test name
Test status
Simulation time 607158220 ps
CPU time 10.33 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:33 PM PDT 24
Peak memory 226124 kb
Host smart-0b216c34-c3d6-4c25-b31f-9d4406c890a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980561898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2980561898
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.4101321423
Short name T37
Test name
Test status
Simulation time 313630308 ps
CPU time 13.82 seconds
Started Mar 19 03:20:43 PM PDT 24
Finished Mar 19 03:20:57 PM PDT 24
Peak memory 218924 kb
Host smart-56f55e49-cb78-4c94-b5da-ee49f22043c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101321423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.4101321423
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1225131632
Short name T1252
Test name
Test status
Simulation time 291767531 ps
CPU time 10.2 seconds
Started Mar 19 03:17:22 PM PDT 24
Finished Mar 19 03:17:33 PM PDT 24
Peak memory 217816 kb
Host smart-78a7b6fa-e759-48e8-8d77-6687dbb51142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225131632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1225131632
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.23089820
Short name T587
Test name
Test status
Simulation time 778903593 ps
CPU time 22.45 seconds
Started Mar 19 03:20:42 PM PDT 24
Finished Mar 19 03:21:05 PM PDT 24
Peak memory 217940 kb
Host smart-29e3c3ff-033e-4fd1-8e5c-7701cca0337f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23089820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_dig
est.23089820
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2258891464
Short name T1422
Test name
Test status
Simulation time 742926795 ps
CPU time 12.58 seconds
Started Mar 19 03:20:53 PM PDT 24
Finished Mar 19 03:21:06 PM PDT 24
Peak memory 217884 kb
Host smart-4e86385a-bf86-4714-9eb5-6fae97b16011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258891464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2258891464
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4069248367
Short name T579
Test name
Test status
Simulation time 1163840346 ps
CPU time 15.4 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:17:39 PM PDT 24
Peak memory 217880 kb
Host smart-76f05eec-0635-43c4-bb1e-12d7f4f07bb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069248367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4069248367
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1901015206
Short name T1047
Test name
Test status
Simulation time 980129802 ps
CPU time 6.18 seconds
Started Mar 19 03:20:48 PM PDT 24
Finished Mar 19 03:20:54 PM PDT 24
Peak memory 224864 kb
Host smart-50cbce1e-cd75-448b-a2ed-6c79e8029fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901015206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1901015206
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3947858897
Short name T1173
Test name
Test status
Simulation time 314505494 ps
CPU time 11.48 seconds
Started Mar 19 03:17:21 PM PDT 24
Finished Mar 19 03:17:32 PM PDT 24
Peak memory 226072 kb
Host smart-44c213fc-1196-463c-80e7-a86d6e92cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947858897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3947858897
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1912198088
Short name T1411
Test name
Test status
Simulation time 176546687 ps
CPU time 5.52 seconds
Started Mar 19 03:20:39 PM PDT 24
Finished Mar 19 03:20:45 PM PDT 24
Peak memory 214388 kb
Host smart-07bd583a-1d3b-41db-83a9-b3d1debe1a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912198088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1912198088
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4267379067
Short name T59
Test name
Test status
Simulation time 32986421 ps
CPU time 1.56 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:32 PM PDT 24
Peak memory 213500 kb
Host smart-07534c88-5a57-4ee3-989d-6ac05a4e66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267379067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4267379067
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3113016400
Short name T504
Test name
Test status
Simulation time 639953834 ps
CPU time 25.62 seconds
Started Mar 19 03:20:50 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 250968 kb
Host smart-b06beba9-be0d-483b-bb95-8f0001a057e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113016400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3113016400
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3518779011
Short name T747
Test name
Test status
Simulation time 273584723 ps
CPU time 28.71 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:48 PM PDT 24
Peak memory 248456 kb
Host smart-070fb0fe-cfef-47aa-8873-8142d5b648a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518779011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3518779011
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.609636135
Short name T957
Test name
Test status
Simulation time 351326955 ps
CPU time 8.6 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:06 PM PDT 24
Peak memory 250972 kb
Host smart-33d5e193-0aa3-4309-8ca7-9fed7f52aa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609636135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.609636135
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.987110082
Short name T484
Test name
Test status
Simulation time 111788484 ps
CPU time 3.46 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 226364 kb
Host smart-56a1baaf-6e49-42f2-b4cd-0b74c2fc99ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987110082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.987110082
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1962655412
Short name T1534
Test name
Test status
Simulation time 52918529967 ps
CPU time 195.39 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:24:01 PM PDT 24
Peak memory 270304 kb
Host smart-5e8b6bb4-d393-4984-a9f5-51a2ec3a65ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962655412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1962655412
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3651698677
Short name T818
Test name
Test status
Simulation time 40390886973 ps
CPU time 78.42 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:18:42 PM PDT 24
Peak memory 251060 kb
Host smart-c343cacb-0989-4d20-970e-c9c08c152fe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651698677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3651698677
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.793448487
Short name T118
Test name
Test status
Simulation time 13917090599 ps
CPU time 512.35 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:29:17 PM PDT 24
Peak memory 405800 kb
Host smart-972ea0c3-1bb9-4fd8-9781-5c20397054ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=793448487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.793448487
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1469606144
Short name T1281
Test name
Test status
Simulation time 17175115 ps
CPU time 1 seconds
Started Mar 19 03:20:54 PM PDT 24
Finished Mar 19 03:20:56 PM PDT 24
Peak memory 212604 kb
Host smart-f4b378ca-a4a6-4fce-8632-38fd66c22269
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469606144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1469606144
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2112654928
Short name T480
Test name
Test status
Simulation time 42769030 ps
CPU time 1.01 seconds
Started Mar 19 03:17:24 PM PDT 24
Finished Mar 19 03:17:26 PM PDT 24
Peak memory 211552 kb
Host smart-26afd49d-2e03-48ea-8a23-b084ad3c85dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112654928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2112654928
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1353592221
Short name T593
Test name
Test status
Simulation time 39373670 ps
CPU time 1.01 seconds
Started Mar 19 03:20:48 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 209608 kb
Host smart-1a347972-e07a-4da8-a7fb-8f9dff30f1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353592221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1353592221
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.4253927590
Short name T68
Test name
Test status
Simulation time 17073101 ps
CPU time 1.01 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 209620 kb
Host smart-33fdf469-f1c9-4640-97e2-ca30f064e9db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253927590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.4253927590
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2085179208
Short name T1087
Test name
Test status
Simulation time 596444482 ps
CPU time 14.58 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:21:00 PM PDT 24
Peak memory 217936 kb
Host smart-327b5590-1629-4f74-9e63-cabbd5ee4632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085179208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2085179208
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3725879453
Short name T398
Test name
Test status
Simulation time 910666123 ps
CPU time 13.32 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 217960 kb
Host smart-8192916f-10fd-4ef3-bc63-9619048aefef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725879453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3725879453
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3705308093
Short name T1349
Test name
Test status
Simulation time 696259548 ps
CPU time 2.99 seconds
Started Mar 19 03:20:53 PM PDT 24
Finished Mar 19 03:20:57 PM PDT 24
Peak memory 209508 kb
Host smart-b7855eb8-ecfa-47bd-9615-5a2b321773d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705308093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3705308093
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.904379374
Short name T875
Test name
Test status
Simulation time 2305624040 ps
CPU time 6.33 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:29 PM PDT 24
Peak memory 209560 kb
Host smart-3fbe583e-54f1-4e5e-b3f7-4be4fa4b8623
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904379374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.904379374
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2786804090
Short name T395
Test name
Test status
Simulation time 152214599 ps
CPU time 2.54 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 221736 kb
Host smart-08e2a3a2-d6d5-4a38-a9db-894fd9d2cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786804090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2786804090
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.644653462
Short name T789
Test name
Test status
Simulation time 30171387 ps
CPU time 2.21 seconds
Started Mar 19 03:20:53 PM PDT 24
Finished Mar 19 03:20:55 PM PDT 24
Peak memory 218044 kb
Host smart-94bcfc7e-8519-4fa6-8815-2e2fe33c63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644653462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.644653462
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2929297875
Short name T1250
Test name
Test status
Simulation time 1287252822 ps
CPU time 10.01 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:40 PM PDT 24
Peak memory 226060 kb
Host smart-3293b296-2a2b-4a98-807f-c0ff56efeacd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929297875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2929297875
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3412153588
Short name T1483
Test name
Test status
Simulation time 2594734017 ps
CPU time 10.53 seconds
Started Mar 19 03:20:52 PM PDT 24
Finished Mar 19 03:21:03 PM PDT 24
Peak memory 219260 kb
Host smart-ff2ad6f8-16d5-4476-a57d-add39053dc87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412153588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3412153588
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.132754369
Short name T822
Test name
Test status
Simulation time 12611088529 ps
CPU time 22.14 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:54 PM PDT 24
Peak memory 217988 kb
Host smart-a8b58f16-27a5-4eac-bbe2-d4c303055ff2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132754369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.132754369
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2313078569
Short name T599
Test name
Test status
Simulation time 762937387 ps
CPU time 12.2 seconds
Started Mar 19 03:20:43 PM PDT 24
Finished Mar 19 03:20:55 PM PDT 24
Peak memory 217872 kb
Host smart-745c9b6f-a001-4616-983b-9e59fc50ca24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313078569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2313078569
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1397625439
Short name T1574
Test name
Test status
Simulation time 291109909 ps
CPU time 10.85 seconds
Started Mar 19 03:17:20 PM PDT 24
Finished Mar 19 03:17:31 PM PDT 24
Peak memory 217884 kb
Host smart-a1af67a8-4e51-4a77-89c6-9d09c5f5e601
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397625439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1397625439
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3385447018
Short name T495
Test name
Test status
Simulation time 195799328 ps
CPU time 8.13 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:53 PM PDT 24
Peak memory 217864 kb
Host smart-7b9561e5-0a84-4655-8331-ee7d2f8c6009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385447018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3385447018
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.352420989
Short name T797
Test name
Test status
Simulation time 551966051 ps
CPU time 12.85 seconds
Started Mar 19 03:20:46 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 225384 kb
Host smart-4333d93b-aade-492d-8771-b4a1edd86470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352420989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.352420989
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.4183245501
Short name T1607
Test name
Test status
Simulation time 361661664 ps
CPU time 13.61 seconds
Started Mar 19 03:17:23 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 225788 kb
Host smart-74001762-9cec-475b-adf6-a31174b8d17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183245501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.4183245501
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1465860216
Short name T1204
Test name
Test status
Simulation time 81799829 ps
CPU time 4.77 seconds
Started Mar 19 03:20:56 PM PDT 24
Finished Mar 19 03:21:01 PM PDT 24
Peak memory 217668 kb
Host smart-9141b86c-f769-4385-b928-11fe227f0b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465860216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1465860216
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.605518889
Short name T864
Test name
Test status
Simulation time 110894162 ps
CPU time 2.76 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:32 PM PDT 24
Peak memory 217880 kb
Host smart-a20792c1-735a-4d70-9585-cd51c824920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605518889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.605518889
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2608826988
Short name T1031
Test name
Test status
Simulation time 341236191 ps
CPU time 28.2 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:57 PM PDT 24
Peak memory 250968 kb
Host smart-2dd6d81b-11ef-443e-a89c-a461c86b96f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608826988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2608826988
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.931888402
Short name T629
Test name
Test status
Simulation time 305538992 ps
CPU time 25.39 seconds
Started Mar 19 03:20:42 PM PDT 24
Finished Mar 19 03:21:08 PM PDT 24
Peak memory 250940 kb
Host smart-c7d08ea7-e93e-4d7a-b6c3-e43ab165a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931888402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.931888402
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1069595738
Short name T1597
Test name
Test status
Simulation time 772126429 ps
CPU time 6.1 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:51 PM PDT 24
Peak memory 250932 kb
Host smart-451eba51-2413-4a36-aef9-9be1443b9802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069595738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1069595738
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1197332887
Short name T572
Test name
Test status
Simulation time 240705494 ps
CPU time 7.39 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 248588 kb
Host smart-c744ddcf-6150-4b72-9226-7fbc7d763382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197332887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1197332887
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.345504553
Short name T1139
Test name
Test status
Simulation time 4690686943 ps
CPU time 113.36 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:19:28 PM PDT 24
Peak memory 282132 kb
Host smart-0bb1fae8-7987-4133-8899-6092a2b18588
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345504553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.345504553
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.955092380
Short name T440
Test name
Test status
Simulation time 4065657960 ps
CPU time 40.98 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 246632 kb
Host smart-496e550c-e362-4c2a-80c7-e03b40085a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955092380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.955092380
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1441983813
Short name T1072
Test name
Test status
Simulation time 31381508 ps
CPU time 0.84 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 211528 kb
Host smart-10ae19b7-65c3-4852-80c5-8533a759c0e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441983813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1441983813
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.283644234
Short name T254
Test name
Test status
Simulation time 13784408 ps
CPU time 1.07 seconds
Started Mar 19 03:17:32 PM PDT 24
Finished Mar 19 03:17:33 PM PDT 24
Peak memory 211576 kb
Host smart-6e8ba8eb-c608-435a-aca1-60000435b9a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283644234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.283644234
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2058134352
Short name T69
Test name
Test status
Simulation time 17646197 ps
CPU time 1.14 seconds
Started Mar 19 03:17:39 PM PDT 24
Finished Mar 19 03:17:41 PM PDT 24
Peak memory 209608 kb
Host smart-708bebd6-b96e-4807-8551-aa675e7fd66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058134352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2058134352
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3030919390
Short name T267
Test name
Test status
Simulation time 17747334 ps
CPU time 1.09 seconds
Started Mar 19 03:20:53 PM PDT 24
Finished Mar 19 03:20:54 PM PDT 24
Peak memory 209856 kb
Host smart-3e2f2063-f6ac-469b-942e-4ecbbd1c9d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030919390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3030919390
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3634896381
Short name T1236
Test name
Test status
Simulation time 1992660749 ps
CPU time 18.9 seconds
Started Mar 19 03:20:51 PM PDT 24
Finished Mar 19 03:21:10 PM PDT 24
Peak memory 217944 kb
Host smart-3e35502d-bebe-47d5-ac6a-db6293764997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634896381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3634896381
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3893313709
Short name T801
Test name
Test status
Simulation time 810676788 ps
CPU time 13.71 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 217892 kb
Host smart-34d25aee-f944-4c61-91c7-d1e6d5c397ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893313709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3893313709
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2887157520
Short name T482
Test name
Test status
Simulation time 97514968 ps
CPU time 1.67 seconds
Started Mar 19 03:17:32 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 209476 kb
Host smart-625d13ab-7257-48df-9fe0-a1dd7083d40e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887157520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2887157520
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3772469670
Short name T1145
Test name
Test status
Simulation time 483079318 ps
CPU time 7.46 seconds
Started Mar 19 03:20:50 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 209468 kb
Host smart-3ce80a09-8b3f-4558-aee9-f9b42349adf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772469670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3772469670
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2450752393
Short name T453
Test name
Test status
Simulation time 55444518 ps
CPU time 2.99 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:33 PM PDT 24
Peak memory 221860 kb
Host smart-bc4d62fc-6842-4b60-baf0-1f8454772f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450752393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2450752393
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3064205465
Short name T338
Test name
Test status
Simulation time 37982758 ps
CPU time 2.3 seconds
Started Mar 19 03:21:00 PM PDT 24
Finished Mar 19 03:21:03 PM PDT 24
Peak memory 218016 kb
Host smart-46cd1e8e-6261-42f1-92d4-f07cca8ab432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064205465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3064205465
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1689443636
Short name T596
Test name
Test status
Simulation time 3665490794 ps
CPU time 15.02 seconds
Started Mar 19 03:20:43 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 226168 kb
Host smart-7e343e74-5baa-4d5d-b8ad-0b76afd4ca5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689443636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1689443636
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.327816781
Short name T396
Test name
Test status
Simulation time 570473592 ps
CPU time 13.59 seconds
Started Mar 19 03:17:35 PM PDT 24
Finished Mar 19 03:17:49 PM PDT 24
Peak memory 218504 kb
Host smart-8ce56179-1db7-4171-89fd-905bac1cdc35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327816781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.327816781
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3623400606
Short name T861
Test name
Test status
Simulation time 415897848 ps
CPU time 15.79 seconds
Started Mar 19 03:20:48 PM PDT 24
Finished Mar 19 03:21:04 PM PDT 24
Peak memory 217836 kb
Host smart-249bf359-78ca-4ca2-b473-098a9439137d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623400606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3623400606
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.4054331562
Short name T343
Test name
Test status
Simulation time 1650728252 ps
CPU time 8.38 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:38 PM PDT 24
Peak memory 217952 kb
Host smart-3c73c1b5-6b1b-4f68-bfc0-2a71acacc972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054331562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.4054331562
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2392174980
Short name T1133
Test name
Test status
Simulation time 339485746 ps
CPU time 6.39 seconds
Started Mar 19 03:20:51 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 217908 kb
Host smart-c3968973-b396-44a0-8788-82f752cf7f6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392174980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2392174980
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.378179715
Short name T1059
Test name
Test status
Simulation time 315748507 ps
CPU time 8.36 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 217836 kb
Host smart-8f34d143-e16e-4673-9d33-f5af7ec5727c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378179715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.378179715
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2772820972
Short name T1515
Test name
Test status
Simulation time 907144160 ps
CPU time 9.56 seconds
Started Mar 19 03:17:32 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 224588 kb
Host smart-4cf4f2cf-6775-443d-b296-4eb10b140c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772820972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2772820972
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.4109178533
Short name T1318
Test name
Test status
Simulation time 1445967679 ps
CPU time 8.26 seconds
Started Mar 19 03:20:53 PM PDT 24
Finished Mar 19 03:21:01 PM PDT 24
Peak memory 225316 kb
Host smart-9d21b6f3-6f60-4cc3-adff-c4ff8322fdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109178533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.4109178533
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.296625964
Short name T1290
Test name
Test status
Simulation time 25956216 ps
CPU time 1.8 seconds
Started Mar 19 03:17:27 PM PDT 24
Finished Mar 19 03:17:30 PM PDT 24
Peak memory 213652 kb
Host smart-3591c54b-65ef-403c-a81c-7437acdd4d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296625964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.296625964
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3378664301
Short name T521
Test name
Test status
Simulation time 31347319 ps
CPU time 1.73 seconds
Started Mar 19 03:20:47 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 213484 kb
Host smart-421150cb-e51c-4ead-a67c-070541d214e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378664301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3378664301
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4105509313
Short name T414
Test name
Test status
Simulation time 358684026 ps
CPU time 22.5 seconds
Started Mar 19 03:20:53 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 251136 kb
Host smart-2052396e-5b7b-4cf9-8202-2bc7513cf448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105509313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4105509313
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4156241897
Short name T1106
Test name
Test status
Simulation time 230602202 ps
CPU time 25.76 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:55 PM PDT 24
Peak memory 250948 kb
Host smart-3947f32d-712e-4024-b3b6-0f6eb4c25cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156241897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4156241897
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.14919668
Short name T661
Test name
Test status
Simulation time 68489575 ps
CPU time 3.82 seconds
Started Mar 19 03:20:50 PM PDT 24
Finished Mar 19 03:20:54 PM PDT 24
Peak memory 222388 kb
Host smart-d63fd979-bcf5-4549-aefa-71c963a23af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14919668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.14919668
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.641177138
Short name T630
Test name
Test status
Simulation time 250201154 ps
CPU time 8.83 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:39 PM PDT 24
Peak memory 248244 kb
Host smart-5a2c135d-871f-40d0-9335-44cbfcbeb4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641177138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.641177138
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3739892708
Short name T1428
Test name
Test status
Simulation time 7113045198 ps
CPU time 142.66 seconds
Started Mar 19 03:20:48 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 270424 kb
Host smart-a9dd744e-2083-4841-9b1f-7e9d1c603ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739892708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3739892708
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3810563464
Short name T982
Test name
Test status
Simulation time 8038600193 ps
CPU time 73.04 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:18:42 PM PDT 24
Peak memory 247168 kb
Host smart-6b1edb07-1985-4540-8f7b-b1d9995ee210
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810563464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3810563464
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3883486664
Short name T1351
Test name
Test status
Simulation time 14471527982 ps
CPU time 302.7 seconds
Started Mar 19 03:20:59 PM PDT 24
Finished Mar 19 03:26:02 PM PDT 24
Peak memory 278704 kb
Host smart-2bac1f71-9f80-48ff-bf4a-4835b2fa72e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3883486664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3883486664
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1489512998
Short name T1447
Test name
Test status
Simulation time 14222976 ps
CPU time 1.06 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:31 PM PDT 24
Peak memory 211488 kb
Host smart-3e412270-d71f-4b57-bf59-69c9d9073451
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489512998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1489512998
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2088654044
Short name T416
Test name
Test status
Simulation time 103818927 ps
CPU time 1.03 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:47 PM PDT 24
Peak memory 212692 kb
Host smart-23b6a100-5103-4a81-afa6-787553744943
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088654044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2088654044
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1328881676
Short name T533
Test name
Test status
Simulation time 51679843 ps
CPU time 1.1 seconds
Started Mar 19 03:20:58 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 209628 kb
Host smart-bd2539aa-510d-4d40-bdf4-d25486011749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328881676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1328881676
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1965069132
Short name T570
Test name
Test status
Simulation time 32278400 ps
CPU time 1.09 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:36 PM PDT 24
Peak memory 209600 kb
Host smart-726c6f3c-8987-4140-bb57-d4eda80033eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965069132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1965069132
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.149489268
Short name T1102
Test name
Test status
Simulation time 1385329719 ps
CPU time 12.8 seconds
Started Mar 19 03:20:52 PM PDT 24
Finished Mar 19 03:21:05 PM PDT 24
Peak memory 217960 kb
Host smart-54f98d7f-f3f5-4e83-afc5-baf1bc11f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149489268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.149489268
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2354369890
Short name T955
Test name
Test status
Simulation time 503111096 ps
CPU time 9.19 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:39 PM PDT 24
Peak memory 217936 kb
Host smart-12710de9-7b32-488d-92af-020390c25079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354369890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2354369890
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3654088538
Short name T873
Test name
Test status
Simulation time 542495032 ps
CPU time 6.57 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:39 PM PDT 24
Peak memory 209328 kb
Host smart-a821e457-ddc9-49e3-83df-31422d8fada5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654088538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3654088538
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.643432292
Short name T663
Test name
Test status
Simulation time 132235610 ps
CPU time 2.15 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 209480 kb
Host smart-703671a1-a172-427d-9e7d-9509907ae461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643432292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.643432292
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1894514025
Short name T1655
Test name
Test status
Simulation time 81312930 ps
CPU time 3.27 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:48 PM PDT 24
Peak memory 217996 kb
Host smart-5d733b17-9122-4028-ace7-2f5a6e05e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894514025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1894514025
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.241054694
Short name T1563
Test name
Test status
Simulation time 357624135 ps
CPU time 3.17 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:36 PM PDT 24
Peak memory 222148 kb
Host smart-c6ea24c0-d1fa-41c2-83d8-db1280530328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241054694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.241054694
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.219164029
Short name T16
Test name
Test status
Simulation time 613417699 ps
CPU time 14.58 seconds
Started Mar 19 03:21:02 PM PDT 24
Finished Mar 19 03:21:17 PM PDT 24
Peak memory 219172 kb
Host smart-edfbc70e-1078-47e6-94f7-0578ea2d46c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219164029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.219164029
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3994670450
Short name T1430
Test name
Test status
Simulation time 1447593901 ps
CPU time 12.53 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:43 PM PDT 24
Peak memory 218908 kb
Host smart-cf519260-ea84-47de-9c3e-808839bd8d22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994670450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3994670450
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2796103567
Short name T1695
Test name
Test status
Simulation time 809049086 ps
CPU time 8.73 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:40 PM PDT 24
Peak memory 217836 kb
Host smart-c92ef5af-bcc1-45c7-900f-0f2e78355417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796103567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2796103567
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.694147322
Short name T804
Test name
Test status
Simulation time 1800439899 ps
CPU time 17.09 seconds
Started Mar 19 03:20:47 PM PDT 24
Finished Mar 19 03:21:04 PM PDT 24
Peak memory 217832 kb
Host smart-5b485c18-d70d-4e81-95a1-accac7024de1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694147322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.694147322
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2587344727
Short name T1174
Test name
Test status
Simulation time 503586221 ps
CPU time 11.34 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:41 PM PDT 24
Peak memory 217964 kb
Host smart-e8697af6-55a7-45ad-b940-b327c4147314
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587344727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2587344727
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.486966037
Short name T436
Test name
Test status
Simulation time 273132653 ps
CPU time 10.65 seconds
Started Mar 19 03:20:53 PM PDT 24
Finished Mar 19 03:21:04 PM PDT 24
Peak memory 218228 kb
Host smart-d858e5f9-3771-4fc5-9136-56bbf1f16dd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486966037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.486966037
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1554314616
Short name T987
Test name
Test status
Simulation time 1063350920 ps
CPU time 11.62 seconds
Started Mar 19 03:17:32 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 226040 kb
Host smart-fe576509-979e-4b7f-ab1b-29401ad693b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554314616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1554314616
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2390046081
Short name T550
Test name
Test status
Simulation time 5593407556 ps
CPU time 11.43 seconds
Started Mar 19 03:20:47 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 225868 kb
Host smart-598c6db7-1865-4247-ad43-6dc22eb1436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390046081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2390046081
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1256609810
Short name T1316
Test name
Test status
Simulation time 56480824 ps
CPU time 3.61 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 214652 kb
Host smart-cfba1dd1-cb3d-406f-af5f-35fcff21dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256609810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1256609810
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2733821765
Short name T428
Test name
Test status
Simulation time 36349055 ps
CPU time 1.96 seconds
Started Mar 19 03:20:49 PM PDT 24
Finished Mar 19 03:20:51 PM PDT 24
Peak memory 213820 kb
Host smart-7a75574b-d689-4ddb-9332-d419bff7cbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733821765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2733821765
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2182675749
Short name T113
Test name
Test status
Simulation time 194555732 ps
CPU time 27.36 seconds
Started Mar 19 03:20:47 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 250948 kb
Host smart-77b50aaa-4365-4e2d-b83a-dd66e8b2fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182675749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2182675749
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4096807477
Short name T1014
Test name
Test status
Simulation time 206521415 ps
CPU time 22.62 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:53 PM PDT 24
Peak memory 250972 kb
Host smart-adad510e-b9c7-45b0-bf53-99477c867e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096807477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4096807477
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2183075819
Short name T946
Test name
Test status
Simulation time 63990190 ps
CPU time 10.67 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:40 PM PDT 24
Peak memory 250936 kb
Host smart-2a87c142-61f5-4f99-878b-826957f77947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183075819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2183075819
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.428843306
Short name T1161
Test name
Test status
Simulation time 271364913 ps
CPU time 3.11 seconds
Started Mar 19 03:20:50 PM PDT 24
Finished Mar 19 03:20:53 PM PDT 24
Peak memory 222404 kb
Host smart-9c9db525-f9ba-4c28-934d-67736a50d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428843306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.428843306
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1435951510
Short name T449
Test name
Test status
Simulation time 70976560541 ps
CPU time 580.88 seconds
Started Mar 19 03:17:35 PM PDT 24
Finished Mar 19 03:27:16 PM PDT 24
Peak memory 253460 kb
Host smart-12edf0d0-2ac6-4165-8a2d-7bce23ee7557
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435951510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1435951510
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.336725695
Short name T476
Test name
Test status
Simulation time 4255261616 ps
CPU time 76.99 seconds
Started Mar 19 03:20:50 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 250880 kb
Host smart-a5d2c0fb-5a7a-4cf0-8391-5bd0b39e645d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336725695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.336725695
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1421771152
Short name T319
Test name
Test status
Simulation time 32529282 ps
CPU time 0.87 seconds
Started Mar 19 03:20:46 PM PDT 24
Finished Mar 19 03:20:46 PM PDT 24
Peak memory 211516 kb
Host smart-1fffc6a7-2c35-4235-a7d3-a26c451ff529
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421771152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1421771152
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.284813592
Short name T1509
Test name
Test status
Simulation time 50605782 ps
CPU time 0.84 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:32 PM PDT 24
Peak memory 211412 kb
Host smart-3080f4c3-942d-40f8-80fc-d61d9fe5aa60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284813592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.284813592
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3857728290
Short name T728
Test name
Test status
Simulation time 20046566 ps
CPU time 1.16 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 209720 kb
Host smart-ce02592c-a9b8-4bdf-9a48-e3f8768dabab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857728290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3857728290
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3886318790
Short name T491
Test name
Test status
Simulation time 67686921 ps
CPU time 0.95 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 209564 kb
Host smart-5e47c36b-82ce-4265-8cb7-5c16d03deebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886318790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3886318790
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1099957798
Short name T1013
Test name
Test status
Simulation time 4558131495 ps
CPU time 11.93 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:57 PM PDT 24
Peak memory 219032 kb
Host smart-ca56f784-42c6-47c2-a05a-e85eca938320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099957798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1099957798
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2703587094
Short name T900
Test name
Test status
Simulation time 399249945 ps
CPU time 12.24 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:41 PM PDT 24
Peak memory 226040 kb
Host smart-1fe466eb-b129-4fe3-83cb-542c2bb0c3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703587094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2703587094
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1738384407
Short name T888
Test name
Test status
Simulation time 2615484247 ps
CPU time 12.52 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:10 PM PDT 24
Peak memory 209676 kb
Host smart-5a423cb2-3c5a-4242-beef-7b03fda04455
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738384407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1738384407
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.549448406
Short name T609
Test name
Test status
Simulation time 262029946 ps
CPU time 3.79 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:17:33 PM PDT 24
Peak memory 209540 kb
Host smart-ff71a098-7761-4ff0-955c-a8cfe4ad59a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549448406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.549448406
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1773795741
Short name T1523
Test name
Test status
Simulation time 171485024 ps
CPU time 2.16 seconds
Started Mar 19 03:17:31 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 218020 kb
Host smart-3078b173-74fc-4d9d-aa45-ade087356df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773795741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1773795741
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4018982272
Short name T474
Test name
Test status
Simulation time 28609643 ps
CPU time 1.58 seconds
Started Mar 19 03:20:51 PM PDT 24
Finished Mar 19 03:20:53 PM PDT 24
Peak memory 218016 kb
Host smart-6bd412b7-283b-404c-8161-1ec5ee94e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018982272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4018982272
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2910906320
Short name T1162
Test name
Test status
Simulation time 229023760 ps
CPU time 10.6 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 217972 kb
Host smart-b83a59d0-6b25-459e-b17d-d47f8dfc2344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910906320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2910906320
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3620619231
Short name T649
Test name
Test status
Simulation time 1396664847 ps
CPU time 16.08 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:13 PM PDT 24
Peak memory 218176 kb
Host smart-9d6cf415-7d8d-4740-a846-e385764c4b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620619231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3620619231
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2906887431
Short name T1208
Test name
Test status
Simulation time 1154462053 ps
CPU time 12.72 seconds
Started Mar 19 03:21:05 PM PDT 24
Finished Mar 19 03:21:19 PM PDT 24
Peak memory 217884 kb
Host smart-9563d141-7ab7-4366-af7b-bd3bbae2bb4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906887431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2906887431
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.531067525
Short name T1234
Test name
Test status
Simulation time 2987720565 ps
CPU time 12.03 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 217984 kb
Host smart-cc2b2103-2a1c-4c32-86f5-2e62867db4f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531067525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.531067525
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1360618839
Short name T850
Test name
Test status
Simulation time 1262782812 ps
CPU time 10.61 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 217848 kb
Host smart-96563d97-2509-4dca-be3b-61c75df5cf30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360618839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1360618839
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1413035702
Short name T808
Test name
Test status
Simulation time 365096832 ps
CPU time 10.34 seconds
Started Mar 19 03:21:07 PM PDT 24
Finished Mar 19 03:21:18 PM PDT 24
Peak memory 217972 kb
Host smart-06008fb2-cc40-4a6f-8b09-fef6b9bb2a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413035702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1413035702
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1349808820
Short name T1116
Test name
Test status
Simulation time 1553018722 ps
CPU time 12.1 seconds
Started Mar 19 03:20:44 PM PDT 24
Finished Mar 19 03:20:57 PM PDT 24
Peak memory 224404 kb
Host smart-b9c8fc51-429e-4313-9081-ca48dda845b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349808820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1349808820
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2175639758
Short name T1457
Test name
Test status
Simulation time 332451727 ps
CPU time 11.28 seconds
Started Mar 19 03:17:35 PM PDT 24
Finished Mar 19 03:17:46 PM PDT 24
Peak memory 225792 kb
Host smart-5c098b48-f9ad-4dcc-8413-d3e015d2190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175639758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2175639758
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3723101647
Short name T302
Test name
Test status
Simulation time 145937431 ps
CPU time 3.39 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 214068 kb
Host smart-9c0fedc7-5517-41c9-bde5-29cbe3ee6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723101647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3723101647
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3749495414
Short name T960
Test name
Test status
Simulation time 65779700 ps
CPU time 1.28 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:17:31 PM PDT 24
Peak memory 213368 kb
Host smart-6c47593b-47a9-45b2-897d-a1906d72f899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749495414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3749495414
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3322964339
Short name T1265
Test name
Test status
Simulation time 3608058175 ps
CPU time 29.56 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:18:03 PM PDT 24
Peak memory 250880 kb
Host smart-1244b6e7-292f-45dd-9c30-5195bf43d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322964339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3322964339
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3614162068
Short name T972
Test name
Test status
Simulation time 1270554452 ps
CPU time 28.45 seconds
Started Mar 19 03:20:52 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 250896 kb
Host smart-cd4b5264-66dd-41cd-834b-dca1ec0637ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614162068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3614162068
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1736534123
Short name T308
Test name
Test status
Simulation time 421574689 ps
CPU time 8.65 seconds
Started Mar 19 03:20:45 PM PDT 24
Finished Mar 19 03:20:54 PM PDT 24
Peak memory 250876 kb
Host smart-bc7fec8d-9a43-44f3-a3c3-cd9e8f89159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736534123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1736534123
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3559868183
Short name T1159
Test name
Test status
Simulation time 191271766 ps
CPU time 2.85 seconds
Started Mar 19 03:17:32 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 222000 kb
Host smart-d0a671f8-1738-4c53-ba03-c82bbb74745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559868183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3559868183
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1258845431
Short name T1581
Test name
Test status
Simulation time 5232217789 ps
CPU time 163.01 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:20:17 PM PDT 24
Peak memory 269716 kb
Host smart-8dfda277-0ff0-4f99-80c8-5dc805c8d83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258845431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1258845431
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3067701885
Short name T88
Test name
Test status
Simulation time 2777002625 ps
CPU time 58.93 seconds
Started Mar 19 03:21:03 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 251060 kb
Host smart-96ee584e-a5c5-412b-96c9-1fd43d16a084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067701885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3067701885
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3030237834
Short name T392
Test name
Test status
Simulation time 35637704 ps
CPU time 0.87 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 211600 kb
Host smart-387ebf30-a64f-4fe4-9e64-8a07d21cd2bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030237834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3030237834
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.304970249
Short name T709
Test name
Test status
Simulation time 44567518 ps
CPU time 0.91 seconds
Started Mar 19 03:20:54 PM PDT 24
Finished Mar 19 03:20:56 PM PDT 24
Peak memory 211496 kb
Host smart-8d2b5209-4a85-45e5-98f0-b6345020eb88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304970249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.304970249
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1647765893
Short name T539
Test name
Test status
Simulation time 14563766 ps
CPU time 1.06 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 209600 kb
Host smart-9ba68310-4bf3-45da-9b2d-f3b9eeb204c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647765893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1647765893
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3554094017
Short name T651
Test name
Test status
Simulation time 19155264 ps
CPU time 1.2 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 209612 kb
Host smart-c6ab032c-3947-4cb1-864b-3b52820e7d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554094017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3554094017
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.410112723
Short name T1598
Test name
Test status
Simulation time 5426456605 ps
CPU time 16.49 seconds
Started Mar 19 03:17:32 PM PDT 24
Finished Mar 19 03:17:49 PM PDT 24
Peak memory 218324 kb
Host smart-dd5197f2-62b9-4ea2-b933-a47969fd91e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410112723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.410112723
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.4209896795
Short name T1061
Test name
Test status
Simulation time 991266027 ps
CPU time 7.56 seconds
Started Mar 19 03:21:08 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 225600 kb
Host smart-ee7980cf-f960-41a1-bae5-59da26afff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209896795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4209896795
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3262606114
Short name T523
Test name
Test status
Simulation time 242782562 ps
CPU time 7.21 seconds
Started Mar 19 03:20:55 PM PDT 24
Finished Mar 19 03:21:03 PM PDT 24
Peak memory 217184 kb
Host smart-e6e82413-42a4-4f6e-b708-4c5e63deb38e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262606114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3262606114
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.988641177
Short name T836
Test name
Test status
Simulation time 445518607 ps
CPU time 4.89 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:38 PM PDT 24
Peak memory 209464 kb
Host smart-4f0117f8-28d7-4e76-a961-877465a1fb5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988641177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.988641177
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1013919225
Short name T977
Test name
Test status
Simulation time 410529013 ps
CPU time 3.65 seconds
Started Mar 19 03:21:02 PM PDT 24
Finished Mar 19 03:21:06 PM PDT 24
Peak memory 222320 kb
Host smart-8593daf6-f990-407e-983b-2e3d20d29854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013919225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1013919225
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1209975163
Short name T1567
Test name
Test status
Simulation time 83859162 ps
CPU time 2.65 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 221732 kb
Host smart-ffc16c95-408e-4aa7-9b0e-ee57df3e0daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209975163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1209975163
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2522077113
Short name T1164
Test name
Test status
Simulation time 517869700 ps
CPU time 15.2 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:12 PM PDT 24
Peak memory 226032 kb
Host smart-2bd5f95a-f46d-47b4-ad08-2b71a1eef0d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522077113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2522077113
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.4080411271
Short name T373
Test name
Test status
Simulation time 572407831 ps
CPU time 8.43 seconds
Started Mar 19 03:17:28 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 218152 kb
Host smart-3efb7920-30b1-4545-b747-78aa08e7207a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080411271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.4080411271
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.164361516
Short name T340
Test name
Test status
Simulation time 318789538 ps
CPU time 13.88 seconds
Started Mar 19 03:17:35 PM PDT 24
Finished Mar 19 03:17:49 PM PDT 24
Peak memory 217980 kb
Host smart-330be7e3-86fa-4786-b308-b86f529ea5ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164361516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.164361516
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.366174158
Short name T1218
Test name
Test status
Simulation time 858286703 ps
CPU time 19.4 seconds
Started Mar 19 03:21:01 PM PDT 24
Finished Mar 19 03:21:20 PM PDT 24
Peak memory 217912 kb
Host smart-c4581d86-b305-4f9d-8658-04a004eb53e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366174158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.366174158
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1198480456
Short name T507
Test name
Test status
Simulation time 3960594152 ps
CPU time 8.61 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:06 PM PDT 24
Peak memory 218016 kb
Host smart-4791650d-53c1-448e-b3f0-ce6d249923fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198480456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1198480456
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1819533007
Short name T1622
Test name
Test status
Simulation time 1286972322 ps
CPU time 10.73 seconds
Started Mar 19 03:17:33 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 217836 kb
Host smart-b075bfbe-6ca3-4001-8ac8-b28a2efaa2b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819533007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1819533007
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1550412561
Short name T1546
Test name
Test status
Simulation time 2266673363 ps
CPU time 9.32 seconds
Started Mar 19 03:21:06 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 225192 kb
Host smart-104f5bc6-338b-466b-a8a4-3a36d99e18b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550412561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1550412561
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1761624473
Short name T1605
Test name
Test status
Simulation time 290330413 ps
CPU time 12.7 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:47 PM PDT 24
Peak memory 225468 kb
Host smart-5b985941-bba9-428c-9106-209cc0c43a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761624473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1761624473
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2054642688
Short name T1006
Test name
Test status
Simulation time 255896319 ps
CPU time 3.5 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:38 PM PDT 24
Peak memory 217700 kb
Host smart-77e20816-8806-444d-9938-19bbceb0a603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054642688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2054642688
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2617659211
Short name T1298
Test name
Test status
Simulation time 324949599 ps
CPU time 2.27 seconds
Started Mar 19 03:21:08 PM PDT 24
Finished Mar 19 03:21:10 PM PDT 24
Peak memory 217676 kb
Host smart-cb4e1c7b-3f92-477f-afd2-c799f8b7626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617659211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2617659211
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.303593629
Short name T538
Test name
Test status
Simulation time 3892522356 ps
CPU time 30.75 seconds
Started Mar 19 03:17:29 PM PDT 24
Finished Mar 19 03:18:00 PM PDT 24
Peak memory 251076 kb
Host smart-5e0ae54c-3a96-4371-b581-6fd489fa8b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303593629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.303593629
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.372642015
Short name T1023
Test name
Test status
Simulation time 1111516119 ps
CPU time 30.16 seconds
Started Mar 19 03:20:59 PM PDT 24
Finished Mar 19 03:21:29 PM PDT 24
Peak memory 250976 kb
Host smart-f496427a-9b94-4c12-9df5-ecdc97df0da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372642015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.372642015
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3962390821
Short name T1180
Test name
Test status
Simulation time 162440989 ps
CPU time 3.17 seconds
Started Mar 19 03:17:32 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 217952 kb
Host smart-41c27dbe-eb5e-4e95-9b4f-aadae048c205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962390821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3962390821
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.984708175
Short name T1077
Test name
Test status
Simulation time 128614910 ps
CPU time 2.92 seconds
Started Mar 19 03:21:02 PM PDT 24
Finished Mar 19 03:21:05 PM PDT 24
Peak memory 222268 kb
Host smart-08f24696-a9f1-47dc-81ae-32d60d869d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984708175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.984708175
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1594888114
Short name T25
Test name
Test status
Simulation time 3157663543 ps
CPU time 63 seconds
Started Mar 19 03:17:30 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 250980 kb
Host smart-e1e9a7e9-5d3c-43b8-be65-b8e298722ac6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594888114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1594888114
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.575220146
Short name T1331
Test name
Test status
Simulation time 60838682484 ps
CPU time 237.74 seconds
Started Mar 19 03:20:55 PM PDT 24
Finished Mar 19 03:24:54 PM PDT 24
Peak memory 270812 kb
Host smart-3b7551bb-3480-46cb-bc43-5d5f3969658b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575220146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.575220146
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.1602205540
Short name T1189
Test name
Test status
Simulation time 18429972810 ps
CPU time 738.43 seconds
Started Mar 19 03:21:05 PM PDT 24
Finished Mar 19 03:33:24 PM PDT 24
Peak memory 438144 kb
Host smart-f2dd4dd5-7b3d-45ea-bf62-4df714b73d39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1602205540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.1602205540
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1014403412
Short name T1345
Test name
Test status
Simulation time 38413638 ps
CPU time 0.89 seconds
Started Mar 19 03:17:34 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 211540 kb
Host smart-8dd4d508-0374-4c73-a6fe-2720996a4502
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014403412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1014403412
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.657326889
Short name T545
Test name
Test status
Simulation time 18977913 ps
CPU time 1.22 seconds
Started Mar 19 03:20:58 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 212960 kb
Host smart-c401c128-3e2b-4289-816e-2b8c88c14d4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657326889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.657326889
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1410797534
Short name T1572
Test name
Test status
Simulation time 25128538 ps
CPU time 1.04 seconds
Started Mar 19 03:21:05 PM PDT 24
Finished Mar 19 03:21:06 PM PDT 24
Peak memory 209608 kb
Host smart-2a979d38-aed2-4d61-8da4-51efbbfdee65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410797534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1410797534
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2946017570
Short name T1380
Test name
Test status
Simulation time 27887622 ps
CPU time 0.9 seconds
Started Mar 19 03:17:49 PM PDT 24
Finished Mar 19 03:17:50 PM PDT 24
Peak memory 209520 kb
Host smart-43717e76-88d5-4f77-b616-c1b1978baed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946017570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2946017570
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1008001946
Short name T811
Test name
Test status
Simulation time 1357999434 ps
CPU time 24.44 seconds
Started Mar 19 03:17:54 PM PDT 24
Finished Mar 19 03:18:18 PM PDT 24
Peak memory 226056 kb
Host smart-61c43bdb-49ae-4544-8663-23c0d5a48540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008001946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1008001946
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3204203442
Short name T959
Test name
Test status
Simulation time 605997851 ps
CPU time 13.86 seconds
Started Mar 19 03:20:59 PM PDT 24
Finished Mar 19 03:21:13 PM PDT 24
Peak memory 217864 kb
Host smart-a7a92896-9864-458b-b00d-48942afd874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204203442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3204203442
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3328793588
Short name T1651
Test name
Test status
Simulation time 79342045 ps
CPU time 1.89 seconds
Started Mar 19 03:20:59 PM PDT 24
Finished Mar 19 03:21:01 PM PDT 24
Peak memory 209464 kb
Host smart-9f2c352d-9cb6-41d1-a44d-c79f263235f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328793588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3328793588
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.849864038
Short name T837
Test name
Test status
Simulation time 723111967 ps
CPU time 2.34 seconds
Started Mar 19 03:17:46 PM PDT 24
Finished Mar 19 03:17:48 PM PDT 24
Peak memory 216832 kb
Host smart-b2de3d58-2f54-42c8-9f6c-faa54d792e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849864038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.849864038
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2940886196
Short name T1285
Test name
Test status
Simulation time 61833538 ps
CPU time 1.42 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 221332 kb
Host smart-9df8a29b-4cfb-4ca7-9d21-cbb3c7a75b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940886196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2940886196
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3551719011
Short name T905
Test name
Test status
Simulation time 146019449 ps
CPU time 3.99 seconds
Started Mar 19 03:20:58 PM PDT 24
Finished Mar 19 03:21:02 PM PDT 24
Peak memory 222096 kb
Host smart-e716b15e-350b-44aa-9dc1-aa9696c392f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551719011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3551719011
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1108505729
Short name T1123
Test name
Test status
Simulation time 559373356 ps
CPU time 16.72 seconds
Started Mar 19 03:21:00 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 226052 kb
Host smart-844bda9c-c192-4abd-94af-a489631f8aab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108505729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1108505729
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3170177432
Short name T1681
Test name
Test status
Simulation time 1634042780 ps
CPU time 15.06 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:17:57 PM PDT 24
Peak memory 218888 kb
Host smart-f7b43a4a-66c7-4897-8adb-561aa95538a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170177432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3170177432
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2278882469
Short name T757
Test name
Test status
Simulation time 2414461831 ps
CPU time 15.32 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:13 PM PDT 24
Peak memory 218004 kb
Host smart-bd1c5807-18a6-4589-bd06-cd3365863a3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278882469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2278882469
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.363230881
Short name T1693
Test name
Test status
Simulation time 274790947 ps
CPU time 11.27 seconds
Started Mar 19 03:17:40 PM PDT 24
Finished Mar 19 03:17:52 PM PDT 24
Peak memory 217892 kb
Host smart-6c521db5-895b-4a88-acd2-5098a29704e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363230881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.363230881
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1298481123
Short name T1224
Test name
Test status
Simulation time 247954404 ps
CPU time 7.5 seconds
Started Mar 19 03:17:49 PM PDT 24
Finished Mar 19 03:17:56 PM PDT 24
Peak memory 217888 kb
Host smart-4a465819-16a4-422c-8b5f-2e6be5dba5f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298481123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1298481123
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.348330046
Short name T928
Test name
Test status
Simulation time 4462546239 ps
CPU time 7.2 seconds
Started Mar 19 03:20:59 PM PDT 24
Finished Mar 19 03:21:06 PM PDT 24
Peak memory 218052 kb
Host smart-475eeb8b-3b50-4b8c-82e1-1212c6924d0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348330046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.348330046
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2020267644
Short name T246
Test name
Test status
Simulation time 2238939682 ps
CPU time 8.6 seconds
Started Mar 19 03:20:56 PM PDT 24
Finished Mar 19 03:21:05 PM PDT 24
Peak memory 224300 kb
Host smart-cb374fc8-c7fe-4f1b-8ecd-99341a44cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020267644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2020267644
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.377026742
Short name T1648
Test name
Test status
Simulation time 673329922 ps
CPU time 12.85 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:17:55 PM PDT 24
Peak memory 224776 kb
Host smart-562ef887-f36f-4139-a189-0517736b88fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377026742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.377026742
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2175795852
Short name T780
Test name
Test status
Simulation time 154645664 ps
CPU time 4.68 seconds
Started Mar 19 03:17:44 PM PDT 24
Finished Mar 19 03:17:48 PM PDT 24
Peak memory 217636 kb
Host smart-e61ad5cf-4ab0-44bc-aa7f-d322a55087f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175795852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2175795852
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3616934148
Short name T1184
Test name
Test status
Simulation time 218387554 ps
CPU time 2.34 seconds
Started Mar 19 03:21:01 PM PDT 24
Finished Mar 19 03:21:03 PM PDT 24
Peak memory 217832 kb
Host smart-4b773636-7da3-4e39-8261-0ec84225efe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616934148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3616934148
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.470971207
Short name T1685
Test name
Test status
Simulation time 877330702 ps
CPU time 25.81 seconds
Started Mar 19 03:20:59 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 250860 kb
Host smart-b5c76c00-ccdd-4359-b920-8430334d78ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470971207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.470971207
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.694613124
Short name T311
Test name
Test status
Simulation time 835553086 ps
CPU time 31.08 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:18:13 PM PDT 24
Peak memory 250908 kb
Host smart-068ea2a6-5723-4045-a74f-9b0c6a386fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694613124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.694613124
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2314569689
Short name T1423
Test name
Test status
Simulation time 253749072 ps
CPU time 10.44 seconds
Started Mar 19 03:17:45 PM PDT 24
Finished Mar 19 03:17:56 PM PDT 24
Peak memory 243552 kb
Host smart-8a660e8e-ffa7-42cd-a42f-06aa4e846a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314569689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2314569689
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3680182674
Short name T1003
Test name
Test status
Simulation time 387569271 ps
CPU time 8.97 seconds
Started Mar 19 03:20:58 PM PDT 24
Finished Mar 19 03:21:07 PM PDT 24
Peak memory 250856 kb
Host smart-f7d8ad7d-fd1f-4b28-8b70-94b5f80e8df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680182674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3680182674
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1941706739
Short name T1153
Test name
Test status
Simulation time 27344682532 ps
CPU time 137.64 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 282612 kb
Host smart-547d1594-6523-4f31-8452-048432e26ce6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941706739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1941706739
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3387649596
Short name T644
Test name
Test status
Simulation time 25614688897 ps
CPU time 106.3 seconds
Started Mar 19 03:17:40 PM PDT 24
Finished Mar 19 03:19:27 PM PDT 24
Peak memory 273144 kb
Host smart-95e5ce58-6408-4f85-b57b-b8515904cef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387649596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3387649596
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3975844141
Short name T1110
Test name
Test status
Simulation time 45519799 ps
CPU time 0.87 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:17:43 PM PDT 24
Peak memory 212396 kb
Host smart-0eeba2f1-bb9e-4de7-9cd7-356115c6a093
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975844141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3975844141
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.542927709
Short name T1630
Test name
Test status
Simulation time 28082732 ps
CPU time 0.96 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 212656 kb
Host smart-f863d990-ac82-4b24-9240-2f0aaf7c30a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542927709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.542927709
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1156106437
Short name T1401
Test name
Test status
Simulation time 24817977 ps
CPU time 1.06 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 209588 kb
Host smart-8a8b9eff-e105-4e43-9e11-78553ab0e8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156106437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1156106437
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.68890779
Short name T1425
Test name
Test status
Simulation time 17878214 ps
CPU time 1.16 seconds
Started Mar 19 03:21:01 PM PDT 24
Finished Mar 19 03:21:02 PM PDT 24
Peak memory 209456 kb
Host smart-a57454ad-c1c9-4a3f-af7b-a456c3330ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68890779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.68890779
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2806694077
Short name T1259
Test name
Test status
Simulation time 486799062 ps
CPU time 8.72 seconds
Started Mar 19 03:20:58 PM PDT 24
Finished Mar 19 03:21:07 PM PDT 24
Peak memory 217880 kb
Host smart-0664758c-f8ba-4f64-989d-89eba8e170b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806694077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2806694077
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.395290373
Short name T1594
Test name
Test status
Simulation time 2278814960 ps
CPU time 17.66 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:18:00 PM PDT 24
Peak memory 217960 kb
Host smart-4d753d49-ace0-429c-86dc-fd9970abb33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395290373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.395290373
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.18173563
Short name T564
Test name
Test status
Simulation time 89732493 ps
CPU time 2.38 seconds
Started Mar 19 03:21:02 PM PDT 24
Finished Mar 19 03:21:05 PM PDT 24
Peak memory 216892 kb
Host smart-4ae3d3aa-985b-4397-bea8-65ee7eb2fa6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18173563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.18173563
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2070755846
Short name T1233
Test name
Test status
Simulation time 1178194631 ps
CPU time 3 seconds
Started Mar 19 03:17:39 PM PDT 24
Finished Mar 19 03:17:43 PM PDT 24
Peak memory 216860 kb
Host smart-18aa8b1f-2bd5-4a7a-a27b-f5f1725e042a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070755846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2070755846
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2756061149
Short name T557
Test name
Test status
Simulation time 28211400 ps
CPU time 2.21 seconds
Started Mar 19 03:20:58 PM PDT 24
Finished Mar 19 03:21:00 PM PDT 24
Peak memory 221712 kb
Host smart-23ae539a-5a3f-4e88-b8de-7e0dae3289ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756061149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2756061149
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3382725660
Short name T384
Test name
Test status
Simulation time 146166338 ps
CPU time 2.38 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 221828 kb
Host smart-9e073dfd-299f-419e-8860-65c036bdc4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382725660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3382725660
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2893641475
Short name T1206
Test name
Test status
Simulation time 457067702 ps
CPU time 9.08 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:50 PM PDT 24
Peak memory 226052 kb
Host smart-f46480e7-9cf2-41eb-8677-153ea7b71475
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893641475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2893641475
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3379657392
Short name T387
Test name
Test status
Simulation time 487618098 ps
CPU time 13.36 seconds
Started Mar 19 03:21:01 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 225904 kb
Host smart-5d75a7b3-a7bb-4e85-a027-4280dbd8707b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379657392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3379657392
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3694185332
Short name T799
Test name
Test status
Simulation time 404030681 ps
CPU time 14.98 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:58 PM PDT 24
Peak memory 217836 kb
Host smart-e5823036-b0d6-43a5-af42-0628fe0570ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694185332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3694185332
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.803683860
Short name T1340
Test name
Test status
Simulation time 553245841 ps
CPU time 12.41 seconds
Started Mar 19 03:21:01 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 217992 kb
Host smart-b9c556b6-5dda-4b6b-983f-dfaee3db9bb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803683860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.803683860
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2875370101
Short name T93
Test name
Test status
Simulation time 816934373 ps
CPU time 13.19 seconds
Started Mar 19 03:21:01 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 217736 kb
Host smart-29968aa1-1a6e-4dfd-a830-aa7f0193d390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875370101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2875370101
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.383373147
Short name T526
Test name
Test status
Simulation time 360689134 ps
CPU time 12.57 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:56 PM PDT 24
Peak memory 217916 kb
Host smart-63935520-ec67-4531-aa7c-30d93a120e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383373147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.383373147
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2133598458
Short name T1632
Test name
Test status
Simulation time 867146251 ps
CPU time 8.56 seconds
Started Mar 19 03:17:39 PM PDT 24
Finished Mar 19 03:17:48 PM PDT 24
Peak memory 224676 kb
Host smart-757344f0-83e4-4078-a3b3-b19008a1c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133598458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2133598458
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3390071330
Short name T1205
Test name
Test status
Simulation time 295717259 ps
CPU time 10.9 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:08 PM PDT 24
Peak memory 225376 kb
Host smart-c2711e8b-29dd-4822-8ab7-cb9fa5131c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390071330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3390071330
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2918305203
Short name T408
Test name
Test status
Simulation time 102424231 ps
CPU time 2.29 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 213900 kb
Host smart-140a3ccf-0957-4816-b5e0-cd173802c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918305203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2918305203
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3663633968
Short name T265
Test name
Test status
Simulation time 250422301 ps
CPU time 3.71 seconds
Started Mar 19 03:21:07 PM PDT 24
Finished Mar 19 03:21:11 PM PDT 24
Peak memory 213744 kb
Host smart-c9493c5e-3b43-4e78-b9e0-9bd81b5a79a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663633968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3663633968
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2637480489
Short name T1067
Test name
Test status
Simulation time 487117093 ps
CPU time 27.8 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:18:09 PM PDT 24
Peak memory 250972 kb
Host smart-fb4ba846-a523-4f4e-85b3-5f39cfa7ce6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637480489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2637480489
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3197484735
Short name T772
Test name
Test status
Simulation time 848522840 ps
CPU time 26.15 seconds
Started Mar 19 03:21:02 PM PDT 24
Finished Mar 19 03:21:29 PM PDT 24
Peak memory 247284 kb
Host smart-56d7a512-d6b6-457e-be54-dae408f35dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197484735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3197484735
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3611575961
Short name T1687
Test name
Test status
Simulation time 71493459 ps
CPU time 7 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:04 PM PDT 24
Peak memory 247064 kb
Host smart-9a1ff0be-495f-450f-87ff-8d50692dbc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611575961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3611575961
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.738972583
Short name T332
Test name
Test status
Simulation time 48957002 ps
CPU time 3.45 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:17:46 PM PDT 24
Peak memory 222452 kb
Host smart-870b9baa-0f98-4b4a-b46b-ebcab344bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738972583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.738972583
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1669790743
Short name T563
Test name
Test status
Simulation time 23788998787 ps
CPU time 180.53 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:20:44 PM PDT 24
Peak memory 250936 kb
Host smart-5bc450e7-116c-4bbb-b5bb-5e2a933bfec4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669790743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1669790743
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1803801816
Short name T591
Test name
Test status
Simulation time 14093061837 ps
CPU time 84.07 seconds
Started Mar 19 03:21:01 PM PDT 24
Finished Mar 19 03:22:25 PM PDT 24
Peak memory 217812 kb
Host smart-b6f3a867-0e6c-4a8c-87b6-2cb3b97a0c5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803801816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1803801816
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.728460461
Short name T1540
Test name
Test status
Simulation time 63397940175 ps
CPU time 548.06 seconds
Started Mar 19 03:21:00 PM PDT 24
Finished Mar 19 03:30:08 PM PDT 24
Peak memory 486852 kb
Host smart-803543b1-092c-446d-93ac-34f9b376dcc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=728460461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.728460461
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1076520118
Short name T301
Test name
Test status
Simulation time 13442224 ps
CPU time 1.05 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:17:43 PM PDT 24
Peak memory 211552 kb
Host smart-f55c507b-9c39-4152-9958-bd2a2a9532a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076520118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1076520118
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.4269027032
Short name T107
Test name
Test status
Simulation time 16929803 ps
CPU time 0.97 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:20:58 PM PDT 24
Peak memory 212684 kb
Host smart-a9980568-a11b-45e0-9bc9-9dad48a49dc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269027032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.4269027032
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1208366427
Short name T255
Test name
Test status
Simulation time 33894637 ps
CPU time 0.89 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 209592 kb
Host smart-ec7ee956-8e7c-4204-bf1d-592c685ce316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208366427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1208366427
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2878712677
Short name T830
Test name
Test status
Simulation time 66697773 ps
CPU time 1.11 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:17 PM PDT 24
Peak memory 209608 kb
Host smart-a2e23b8c-2cab-4265-bb32-dd50dfad9114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878712677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2878712677
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.361866801
Short name T297
Test name
Test status
Simulation time 888443467 ps
CPU time 20.15 seconds
Started Mar 19 03:20:57 PM PDT 24
Finished Mar 19 03:21:17 PM PDT 24
Peak memory 226036 kb
Host smart-226b824c-a5e4-4195-a522-0fd8fafe5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361866801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.361866801
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3808434361
Short name T693
Test name
Test status
Simulation time 571115284 ps
CPU time 8.77 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:50 PM PDT 24
Peak memory 217868 kb
Host smart-76110811-5530-4b17-a30e-2500d944ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808434361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3808434361
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2696516307
Short name T1183
Test name
Test status
Simulation time 565318308 ps
CPU time 8.3 seconds
Started Mar 19 03:20:59 PM PDT 24
Finished Mar 19 03:21:07 PM PDT 24
Peak memory 216928 kb
Host smart-ee4738ef-1390-450b-9376-faf95cfe5fa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696516307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2696516307
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.4086437636
Short name T1219
Test name
Test status
Simulation time 2009206430 ps
CPU time 12.85 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:54 PM PDT 24
Peak memory 209488 kb
Host smart-f72be839-5617-412c-b5c6-ccb5ef5f262f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086437636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4086437636
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1325188451
Short name T802
Test name
Test status
Simulation time 291379110 ps
CPU time 3.9 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:47 PM PDT 24
Peak memory 218020 kb
Host smart-4cd7ab71-ba47-4ed1-906e-19ed60b128ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325188451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1325188451
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1342190065
Short name T459
Test name
Test status
Simulation time 1461307020 ps
CPU time 2.91 seconds
Started Mar 19 03:21:04 PM PDT 24
Finished Mar 19 03:21:07 PM PDT 24
Peak memory 221908 kb
Host smart-717953f1-35ff-486f-8cee-a295ba548099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342190065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1342190065
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.13469091
Short name T365
Test name
Test status
Simulation time 696125819 ps
CPU time 18.01 seconds
Started Mar 19 03:21:08 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 225588 kb
Host smart-6ee68544-9ecb-4aae-bc20-bfb70ff26a32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13469091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.13469091
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.21998404
Short name T1621
Test name
Test status
Simulation time 1801301499 ps
CPU time 12.78 seconds
Started Mar 19 03:17:40 PM PDT 24
Finished Mar 19 03:17:53 PM PDT 24
Peak memory 226056 kb
Host smart-cc8c4191-e6f8-4f14-a360-7e1aae89f4e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21998404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.21998404
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2100121533
Short name T1283
Test name
Test status
Simulation time 202802654 ps
CPU time 7.86 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:51 PM PDT 24
Peak memory 217908 kb
Host smart-0cc47266-98b3-4804-a4c6-a06eba381c1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100121533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2100121533
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3094624950
Short name T1263
Test name
Test status
Simulation time 1068766603 ps
CPU time 8.81 seconds
Started Mar 19 03:21:02 PM PDT 24
Finished Mar 19 03:21:11 PM PDT 24
Peak memory 217864 kb
Host smart-a5f68c55-a399-41e8-927c-00018bcfe1e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094624950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3094624950
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1191336791
Short name T665
Test name
Test status
Simulation time 577381362 ps
CPU time 7.65 seconds
Started Mar 19 03:21:00 PM PDT 24
Finished Mar 19 03:21:08 PM PDT 24
Peak memory 217864 kb
Host smart-310f991d-a97d-41a1-a8b1-0ba506572194
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191336791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1191336791
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3665336512
Short name T1638
Test name
Test status
Simulation time 820624683 ps
CPU time 5.84 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:49 PM PDT 24
Peak memory 217900 kb
Host smart-199a7f85-8c0e-4c92-908d-48802c7df41d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665336512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3665336512
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2662502859
Short name T1673
Test name
Test status
Simulation time 990381762 ps
CPU time 14.68 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 226000 kb
Host smart-7d10c538-3c5c-46b7-a14b-579296cbd8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662502859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2662502859
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.876252825
Short name T1548
Test name
Test status
Simulation time 456075572 ps
CPU time 7.2 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:50 PM PDT 24
Peak memory 224988 kb
Host smart-736a579b-288f-467f-922b-0e230b85cf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876252825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.876252825
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1350817012
Short name T1229
Test name
Test status
Simulation time 69624393 ps
CPU time 4.14 seconds
Started Mar 19 03:17:49 PM PDT 24
Finished Mar 19 03:17:53 PM PDT 24
Peak memory 217676 kb
Host smart-38e55012-ddfc-4e61-9d94-a01ddcfd7336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350817012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1350817012
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.922009901
Short name T75
Test name
Test status
Simulation time 90809852 ps
CPU time 2.72 seconds
Started Mar 19 03:21:05 PM PDT 24
Finished Mar 19 03:21:08 PM PDT 24
Peak memory 217856 kb
Host smart-eafb3dbb-6ae5-413f-9157-4b28bada91ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922009901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.922009901
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2157809168
Short name T1641
Test name
Test status
Simulation time 231750893 ps
CPU time 24.16 seconds
Started Mar 19 03:21:00 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 250916 kb
Host smart-5e85d0d2-3a5d-44bc-a20c-ab9c5622432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157809168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2157809168
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3449532162
Short name T1092
Test name
Test status
Simulation time 163882960 ps
CPU time 16.93 seconds
Started Mar 19 03:17:39 PM PDT 24
Finished Mar 19 03:17:57 PM PDT 24
Peak memory 250908 kb
Host smart-d818a292-6c97-4c32-8b33-345bb6f90d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449532162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3449532162
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2325865133
Short name T1551
Test name
Test status
Simulation time 55146389 ps
CPU time 6.47 seconds
Started Mar 19 03:17:40 PM PDT 24
Finished Mar 19 03:17:47 PM PDT 24
Peak memory 250844 kb
Host smart-8ec2cde7-10c5-44ae-8ac6-f90f80f657fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325865133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2325865133
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2528737748
Short name T313
Test name
Test status
Simulation time 100566238 ps
CPU time 6.78 seconds
Started Mar 19 03:21:07 PM PDT 24
Finished Mar 19 03:21:15 PM PDT 24
Peak memory 246740 kb
Host smart-c039f206-5a8b-487f-8bc4-aa4b56a3f9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528737748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2528737748
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2767165318
Short name T1155
Test name
Test status
Simulation time 9624200202 ps
CPU time 318.4 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:26:28 PM PDT 24
Peak memory 283800 kb
Host smart-ae3bc678-ff9f-4855-bb5b-53c1eab10afe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767165318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2767165318
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3271117905
Short name T349
Test name
Test status
Simulation time 4678194188 ps
CPU time 53.21 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:18:36 PM PDT 24
Peak memory 271760 kb
Host smart-2e3f2c61-f730-4737-8943-007842302c51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271117905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3271117905
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.758245255
Short name T1244
Test name
Test status
Simulation time 76796965345 ps
CPU time 395.61 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:24:18 PM PDT 24
Peak memory 317912 kb
Host smart-fcdf1b0d-b556-45ae-9f2b-4d880a61120e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=758245255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.758245255
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3475188524
Short name T1277
Test name
Test status
Simulation time 14712554 ps
CPU time 0.99 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:44 PM PDT 24
Peak memory 211592 kb
Host smart-14b1372b-be46-49c0-b09d-d4a637bac926
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475188524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3475188524
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4139143829
Short name T1391
Test name
Test status
Simulation time 16869389 ps
CPU time 0.99 seconds
Started Mar 19 03:21:04 PM PDT 24
Finished Mar 19 03:21:05 PM PDT 24
Peak memory 212660 kb
Host smart-6248a535-2bb5-4ee0-ad00-b84ad837bbc4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139143829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.4139143829
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.151668126
Short name T741
Test name
Test status
Simulation time 27585054 ps
CPU time 1.03 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:18 PM PDT 24
Peak memory 209608 kb
Host smart-b1aba3af-428c-4297-a239-8d5d2610c63f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151668126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.151668126
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3460805295
Short name T1628
Test name
Test status
Simulation time 20863143 ps
CPU time 0.98 seconds
Started Mar 19 03:17:51 PM PDT 24
Finished Mar 19 03:17:52 PM PDT 24
Peak memory 209584 kb
Host smart-b0b865b8-802e-4c09-9e4d-622377c7f2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460805295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3460805295
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1214045548
Short name T111
Test name
Test status
Simulation time 532306622 ps
CPU time 12.12 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:17:55 PM PDT 24
Peak memory 217976 kb
Host smart-7a23b3cd-256e-4364-8acf-91b100bb4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214045548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1214045548
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3467471555
Short name T839
Test name
Test status
Simulation time 561603675 ps
CPU time 11.43 seconds
Started Mar 19 03:21:14 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 217944 kb
Host smart-5e3bb680-d905-4d5d-a960-b79106819e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467471555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3467471555
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1722553529
Short name T1514
Test name
Test status
Simulation time 691349041 ps
CPU time 8 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:17:49 PM PDT 24
Peak memory 209460 kb
Host smart-528496e6-ba97-4139-ad02-167a8d917376
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722553529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1722553529
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2747414703
Short name T28
Test name
Test status
Simulation time 1115357820 ps
CPU time 8.68 seconds
Started Mar 19 03:21:07 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 209460 kb
Host smart-9b23ab00-3351-4621-ab66-d76ec8b1143a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747414703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2747414703
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2986117502
Short name T1560
Test name
Test status
Simulation time 59799311 ps
CPU time 1.72 seconds
Started Mar 19 03:17:40 PM PDT 24
Finished Mar 19 03:17:42 PM PDT 24
Peak memory 221392 kb
Host smart-39b8597e-0e9e-47db-9ae9-4c1553aae9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986117502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2986117502
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3117440388
Short name T1602
Test name
Test status
Simulation time 148980483 ps
CPU time 2.09 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:11 PM PDT 24
Peak memory 218020 kb
Host smart-edc0e7e1-9db8-4e09-9223-8ae608a5d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117440388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3117440388
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1357808408
Short name T419
Test name
Test status
Simulation time 274966449 ps
CPU time 10.64 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:22 PM PDT 24
Peak memory 226068 kb
Host smart-c69a28ce-ab05-4637-8ecf-8dfbf679d106
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357808408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1357808408
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.439013690
Short name T961
Test name
Test status
Simulation time 789464922 ps
CPU time 13.49 seconds
Started Mar 19 03:17:49 PM PDT 24
Finished Mar 19 03:18:03 PM PDT 24
Peak memory 225488 kb
Host smart-ac219370-59f1-4833-9feb-6782442ebd98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439013690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.439013690
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2128786060
Short name T1650
Test name
Test status
Simulation time 3480304660 ps
CPU time 16.06 seconds
Started Mar 19 03:17:49 PM PDT 24
Finished Mar 19 03:18:05 PM PDT 24
Peak memory 218084 kb
Host smart-2436a44c-e75e-4f1b-a7ee-debaba131897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128786060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2128786060
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.597432769
Short name T1562
Test name
Test status
Simulation time 1116284520 ps
CPU time 9.53 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:21:20 PM PDT 24
Peak memory 217880 kb
Host smart-491c886f-0f37-4d1d-850f-cdd7e2440921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597432769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.597432769
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1537208
Short name T1467
Test name
Test status
Simulation time 1057831366 ps
CPU time 11.27 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 217844 kb
Host smart-d8c38496-e070-41f8-9006-73770b6184bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.1537208
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4187136110
Short name T394
Test name
Test status
Simulation time 332243669 ps
CPU time 6.53 seconds
Started Mar 19 03:17:51 PM PDT 24
Finished Mar 19 03:17:57 PM PDT 24
Peak memory 217892 kb
Host smart-3c6a4169-4c9f-4efd-af65-671262c8c9c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187136110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4187136110
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1926461489
Short name T180
Test name
Test status
Simulation time 1392835381 ps
CPU time 8.26 seconds
Started Mar 19 03:17:42 PM PDT 24
Finished Mar 19 03:17:50 PM PDT 24
Peak memory 224740 kb
Host smart-74ab9133-945f-4fbb-a6a3-6422c4f70310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926461489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1926461489
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.247613454
Short name T1248
Test name
Test status
Simulation time 285976087 ps
CPU time 6.98 seconds
Started Mar 19 03:21:12 PM PDT 24
Finished Mar 19 03:21:19 PM PDT 24
Peak memory 223968 kb
Host smart-5865e7bd-86ce-4154-baff-61554eada55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247613454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.247613454
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3241556008
Short name T726
Test name
Test status
Simulation time 40314837 ps
CPU time 1.68 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 217672 kb
Host smart-55c7899a-c889-41c9-bcb2-281123a602a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241556008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3241556008
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.564863859
Short name T1001
Test name
Test status
Simulation time 14987309 ps
CPU time 1.23 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:13 PM PDT 24
Peak memory 212060 kb
Host smart-1798e030-6dc5-4f94-aaba-9a4cb4aa588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564863859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.564863859
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2271637673
Short name T334
Test name
Test status
Simulation time 4442073353 ps
CPU time 38.19 seconds
Started Mar 19 03:17:41 PM PDT 24
Finished Mar 19 03:18:19 PM PDT 24
Peak memory 248240 kb
Host smart-ea938602-530d-4650-9e99-c7fab1fc13fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271637673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2271637673
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.86447766
Short name T1383
Test name
Test status
Simulation time 2969195376 ps
CPU time 20.23 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:37 PM PDT 24
Peak memory 250896 kb
Host smart-7d28a5aa-50eb-45b7-89fa-85619e871df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86447766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.86447766
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1406698528
Short name T191
Test name
Test status
Simulation time 425422096 ps
CPU time 3.45 seconds
Started Mar 19 03:17:45 PM PDT 24
Finished Mar 19 03:17:48 PM PDT 24
Peak memory 222280 kb
Host smart-69a03351-e842-485a-8f20-66612155af9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406698528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1406698528
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.532067664
Short name T554
Test name
Test status
Simulation time 87441281 ps
CPU time 7.19 seconds
Started Mar 19 03:21:15 PM PDT 24
Finished Mar 19 03:21:22 PM PDT 24
Peak memory 247096 kb
Host smart-19b141a5-c7da-4501-b38c-c519350edc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532067664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.532067664
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.235468212
Short name T26
Test name
Test status
Simulation time 37744765396 ps
CPU time 350.45 seconds
Started Mar 19 03:17:50 PM PDT 24
Finished Mar 19 03:23:41 PM PDT 24
Peak memory 276500 kb
Host smart-37c2a92c-999f-494d-bb16-7a1c857db6d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235468212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.235468212
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2807516440
Short name T1494
Test name
Test status
Simulation time 15718869073 ps
CPU time 144.57 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:23:35 PM PDT 24
Peak memory 278484 kb
Host smart-faf327db-9718-40de-ba28-d69f0e3037fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807516440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2807516440
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1840399450
Short name T1223
Test name
Test status
Simulation time 23025355 ps
CPU time 0.87 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:10 PM PDT 24
Peak memory 211544 kb
Host smart-e8001d17-7ad5-40cd-ad66-9052f2dfd46a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840399450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1840399450
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.563868719
Short name T1538
Test name
Test status
Simulation time 76966538 ps
CPU time 1 seconds
Started Mar 19 03:17:43 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 211560 kb
Host smart-9ecd9b1f-050c-4cdb-af4a-2f2e104ea82b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563868719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.563868719
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.103816757
Short name T372
Test name
Test status
Simulation time 35051519 ps
CPU time 0.92 seconds
Started Mar 19 03:19:09 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 209472 kb
Host smart-e89a9842-3c2e-498b-87c9-5fe313be479c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103816757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.103816757
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3562975676
Short name T934
Test name
Test status
Simulation time 118772900 ps
CPU time 1.39 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:15:51 PM PDT 24
Peak memory 209584 kb
Host smart-1cc14546-2772-4b69-b524-e0c3012b32bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562975676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3562975676
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2213436239
Short name T286
Test name
Test status
Simulation time 32394982 ps
CPU time 0.87 seconds
Started Mar 19 03:19:05 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 209360 kb
Host smart-09011b17-fa1c-4c18-911b-b55b01f66b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213436239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2213436239
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2395213068
Short name T1225
Test name
Test status
Simulation time 13107655 ps
CPU time 0.99 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:15:50 PM PDT 24
Peak memory 209484 kb
Host smart-95c27c9c-0242-4c92-95d9-17d25e0870d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395213068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2395213068
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.341625080
Short name T466
Test name
Test status
Simulation time 486603956 ps
CPU time 14.22 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:16:05 PM PDT 24
Peak memory 226048 kb
Host smart-dfa2f20a-1087-4e73-9d1d-7233aff7f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341625080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.341625080
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.602307061
Short name T41
Test name
Test status
Simulation time 625746471 ps
CPU time 17.07 seconds
Started Mar 19 03:19:05 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 217928 kb
Host smart-b6488f55-c8c9-473b-9e88-09a506e789ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602307061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.602307061
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1644624602
Short name T894
Test name
Test status
Simulation time 875308242 ps
CPU time 20.41 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:38 PM PDT 24
Peak memory 209480 kb
Host smart-f7547d3e-6696-4161-b3e6-b66c27936789
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644624602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1644624602
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3549868280
Short name T674
Test name
Test status
Simulation time 747074252 ps
CPU time 3.73 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:55 PM PDT 24
Peak memory 216820 kb
Host smart-14fb78a7-f7a2-41ba-8688-bb87c1a118eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549868280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3549868280
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1323879958
Short name T673
Test name
Test status
Simulation time 1939567949 ps
CPU time 48.84 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:16:40 PM PDT 24
Peak memory 218012 kb
Host smart-7f762f11-a5b5-466e-9da5-4beef086ca1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323879958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1323879958
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.965413605
Short name T544
Test name
Test status
Simulation time 2525519078 ps
CPU time 70.49 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:20:31 PM PDT 24
Peak memory 218368 kb
Host smart-a7d68ccf-6623-4655-9b40-f13e397486a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965413605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.965413605
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2028212841
Short name T671
Test name
Test status
Simulation time 926393337 ps
CPU time 22.53 seconds
Started Mar 19 03:19:11 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 217680 kb
Host smart-81e0091e-0855-43ca-9e83-0965355d1f7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028212841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
028212841
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3296218625
Short name T305
Test name
Test status
Simulation time 340820557 ps
CPU time 5.16 seconds
Started Mar 19 03:15:47 PM PDT 24
Finished Mar 19 03:15:53 PM PDT 24
Peak memory 217072 kb
Host smart-b0460019-73e5-4d5c-9bbb-809270e5717d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296218625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
296218625
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.425913106
Short name T275
Test name
Test status
Simulation time 745019062 ps
CPU time 9.72 seconds
Started Mar 19 03:15:52 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 218004 kb
Host smart-059546cb-56ef-4c78-8f77-ff4711c06633
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425913106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.425913106
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.883748349
Short name T1471
Test name
Test status
Simulation time 1934431107 ps
CPU time 11.82 seconds
Started Mar 19 03:19:07 PM PDT 24
Finished Mar 19 03:19:19 PM PDT 24
Peak memory 217936 kb
Host smart-1d253410-ce87-46ed-b280-50747fb1ba38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883748349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.883748349
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.22015532
Short name T606
Test name
Test status
Simulation time 850003365 ps
CPU time 24.66 seconds
Started Mar 19 03:15:48 PM PDT 24
Finished Mar 19 03:16:13 PM PDT 24
Peak memory 213192 kb
Host smart-2ba7f159-f57f-4dae-9bd7-fc6e268a5b12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22015532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_regwen_during_op.22015532
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.982130295
Short name T668
Test name
Test status
Simulation time 1403590611 ps
CPU time 35.95 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:56 PM PDT 24
Peak memory 213336 kb
Host smart-7a3b1c46-48b0-48d1-a73b-e38919056f7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982130295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.982130295
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1028077802
Short name T1544
Test name
Test status
Simulation time 712669056 ps
CPU time 5.31 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:05 PM PDT 24
Peak memory 213212 kb
Host smart-ee8cd218-7ded-4427-a7f5-551f5c7cece4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028077802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1028077802
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3547495069
Short name T773
Test name
Test status
Simulation time 1165384408 ps
CPU time 4.43 seconds
Started Mar 19 03:15:47 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 213260 kb
Host smart-6c63773e-2d51-4c12-bd82-f6b4d53040f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547495069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3547495069
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2176875662
Short name T565
Test name
Test status
Simulation time 1540188850 ps
CPU time 37.41 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:19:56 PM PDT 24
Peak memory 270640 kb
Host smart-74128827-9127-4cec-a6e6-03845ca9dc01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176875662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2176875662
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2333286760
Short name T489
Test name
Test status
Simulation time 1149957555 ps
CPU time 60.93 seconds
Started Mar 19 03:15:48 PM PDT 24
Finished Mar 19 03:16:49 PM PDT 24
Peak memory 268160 kb
Host smart-92b7030f-bf0b-4fe9-bd97-5fb63079294e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333286760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2333286760
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1450099417
Short name T1537
Test name
Test status
Simulation time 326942250 ps
CPU time 7 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 224208 kb
Host smart-ee91a122-83d6-4c13-8309-129f9ad638e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450099417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1450099417
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1482979664
Short name T898
Test name
Test status
Simulation time 653851390 ps
CPU time 15.82 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 250900 kb
Host smart-4a3167d0-8a6d-489e-8a48-7fc2192ce240
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482979664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1482979664
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2623994108
Short name T857
Test name
Test status
Simulation time 81924433 ps
CPU time 2.07 seconds
Started Mar 19 03:19:04 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 218048 kb
Host smart-244b66af-dbd9-47ba-8139-8114468f08b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623994108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2623994108
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.757441632
Short name T1474
Test name
Test status
Simulation time 414215868 ps
CPU time 3.48 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:15:54 PM PDT 24
Peak memory 221836 kb
Host smart-e24073cd-ff81-42fb-bb34-0c1c25efee20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757441632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.757441632
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.144080005
Short name T203
Test name
Test status
Simulation time 342432748 ps
CPU time 23.48 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:13 PM PDT 24
Peak memory 214520 kb
Host smart-3e971a37-ae7f-4d16-9075-5ac8362f1688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144080005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.144080005
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3342981613
Short name T190
Test name
Test status
Simulation time 1148908583 ps
CPU time 20.03 seconds
Started Mar 19 03:19:03 PM PDT 24
Finished Mar 19 03:19:23 PM PDT 24
Peak memory 214428 kb
Host smart-bcc2f4bb-5e4e-4a43-96c9-fd2a90de1ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342981613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3342981613
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1171209286
Short name T622
Test name
Test status
Simulation time 482217806 ps
CPU time 14.97 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:04 PM PDT 24
Peak memory 218908 kb
Host smart-ede62dfd-e949-40d3-a216-a42d44980ece
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171209286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1171209286
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.144654140
Short name T1207
Test name
Test status
Simulation time 534708619 ps
CPU time 10.74 seconds
Started Mar 19 03:19:08 PM PDT 24
Finished Mar 19 03:19:19 PM PDT 24
Peak memory 226024 kb
Host smart-6e319a6d-4cec-4678-90c9-34ccf71fbfe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144654140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.144654140
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3051831096
Short name T816
Test name
Test status
Simulation time 982612659 ps
CPU time 9.64 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:16:01 PM PDT 24
Peak memory 217892 kb
Host smart-94e7fe9c-b154-4a68-9b75-c85fe6123b87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051831096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3051831096
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3788429989
Short name T724
Test name
Test status
Simulation time 1662586451 ps
CPU time 10.8 seconds
Started Mar 19 03:19:23 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 217896 kb
Host smart-c2f0b341-9098-4951-8027-bb8441e821ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788429989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3788429989
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1666409591
Short name T925
Test name
Test status
Simulation time 1380062200 ps
CPU time 13.5 seconds
Started Mar 19 03:19:11 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 217964 kb
Host smart-174de8dc-4b08-439c-8b25-c5c2e9556d72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666409591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
666409591
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.189023727
Short name T672
Test name
Test status
Simulation time 1758800514 ps
CPU time 7.67 seconds
Started Mar 19 03:15:52 PM PDT 24
Finished Mar 19 03:15:59 PM PDT 24
Peak memory 217280 kb
Host smart-ab20be4c-c34d-4b39-9cf4-f14cbfc06e96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189023727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.189023727
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4191574283
Short name T733
Test name
Test status
Simulation time 503125453 ps
CPU time 12.63 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 224480 kb
Host smart-15b6b290-9a9e-42c5-8562-fffc24706d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191574283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4191574283
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4201890052
Short name T1315
Test name
Test status
Simulation time 1993117970 ps
CPU time 10.3 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:19:20 PM PDT 24
Peak memory 224644 kb
Host smart-0ea047ba-198f-4da4-9525-e21284b9d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201890052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4201890052
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2004560942
Short name T252
Test name
Test status
Simulation time 84885033 ps
CPU time 1.79 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 213516 kb
Host smart-3a7a58bd-f438-4e94-8c12-60ee59c972de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004560942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2004560942
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3248460985
Short name T1167
Test name
Test status
Simulation time 62067077 ps
CPU time 2.83 seconds
Started Mar 19 03:19:12 PM PDT 24
Finished Mar 19 03:19:15 PM PDT 24
Peak memory 214436 kb
Host smart-5735cbd2-c828-4cb8-93d8-d206eef0a06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248460985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3248460985
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1933479441
Short name T317
Test name
Test status
Simulation time 451470512 ps
CPU time 19.52 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 250776 kb
Host smart-7c271a4d-0f15-4bad-8399-2d8102e3f28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933479441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1933479441
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.37128298
Short name T292
Test name
Test status
Simulation time 1024397312 ps
CPU time 26.83 seconds
Started Mar 19 03:15:48 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 250720 kb
Host smart-cb9739cf-400d-4ae4-b25c-37a8b9a5450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37128298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.37128298
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2997393484
Short name T879
Test name
Test status
Simulation time 224799384 ps
CPU time 5.69 seconds
Started Mar 19 03:15:48 PM PDT 24
Finished Mar 19 03:15:54 PM PDT 24
Peak memory 246260 kb
Host smart-5544a780-a99d-435b-96bc-d9283eac5afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997393484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2997393484
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4096632250
Short name T1363
Test name
Test status
Simulation time 83338957 ps
CPU time 6.92 seconds
Started Mar 19 03:19:02 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 250300 kb
Host smart-43e5f4e9-d2fe-4fe7-9f8c-c9b0dab4b9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096632250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4096632250
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2889326384
Short name T631
Test name
Test status
Simulation time 84577310242 ps
CPU time 212.36 seconds
Started Mar 19 03:15:52 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 270000 kb
Host smart-177f5f2f-fde0-4480-ae0d-f2dafcd70322
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889326384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2889326384
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3982061133
Short name T1086
Test name
Test status
Simulation time 2435126396 ps
CPU time 75.67 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:20:25 PM PDT 24
Peak memory 219660 kb
Host smart-07c783bc-7785-4df8-8a5a-17318d19a15c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982061133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3982061133
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2821788524
Short name T1095
Test name
Test status
Simulation time 13361896 ps
CPU time 0.89 seconds
Started Mar 19 03:19:05 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 211504 kb
Host smart-c9b84720-f168-467d-a00f-df3236ef2c6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821788524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2821788524
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4293800459
Short name T975
Test name
Test status
Simulation time 52554990 ps
CPU time 0.99 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 212636 kb
Host smart-e61bf570-2ebd-4c9d-a0bd-ae7926f440c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293800459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.4293800459
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1784618957
Short name T1238
Test name
Test status
Simulation time 55155686 ps
CPU time 1 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 209588 kb
Host smart-a916156a-204c-4070-9306-b3ee6eed1736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784618957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1784618957
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.265913222
Short name T465
Test name
Test status
Simulation time 26114323 ps
CPU time 1.01 seconds
Started Mar 19 03:19:26 PM PDT 24
Finished Mar 19 03:19:27 PM PDT 24
Peak memory 209604 kb
Host smart-750f82e0-5d4a-4d06-8c40-1b24be6b2d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265913222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.265913222
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2038129869
Short name T1343
Test name
Test status
Simulation time 34311325 ps
CPU time 0.79 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:19:11 PM PDT 24
Peak memory 209360 kb
Host smart-fbba1d05-172d-45ec-b223-f9fec2dcdc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038129869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2038129869
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2422142783
Short name T1459
Test name
Test status
Simulation time 40634279 ps
CPU time 0.79 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 209344 kb
Host smart-f8366614-9146-4618-aa07-168fbb9ea042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422142783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2422142783
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2851260925
Short name T1125
Test name
Test status
Simulation time 639446631 ps
CPU time 15.29 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:05 PM PDT 24
Peak memory 217952 kb
Host smart-afd6498a-e753-417e-9fbb-eb791349c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851260925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2851260925
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4131257975
Short name T1134
Test name
Test status
Simulation time 394075623 ps
CPU time 13.18 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 226192 kb
Host smart-16796ee5-4735-44e0-94c4-af29ecd36cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131257975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4131257975
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.495192847
Short name T1103
Test name
Test status
Simulation time 894887775 ps
CPU time 5.82 seconds
Started Mar 19 03:19:08 PM PDT 24
Finished Mar 19 03:19:14 PM PDT 24
Peak memory 216964 kb
Host smart-56a3ccaf-9c35-4e91-8acb-c226df094132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495192847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.495192847
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.834907582
Short name T906
Test name
Test status
Simulation time 305437207 ps
CPU time 4.48 seconds
Started Mar 19 03:15:52 PM PDT 24
Finished Mar 19 03:15:56 PM PDT 24
Peak memory 209424 kb
Host smart-19d8fde2-3879-4f8b-b0b5-9e2111aa9b06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834907582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.834907582
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1901155597
Short name T869
Test name
Test status
Simulation time 14647737888 ps
CPU time 100.42 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:21:02 PM PDT 24
Peak memory 219020 kb
Host smart-884f3e81-9e3f-484c-b4c6-4436dba12c88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901155597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1901155597
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.920965174
Short name T1613
Test name
Test status
Simulation time 2165858431 ps
CPU time 36.65 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:16:28 PM PDT 24
Peak memory 217996 kb
Host smart-4ea18de8-d982-43d3-ae48-1e4656cdf04c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920965174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.920965174
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2279175359
Short name T1196
Test name
Test status
Simulation time 805824347 ps
CPU time 2.96 seconds
Started Mar 19 03:19:14 PM PDT 24
Finished Mar 19 03:19:17 PM PDT 24
Peak memory 217000 kb
Host smart-c6294cb8-c4d3-4a6b-bd4a-7b020f8ed863
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279175359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
279175359
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2309329671
Short name T1012
Test name
Test status
Simulation time 324293348 ps
CPU time 3.91 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:54 PM PDT 24
Peak memory 217220 kb
Host smart-28d25135-c183-4bc3-9840-de971550d751
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309329671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
309329671
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2751494274
Short name T1289
Test name
Test status
Simulation time 416791568 ps
CPU time 12.33 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:16:04 PM PDT 24
Peak memory 218004 kb
Host smart-2317f219-ec11-4297-b3b7-b5c0bb3faad6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751494274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2751494274
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2796749678
Short name T562
Test name
Test status
Simulation time 1497686869 ps
CPU time 11.14 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:29 PM PDT 24
Peak memory 217936 kb
Host smart-4d41f579-a3e4-439d-861a-2a22ab1354ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796749678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2796749678
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.334081161
Short name T912
Test name
Test status
Simulation time 1620629857 ps
CPU time 17.24 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 213176 kb
Host smart-c4639bfb-9d50-41ea-892f-1cae64ff270d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334081161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.334081161
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3749627524
Short name T996
Test name
Test status
Simulation time 1379746573 ps
CPU time 18.83 seconds
Started Mar 19 03:19:23 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 213272 kb
Host smart-b80355a6-3ce6-4210-be63-c034d76a61b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749627524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3749627524
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3235986638
Short name T759
Test name
Test status
Simulation time 849222496 ps
CPU time 4.21 seconds
Started Mar 19 03:19:16 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 213512 kb
Host smart-af7ee704-49a5-43e9-be7f-090374230011
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235986638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3235986638
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3435295193
Short name T1181
Test name
Test status
Simulation time 1535421782 ps
CPU time 7.12 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:58 PM PDT 24
Peak memory 213636 kb
Host smart-3e6ef296-e2f8-43af-94f0-d57014dbcc19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435295193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3435295193
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1502819881
Short name T942
Test name
Test status
Simulation time 977779334 ps
CPU time 41.88 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:31 PM PDT 24
Peak memory 250892 kb
Host smart-f05e5e9d-53fa-4c13-8a18-14978674f3b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502819881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1502819881
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.891674886
Short name T1054
Test name
Test status
Simulation time 3589978808 ps
CPU time 65.48 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 276164 kb
Host smart-925bb271-4573-4a67-8671-1c85d2bb56a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891674886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.891674886
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1197398599
Short name T937
Test name
Test status
Simulation time 634902929 ps
CPU time 15.63 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 250876 kb
Host smart-b1dd6d06-4225-4683-8198-951331811437
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197398599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1197398599
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.352858474
Short name T409
Test name
Test status
Simulation time 4611809590 ps
CPU time 19.9 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:16:10 PM PDT 24
Peak memory 226336 kb
Host smart-237cc66d-464b-40a9-abfb-375881b6a2ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352858474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.352858474
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2575696058
Short name T1062
Test name
Test status
Simulation time 198404597 ps
CPU time 3.02 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:54 PM PDT 24
Peak memory 221792 kb
Host smart-3f3c5b10-80e4-4a33-a927-b3811f86d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575696058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2575696058
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2807453979
Short name T628
Test name
Test status
Simulation time 114878617 ps
CPU time 3.49 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:18 PM PDT 24
Peak memory 222128 kb
Host smart-abf3c6af-e1ca-4513-bab5-c28c5f75553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807453979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2807453979
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3894781135
Short name T696
Test name
Test status
Simulation time 245037983 ps
CPU time 7.41 seconds
Started Mar 19 03:15:49 PM PDT 24
Finished Mar 19 03:15:58 PM PDT 24
Peak memory 217652 kb
Host smart-8ba61fc6-e174-41e3-aab7-28b65acda15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894781135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3894781135
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.4224870005
Short name T1287
Test name
Test status
Simulation time 374702879 ps
CPU time 14.27 seconds
Started Mar 19 03:19:07 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 217652 kb
Host smart-8852abbb-a0b1-4e8e-8a57-c093e4dacfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224870005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.4224870005
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.119794962
Short name T734
Test name
Test status
Simulation time 315889987 ps
CPU time 10.83 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 217904 kb
Host smart-64657d63-7728-4e0b-a155-3d609cf0fd51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119794962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.119794962
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2852629523
Short name T1291
Test name
Test status
Simulation time 1487478629 ps
CPU time 15.81 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:31 PM PDT 24
Peak memory 225584 kb
Host smart-01a83ce0-58a9-4071-beba-ccf8f2983d69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852629523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2852629523
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1656400429
Short name T359
Test name
Test status
Simulation time 308706990 ps
CPU time 9.31 seconds
Started Mar 19 03:19:08 PM PDT 24
Finished Mar 19 03:19:18 PM PDT 24
Peak memory 217924 kb
Host smart-2451027f-5301-4f63-a9ae-d675cb874703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656400429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1656400429
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2477060911
Short name T1616
Test name
Test status
Simulation time 495567863 ps
CPU time 11.46 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 217808 kb
Host smart-ed12209a-14cc-4654-9c98-f1bbf568aa3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477060911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2477060911
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3715763595
Short name T57
Test name
Test status
Simulation time 327280348 ps
CPU time 12.43 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 217888 kb
Host smart-83728419-b26b-42fa-8867-a90dadd8064c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715763595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
715763595
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.890522955
Short name T1393
Test name
Test status
Simulation time 332428887 ps
CPU time 11.97 seconds
Started Mar 19 03:19:09 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 217920 kb
Host smart-ca3e7d38-0ec1-45e2-9967-b9d571212746
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890522955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.890522955
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2372517872
Short name T752
Test name
Test status
Simulation time 187717174 ps
CPU time 8.83 seconds
Started Mar 19 03:15:52 PM PDT 24
Finished Mar 19 03:16:01 PM PDT 24
Peak memory 225352 kb
Host smart-73e61454-b862-4026-99e4-adfb0b4dc6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372517872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2372517872
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3818828990
Short name T1282
Test name
Test status
Simulation time 345602696 ps
CPU time 8.48 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 225260 kb
Host smart-81c1ea82-8c07-4387-b9b3-f2222d00329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818828990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3818828990
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1965558930
Short name T467
Test name
Test status
Simulation time 35314100 ps
CPU time 1.89 seconds
Started Mar 19 03:15:48 PM PDT 24
Finished Mar 19 03:15:50 PM PDT 24
Peak memory 217796 kb
Host smart-760de423-72ee-4d46-ac1c-66c851bca092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965558930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1965558930
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3011526424
Short name T293
Test name
Test status
Simulation time 53147010 ps
CPU time 2.13 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:19:12 PM PDT 24
Peak memory 213180 kb
Host smart-25c1f437-6720-4fad-b534-98e529308b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011526424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3011526424
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3341855318
Short name T701
Test name
Test status
Simulation time 811237220 ps
CPU time 19.74 seconds
Started Mar 19 03:15:48 PM PDT 24
Finished Mar 19 03:16:08 PM PDT 24
Peak memory 249512 kb
Host smart-0e880f70-f6af-4a00-b0aa-b89182122579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341855318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3341855318
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4138637177
Short name T639
Test name
Test status
Simulation time 654769997 ps
CPU time 24.65 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 250964 kb
Host smart-d8efebc2-b310-4701-8f57-22440f97e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138637177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4138637177
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2261322299
Short name T968
Test name
Test status
Simulation time 310175793 ps
CPU time 7.72 seconds
Started Mar 19 03:19:06 PM PDT 24
Finished Mar 19 03:19:14 PM PDT 24
Peak memory 247028 kb
Host smart-2649050a-4ad4-492a-8c24-f282e591be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261322299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2261322299
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3191799987
Short name T862
Test name
Test status
Simulation time 258268375 ps
CPU time 6.68 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:58 PM PDT 24
Peak memory 245900 kb
Host smart-dacc99ef-85b2-4247-a8f2-17cb7ab14c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191799987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3191799987
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1631907983
Short name T612
Test name
Test status
Simulation time 26796261866 ps
CPU time 323.82 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:24:43 PM PDT 24
Peak memory 255056 kb
Host smart-420b33cf-d5fc-4d91-9c99-a277dd4b30d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631907983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1631907983
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.730604950
Short name T64
Test name
Test status
Simulation time 22375858529 ps
CPU time 135.26 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:18:06 PM PDT 24
Peak memory 251040 kb
Host smart-0dcb630e-828c-4a09-9126-5c0c4bf8bb76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730604950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.730604950
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.943933520
Short name T1355
Test name
Test status
Simulation time 54118389688 ps
CPU time 475.26 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:23:46 PM PDT 24
Peak memory 271620 kb
Host smart-91e26b36-5d70-4bb1-81cf-99924750a092
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=943933520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.943933520
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2920131186
Short name T1273
Test name
Test status
Simulation time 12352794 ps
CPU time 0.86 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:19:11 PM PDT 24
Peak memory 211556 kb
Host smart-9807a10b-6acb-463b-b92e-e344cee3b2ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920131186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2920131186
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.672507803
Short name T1118
Test name
Test status
Simulation time 35320963 ps
CPU time 0.94 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 211488 kb
Host smart-ef86be17-e9b0-4a0c-b852-90b00bf98ac2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672507803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.672507803
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2293912634
Short name T344
Test name
Test status
Simulation time 42860585 ps
CPU time 0.97 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 209592 kb
Host smart-f5f364e1-eecb-4ce1-a874-eb265496d0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293912634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2293912634
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3405003686
Short name T316
Test name
Test status
Simulation time 17707791 ps
CPU time 0.9 seconds
Started Mar 19 03:19:26 PM PDT 24
Finished Mar 19 03:19:28 PM PDT 24
Peak memory 209588 kb
Host smart-facf8bfd-596e-46ce-9795-c2250d1030d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405003686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3405003686
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1827108576
Short name T271
Test name
Test status
Simulation time 13426790 ps
CPU time 1 seconds
Started Mar 19 03:19:09 PM PDT 24
Finished Mar 19 03:19:10 PM PDT 24
Peak memory 209476 kb
Host smart-86bc7096-1ab5-4311-80cd-38fa6822c722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827108576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1827108576
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2733371681
Short name T1143
Test name
Test status
Simulation time 364432688 ps
CPU time 16.07 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:35 PM PDT 24
Peak memory 217976 kb
Host smart-2a45dc33-3955-4285-aa75-5cd15f85435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733371681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2733371681
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3772880545
Short name T860
Test name
Test status
Simulation time 399185039 ps
CPU time 15.03 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 217928 kb
Host smart-f065ca02-2ecd-408b-ad8b-07b13607b25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772880545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3772880545
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1494981821
Short name T1646
Test name
Test status
Simulation time 2685487681 ps
CPU time 15.12 seconds
Started Mar 19 03:16:04 PM PDT 24
Finished Mar 19 03:16:20 PM PDT 24
Peak memory 217472 kb
Host smart-4fff77b2-1ea2-45d8-8cb5-8a1cead3b82f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494981821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1494981821
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.315946234
Short name T1261
Test name
Test status
Simulation time 274246595 ps
CPU time 8.18 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:25 PM PDT 24
Peak memory 209512 kb
Host smart-9b50681c-a66c-4921-845c-bd8bb3df34af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315946234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.315946234
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2594376178
Short name T866
Test name
Test status
Simulation time 7580250345 ps
CPU time 31.68 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 219044 kb
Host smart-922244e5-e6b2-4e2a-b633-092d47af824e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594376178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2594376178
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.759019045
Short name T1565
Test name
Test status
Simulation time 1509579109 ps
CPU time 43.41 seconds
Started Mar 19 03:15:58 PM PDT 24
Finished Mar 19 03:16:42 PM PDT 24
Peak memory 217932 kb
Host smart-6541f578-ab2a-4626-850f-3f1d5bd6c3e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759019045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.759019045
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3913760720
Short name T347
Test name
Test status
Simulation time 2604005225 ps
CPU time 7.98 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:11 PM PDT 24
Peak memory 217376 kb
Host smart-79746a2e-be83-4b72-b780-9a91bc1b9fe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913760720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
913760720
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1086669658
Short name T970
Test name
Test status
Simulation time 249236631 ps
CPU time 7.97 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:15:59 PM PDT 24
Peak memory 217940 kb
Host smart-ee2c6afa-4b03-437c-b609-7d6d88b19398
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086669658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1086669658
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.509531021
Short name T1582
Test name
Test status
Simulation time 1126600074 ps
CPU time 8.61 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 217932 kb
Host smart-f36c4787-65ba-42cc-b2ed-df53e2197ba2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509531021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.509531021
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2323282685
Short name T326
Test name
Test status
Simulation time 3609890410 ps
CPU time 31.32 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:19:51 PM PDT 24
Peak memory 214092 kb
Host smart-975ecfc4-7269-431f-a2e7-18498776a2ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323282685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2323282685
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4131177750
Short name T475
Test name
Test status
Simulation time 9817814212 ps
CPU time 27.6 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:27 PM PDT 24
Peak memory 213972 kb
Host smart-40717370-77f7-4f40-b97d-23f962e31ebe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131177750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4131177750
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.381904803
Short name T965
Test name
Test status
Simulation time 144218854 ps
CPU time 2.47 seconds
Started Mar 19 03:15:58 PM PDT 24
Finished Mar 19 03:16:01 PM PDT 24
Peak memory 212960 kb
Host smart-d31f6763-7f63-475f-ba36-f5eef8ea3696
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381904803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.381904803
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3821034391
Short name T1657
Test name
Test status
Simulation time 1600438001 ps
CPU time 7.15 seconds
Started Mar 19 03:19:16 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 213552 kb
Host smart-66673c2a-9b8a-42b6-988f-4ce99c6613a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821034391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3821034391
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1660716378
Short name T1227
Test name
Test status
Simulation time 9182282352 ps
CPU time 54.81 seconds
Started Mar 19 03:15:52 PM PDT 24
Finished Mar 19 03:16:47 PM PDT 24
Peak memory 268592 kb
Host smart-aa1ddd4e-e598-4c1c-ac64-36aeb8ee171a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660716378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1660716378
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.4265154820
Short name T448
Test name
Test status
Simulation time 3967009909 ps
CPU time 29.3 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:50 PM PDT 24
Peak memory 251056 kb
Host smart-7c05cd5b-d872-4c43-92e7-933b572fac9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265154820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.4265154820
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1159006129
Short name T1662
Test name
Test status
Simulation time 584988365 ps
CPU time 9.63 seconds
Started Mar 19 03:15:58 PM PDT 24
Finished Mar 19 03:16:08 PM PDT 24
Peak memory 222624 kb
Host smart-ba4d99a3-b9d0-4a0f-a18e-9c7b59b95398
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159006129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1159006129
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2646288383
Short name T1037
Test name
Test status
Simulation time 1422036254 ps
CPU time 17.58 seconds
Started Mar 19 03:19:14 PM PDT 24
Finished Mar 19 03:19:32 PM PDT 24
Peak memory 244144 kb
Host smart-53a13948-d144-4d23-9070-2060183d15c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646288383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2646288383
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2262033161
Short name T261
Test name
Test status
Simulation time 200461878 ps
CPU time 2.36 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:15:54 PM PDT 24
Peak memory 221864 kb
Host smart-e5e15185-b6ad-4df4-a333-142ae1dbe233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262033161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2262033161
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2314037934
Short name T325
Test name
Test status
Simulation time 28746775 ps
CPU time 2.05 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:17 PM PDT 24
Peak memory 221532 kb
Host smart-9b6f7bb7-9612-42d8-b681-15f1f5d892ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314037934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2314037934
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1066965838
Short name T204
Test name
Test status
Simulation time 800575096 ps
CPU time 13.44 seconds
Started Mar 19 03:15:50 PM PDT 24
Finished Mar 19 03:16:04 PM PDT 24
Peak memory 217884 kb
Host smart-f4509ab7-1cfd-4262-b096-6509756cf32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066965838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1066965838
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1680876135
Short name T74
Test name
Test status
Simulation time 1691730240 ps
CPU time 19.52 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:38 PM PDT 24
Peak memory 214340 kb
Host smart-246e81ed-23c8-4a29-a08e-3486d7051295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680876135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1680876135
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3932924512
Short name T803
Test name
Test status
Simulation time 1397591445 ps
CPU time 13.43 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:31 PM PDT 24
Peak memory 218916 kb
Host smart-7e762ae7-1cbd-4be6-bede-ab86a6be2ac4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932924512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3932924512
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.464453071
Short name T512
Test name
Test status
Simulation time 538253964 ps
CPU time 8.53 seconds
Started Mar 19 03:16:00 PM PDT 24
Finished Mar 19 03:16:10 PM PDT 24
Peak memory 226040 kb
Host smart-70363540-b4dd-4974-8347-f2dfb2757f32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464453071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.464453071
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2989534528
Short name T1197
Test name
Test status
Simulation time 1150541253 ps
CPU time 13.12 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 217952 kb
Host smart-6ce301b7-3a04-4af2-9223-9f1127a07d8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989534528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2989534528
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3633441510
Short name T1545
Test name
Test status
Simulation time 357062701 ps
CPU time 10.43 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 217908 kb
Host smart-0a5abc27-fa35-4536-a49f-6b2e42a7c54e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633441510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3633441510
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2927993311
Short name T643
Test name
Test status
Simulation time 239463768 ps
CPU time 6.73 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:11 PM PDT 24
Peak memory 217904 kb
Host smart-79f907c0-8b13-4a02-b667-194364e3049b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927993311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
927993311
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.307168101
Short name T1445
Test name
Test status
Simulation time 260856885 ps
CPU time 9.85 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 217884 kb
Host smart-3f8a13cc-aa2f-406a-8dce-8e0cb6250467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307168101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.307168101
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1418601015
Short name T501
Test name
Test status
Simulation time 5470381704 ps
CPU time 7.68 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:25 PM PDT 24
Peak memory 225200 kb
Host smart-71b8ee92-5415-455f-aa56-0f3e1b4d6faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418601015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1418601015
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2972243232
Short name T530
Test name
Test status
Simulation time 385146396 ps
CPU time 10.37 seconds
Started Mar 19 03:15:53 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 226112 kb
Host smart-686f2cf6-04bf-4bc6-9ecc-d30fd472667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972243232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2972243232
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1279230383
Short name T1487
Test name
Test status
Simulation time 168386216 ps
CPU time 0.96 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:15:52 PM PDT 24
Peak memory 211652 kb
Host smart-f7da64fe-eece-4240-a59e-f1d8db36c15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279230383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1279230383
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2984480667
Short name T1302
Test name
Test status
Simulation time 100833502 ps
CPU time 2.93 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:20 PM PDT 24
Peak memory 214428 kb
Host smart-dbefd571-203f-41c5-ba35-b5ce8e5bc61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984480667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2984480667
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1606419853
Short name T1530
Test name
Test status
Simulation time 159301394 ps
CPU time 20.91 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 249664 kb
Host smart-c4685db5-ebe4-4863-a610-78d7750054ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606419853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1606419853
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.4126877380
Short name T1477
Test name
Test status
Simulation time 165391097 ps
CPU time 21.11 seconds
Started Mar 19 03:15:51 PM PDT 24
Finished Mar 19 03:16:12 PM PDT 24
Peak memory 249652 kb
Host smart-3876713e-154e-43e4-a72c-543eb4440705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126877380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.4126877380
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1599621076
Short name T323
Test name
Test status
Simulation time 65575010 ps
CPU time 6.29 seconds
Started Mar 19 03:15:54 PM PDT 24
Finished Mar 19 03:16:01 PM PDT 24
Peak memory 250844 kb
Host smart-7b8d91d3-6b75-49ad-be8c-4cc6512bef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599621076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1599621076
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.264072309
Short name T1169
Test name
Test status
Simulation time 58320817 ps
CPU time 6.28 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 246852 kb
Host smart-48e160fc-accb-4670-9db4-262de3343c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264072309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.264072309
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4108738517
Short name T65
Test name
Test status
Simulation time 2066985362 ps
CPU time 21.38 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 244052 kb
Host smart-1b1e5c9d-60c1-4c72-9369-f7a408b93da5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108738517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4108738517
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4193735070
Short name T1642
Test name
Test status
Simulation time 2765153206 ps
CPU time 90.43 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:20:49 PM PDT 24
Peak memory 270740 kb
Host smart-388295e4-6602-4ba4-a83e-1a7f1031273f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193735070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4193735070
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1134060750
Short name T327
Test name
Test status
Simulation time 10770983 ps
CPU time 0.85 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:19 PM PDT 24
Peak memory 208316 kb
Host smart-70a2757a-84a7-432b-ace4-2f2f5f59db46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134060750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1134060750
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.136497933
Short name T1664
Test name
Test status
Simulation time 45592325 ps
CPU time 0.97 seconds
Started Mar 19 03:15:54 PM PDT 24
Finished Mar 19 03:15:56 PM PDT 24
Peak memory 211592 kb
Host smart-04775a9f-c519-4a15-8c75-d948110e504c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136497933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.136497933
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.4086821244
Short name T1150
Test name
Test status
Simulation time 27640336 ps
CPU time 0.93 seconds
Started Mar 19 03:19:32 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 209584 kb
Host smart-5af3ac6b-616e-4f8c-a793-c2aa2d4fc138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086821244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.4086821244
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.952069541
Short name T1288
Test name
Test status
Simulation time 70070681 ps
CPU time 1.15 seconds
Started Mar 19 03:16:00 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 209616 kb
Host smart-6c69fd01-5aae-4477-8f01-b7523597af5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952069541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.952069541
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.457804823
Short name T635
Test name
Test status
Simulation time 12445565 ps
CPU time 0.85 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:19:23 PM PDT 24
Peak memory 209408 kb
Host smart-c2505d30-cf91-44eb-9da5-1b06f679cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457804823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.457804823
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.667252395
Short name T1149
Test name
Test status
Simulation time 40737338 ps
CPU time 0.84 seconds
Started Mar 19 03:16:05 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 209352 kb
Host smart-0d53c7c3-3c4a-40c9-afdf-1f93c153d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667252395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.667252395
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1550677616
Short name T1303
Test name
Test status
Simulation time 2049222007 ps
CPU time 8.46 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:26 PM PDT 24
Peak memory 226104 kb
Host smart-0767c0e4-8807-47f8-bc71-476b66676e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550677616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1550677616
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2361863973
Short name T1429
Test name
Test status
Simulation time 1734343524 ps
CPU time 12.24 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 217948 kb
Host smart-a75c16bd-5e75-4a2e-b22a-7554728e125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361863973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2361863973
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.188109345
Short name T1684
Test name
Test status
Simulation time 410309114 ps
CPU time 1.93 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:04 PM PDT 24
Peak memory 209456 kb
Host smart-b5c661a4-b905-4cf4-99f6-f4204bfdd077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188109345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.188109345
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3515219407
Short name T1311
Test name
Test status
Simulation time 2518467754 ps
CPU time 7.48 seconds
Started Mar 19 03:19:25 PM PDT 24
Finished Mar 19 03:19:32 PM PDT 24
Peak memory 217492 kb
Host smart-316f3f6e-bbb2-4ced-808d-390db2fefcab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515219407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3515219407
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1684124859
Short name T1126
Test name
Test status
Simulation time 4530182574 ps
CPU time 20.75 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:25 PM PDT 24
Peak memory 218096 kb
Host smart-9cb92406-d692-43b1-ad3a-86ced2cb0a9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684124859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1684124859
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.4211794324
Short name T1297
Test name
Test status
Simulation time 1447807623 ps
CPU time 46.15 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:20:04 PM PDT 24
Peak memory 217948 kb
Host smart-690fe741-04ce-431a-8b3f-57337b03eb77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211794324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.4211794324
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1180456131
Short name T758
Test name
Test status
Simulation time 491093080 ps
CPU time 1.94 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 217084 kb
Host smart-e2da8fe6-daeb-4b60-a4c1-4c39688b91d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180456131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
180456131
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2194685244
Short name T276
Test name
Test status
Simulation time 340568688 ps
CPU time 8.11 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:10 PM PDT 24
Peak memory 217748 kb
Host smart-e4fd8538-a8e4-40cc-b75c-0da72a3026ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194685244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
194685244
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1330147811
Short name T1027
Test name
Test status
Simulation time 748249122 ps
CPU time 6.77 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 217936 kb
Host smart-ca0874bb-5580-4f6b-9ebe-e7ebf8b8647f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330147811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1330147811
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2888480037
Short name T601
Test name
Test status
Simulation time 631459764 ps
CPU time 5.33 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:19:26 PM PDT 24
Peak memory 217804 kb
Host smart-bdf7b8de-1865-48fc-9681-eb32d17b91e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888480037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2888480037
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1628563596
Short name T1215
Test name
Test status
Simulation time 1302205216 ps
CPU time 17.88 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 213160 kb
Host smart-c1c2b167-ee71-41c9-8a0c-0de43bfaba78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628563596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1628563596
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2066631726
Short name T1480
Test name
Test status
Simulation time 3686984314 ps
CPU time 27.25 seconds
Started Mar 19 03:19:35 PM PDT 24
Finished Mar 19 03:20:02 PM PDT 24
Peak memory 213884 kb
Host smart-179182a8-06cb-4b67-866b-6c234fdda727
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066631726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2066631726
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3147793144
Short name T1478
Test name
Test status
Simulation time 348336971 ps
CPU time 6.55 seconds
Started Mar 19 03:19:27 PM PDT 24
Finished Mar 19 03:19:34 PM PDT 24
Peak memory 213868 kb
Host smart-bc053134-b480-4050-a09f-e98dbb5083fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147793144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3147793144
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.381015433
Short name T710
Test name
Test status
Simulation time 313686576 ps
CPU time 2.21 seconds
Started Mar 19 03:16:00 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 212916 kb
Host smart-99857c84-7123-4912-873a-3c10c2e46c7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381015433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.381015433
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1477993651
Short name T1142
Test name
Test status
Simulation time 1870798739 ps
CPU time 39.49 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:39 PM PDT 24
Peak memory 250940 kb
Host smart-3b3222f0-fb55-49d9-8515-f2bfde5b2719
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477993651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1477993651
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2994150118
Short name T707
Test name
Test status
Simulation time 3148106555 ps
CPU time 54.89 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:20:15 PM PDT 24
Peak memory 249228 kb
Host smart-3f2620cb-b14a-4fe8-a300-26a4fcc1fb00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994150118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2994150118
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2060685366
Short name T751
Test name
Test status
Simulation time 399811803 ps
CPU time 16.54 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:18 PM PDT 24
Peak memory 247108 kb
Host smart-738285cd-f3c3-459b-9072-b54ff1002221
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060685366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2060685366
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.321348267
Short name T989
Test name
Test status
Simulation time 2103261346 ps
CPU time 15.16 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:19:49 PM PDT 24
Peak memory 250800 kb
Host smart-0393fe93-772e-4103-82a8-3c89ce9e46b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321348267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.321348267
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1633548161
Short name T1469
Test name
Test status
Simulation time 89797208 ps
CPU time 2.79 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 221896 kb
Host smart-132ee61d-376a-4c0c-b019-8f9ddc84a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633548161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1633548161
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.407867906
Short name T1696
Test name
Test status
Simulation time 151889162 ps
CPU time 2.49 seconds
Started Mar 19 03:19:15 PM PDT 24
Finished Mar 19 03:19:17 PM PDT 24
Peak memory 221680 kb
Host smart-b187c53b-8ef9-4f06-934d-1dc1ee93417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407867906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.407867906
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1579275533
Short name T1163
Test name
Test status
Simulation time 561515938 ps
CPU time 9.51 seconds
Started Mar 19 03:19:10 PM PDT 24
Finished Mar 19 03:19:20 PM PDT 24
Peak memory 214336 kb
Host smart-6db04197-ecc1-452c-a871-eea32f6a1f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579275533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1579275533
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2896404816
Short name T761
Test name
Test status
Simulation time 458569662 ps
CPU time 7.03 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:09 PM PDT 24
Peak memory 213576 kb
Host smart-5f3a0c95-835a-4846-b4a4-2afd79804d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896404816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2896404816
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2866080396
Short name T1444
Test name
Test status
Simulation time 1291802453 ps
CPU time 17.88 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 226056 kb
Host smart-0ac24114-fb26-4780-b34f-15ba6715c46d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866080396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2866080396
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.996578325
Short name T52
Test name
Test status
Simulation time 7280267685 ps
CPU time 18.2 seconds
Started Mar 19 03:16:00 PM PDT 24
Finished Mar 19 03:16:19 PM PDT 24
Peak memory 226184 kb
Host smart-cfce4910-cfa7-4860-b285-f28580563483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996578325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.996578325
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2471662913
Short name T744
Test name
Test status
Simulation time 358582299 ps
CPU time 10.7 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:14 PM PDT 24
Peak memory 217856 kb
Host smart-d10bbf68-c9f3-49c8-a8ba-6aefe24ef392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471662913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2471662913
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.4187772673
Short name T127
Test name
Test status
Simulation time 583209709 ps
CPU time 11.11 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:29 PM PDT 24
Peak memory 217944 kb
Host smart-9037b7bd-8d75-4c02-9b9e-f74642d9b2ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187772673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.4187772673
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3857790699
Short name T1435
Test name
Test status
Simulation time 894219086 ps
CPU time 7.45 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 217896 kb
Host smart-25e2e2b8-04a1-4d3f-b1db-b008579fd7a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857790699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
857790699
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.575439793
Short name T559
Test name
Test status
Simulation time 663061586 ps
CPU time 7.3 seconds
Started Mar 19 03:19:25 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 217932 kb
Host smart-711602b4-5f03-47a8-8ff7-218d0b87a10c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575439793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.575439793
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2389581756
Short name T1053
Test name
Test status
Simulation time 1688558764 ps
CPU time 9.41 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:29 PM PDT 24
Peak memory 224740 kb
Host smart-79a4c7e8-8bef-4e9b-b554-881c47fbc7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389581756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2389581756
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.684603196
Short name T1365
Test name
Test status
Simulation time 761252962 ps
CPU time 9.45 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:11 PM PDT 24
Peak memory 226056 kb
Host smart-956ce42d-f0de-42ef-83a6-0b9e7a7c059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684603196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.684603196
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1072988253
Short name T439
Test name
Test status
Simulation time 28384776 ps
CPU time 1.4 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 218116 kb
Host smart-74e0286e-8960-4e7d-9806-97a0f0d62393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072988253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1072988253
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2958360481
Short name T383
Test name
Test status
Simulation time 130484739 ps
CPU time 2.15 seconds
Started Mar 19 03:19:25 PM PDT 24
Finished Mar 19 03:19:28 PM PDT 24
Peak memory 213628 kb
Host smart-2128f6f6-944f-4538-b120-d3d35bb38e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958360481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2958360481
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3953177088
Short name T858
Test name
Test status
Simulation time 335950678 ps
CPU time 25.12 seconds
Started Mar 19 03:19:16 PM PDT 24
Finished Mar 19 03:19:41 PM PDT 24
Peak memory 250960 kb
Host smart-913dd76f-b7fe-40a2-8d35-b54e5690d056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953177088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3953177088
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.967599219
Short name T1157
Test name
Test status
Simulation time 626571975 ps
CPU time 21.86 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 245072 kb
Host smart-b16d9b3a-348b-4733-bea0-dd131fa1865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967599219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.967599219
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1050183172
Short name T253
Test name
Test status
Simulation time 192223156 ps
CPU time 8.61 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:08 PM PDT 24
Peak memory 250916 kb
Host smart-9e452d6f-82cb-41ac-9022-1ed43c733d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050183172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1050183172
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3836854702
Short name T268
Test name
Test status
Simulation time 116790284 ps
CPU time 6.05 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:23 PM PDT 24
Peak memory 242752 kb
Host smart-03405b08-d8b1-4c49-8e30-6c186246e2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836854702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3836854702
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3144160675
Short name T1081
Test name
Test status
Simulation time 7988470410 ps
CPU time 134.67 seconds
Started Mar 19 03:19:32 PM PDT 24
Finished Mar 19 03:21:47 PM PDT 24
Peak memory 250972 kb
Host smart-6e560958-75d0-48f3-8689-b7ae8bd19f78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144160675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3144160675
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.967857896
Short name T1113
Test name
Test status
Simulation time 8462049059 ps
CPU time 116.52 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:18:00 PM PDT 24
Peak memory 277044 kb
Host smart-02f0cd96-9bea-4b2c-9036-5825a9207e68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967857896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.967857896
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.108676724
Short name T1443
Test name
Test status
Simulation time 11726957 ps
CPU time 1.04 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:18 PM PDT 24
Peak memory 211472 kb
Host smart-e345fa9e-b799-407f-9598-c771fec3b6a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108676724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.108676724
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3260927563
Short name T1549
Test name
Test status
Simulation time 38040231 ps
CPU time 0.95 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:01 PM PDT 24
Peak memory 211528 kb
Host smart-8e9faec1-ba38-4458-8f1b-e51e14076e5a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260927563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3260927563
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3788477857
Short name T764
Test name
Test status
Simulation time 12596861 ps
CPU time 0.85 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 209528 kb
Host smart-6b3a661b-6d26-4ff8-89ce-a9b07b5f1d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788477857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3788477857
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2877710154
Short name T242
Test name
Test status
Simulation time 12113997 ps
CPU time 0.97 seconds
Started Mar 19 03:19:22 PM PDT 24
Finished Mar 19 03:19:23 PM PDT 24
Peak memory 209476 kb
Host smart-11bd6013-800d-4327-8459-23a3de288b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877710154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2877710154
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.842754008
Short name T234
Test name
Test status
Simulation time 12717685 ps
CPU time 0.91 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 209372 kb
Host smart-38cdf5bf-befc-4af8-9e4d-bd0df4e8f903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842754008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.842754008
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.331489796
Short name T787
Test name
Test status
Simulation time 239487329 ps
CPU time 12.19 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 217904 kb
Host smart-0f22fb11-daec-4feb-9d92-aa6dd74ab81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331489796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.331489796
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.992896862
Short name T1585
Test name
Test status
Simulation time 1106443471 ps
CPU time 13.55 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 217956 kb
Host smart-ae2dd1d9-f717-4d44-a374-eecb1f23d8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992896862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.992896862
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1643386243
Short name T1203
Test name
Test status
Simulation time 145648599 ps
CPU time 2.71 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:07 PM PDT 24
Peak memory 209484 kb
Host smart-6c062f8c-83f0-457e-a33f-48ca697b347a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643386243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1643386243
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.665375576
Short name T1379
Test name
Test status
Simulation time 1400117672 ps
CPU time 5.11 seconds
Started Mar 19 03:19:17 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 216872 kb
Host smart-600cb067-ba92-4510-8c42-08557d5055d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665375576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.665375576
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1269519891
Short name T1242
Test name
Test status
Simulation time 5648258063 ps
CPU time 75.59 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:17:20 PM PDT 24
Peak memory 219284 kb
Host smart-9dfa2b50-f5b2-47da-9c28-67d3964f45e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269519891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1269519891
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2045261078
Short name T1426
Test name
Test status
Simulation time 9702970970 ps
CPU time 70.63 seconds
Started Mar 19 03:19:23 PM PDT 24
Finished Mar 19 03:20:34 PM PDT 24
Peak memory 219020 kb
Host smart-c2400118-31b4-4eed-9e20-7b9f3a63d88d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045261078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2045261078
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2076766385
Short name T1631
Test name
Test status
Simulation time 1008732453 ps
CPU time 3.39 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 217300 kb
Host smart-a8989238-9904-4871-a177-74e32295905f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076766385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
076766385
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.500572031
Short name T1073
Test name
Test status
Simulation time 760762358 ps
CPU time 10.08 seconds
Started Mar 19 03:19:20 PM PDT 24
Finished Mar 19 03:19:30 PM PDT 24
Peak memory 217288 kb
Host smart-65b03d84-4d64-4dc7-808c-5684b83d7788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500572031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.500572031
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2055743777
Short name T567
Test name
Test status
Simulation time 6924213392 ps
CPU time 15.26 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:18 PM PDT 24
Peak memory 219040 kb
Host smart-d4928df7-da8d-41a6-bef4-123ef3c6641f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055743777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2055743777
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4278026578
Short name T483
Test name
Test status
Simulation time 144752252 ps
CPU time 5.64 seconds
Started Mar 19 03:19:30 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 217904 kb
Host smart-b71185de-7137-4dec-a27e-06446fac6bfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278026578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4278026578
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.111142688
Short name T1531
Test name
Test status
Simulation time 2605824719 ps
CPU time 35.86 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:16:40 PM PDT 24
Peak memory 213700 kb
Host smart-06d7c7cb-3a11-4136-94c6-3c935b5bd08c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111142688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.111142688
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1787323364
Short name T385
Test name
Test status
Simulation time 1211614639 ps
CPU time 33.13 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:20:07 PM PDT 24
Peak memory 213416 kb
Host smart-c021379d-6861-43a8-8db7-a88e8e86662c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787323364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1787323364
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2572713588
Short name T425
Test name
Test status
Simulation time 1077124664 ps
CPU time 3.9 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 213032 kb
Host smart-bd590dc8-efd2-4541-ad47-31c113591dbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572713588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2572713588
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3904400902
Short name T1543
Test name
Test status
Simulation time 933280188 ps
CPU time 6.57 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:24 PM PDT 24
Peak memory 213484 kb
Host smart-d69c5298-c350-452a-8fec-e3675076cbd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904400902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3904400902
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1932884744
Short name T597
Test name
Test status
Simulation time 16179790486 ps
CPU time 62.78 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:17:03 PM PDT 24
Peak memory 269880 kb
Host smart-87625632-a0b6-4eba-b433-04c2d4547bf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932884744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1932884744
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.809428418
Short name T266
Test name
Test status
Simulation time 7301893871 ps
CPU time 36.9 seconds
Started Mar 19 03:19:34 PM PDT 24
Finished Mar 19 03:20:11 PM PDT 24
Peak memory 269748 kb
Host smart-21a713df-3170-42a8-a661-e174786bf449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809428418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.809428418
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1372102435
Short name T1672
Test name
Test status
Simulation time 1672086994 ps
CPU time 13.02 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:42 PM PDT 24
Peak memory 250968 kb
Host smart-c9699c93-c984-483b-bb14-3921eeec5c38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372102435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1372102435
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3630725400
Short name T1160
Test name
Test status
Simulation time 1908762982 ps
CPU time 11.62 seconds
Started Mar 19 03:16:04 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 246592 kb
Host smart-dee5ab13-afd4-4609-9fc0-d3728a54f6a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630725400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3630725400
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1896746441
Short name T588
Test name
Test status
Simulation time 72990964 ps
CPU time 3.9 seconds
Started Mar 19 03:16:00 PM PDT 24
Finished Mar 19 03:16:05 PM PDT 24
Peak memory 222008 kb
Host smart-ac3c574b-b691-496c-af2b-3755c59eb617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896746441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1896746441
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.587368399
Short name T1065
Test name
Test status
Simulation time 306195648 ps
CPU time 3.64 seconds
Started Mar 19 03:19:29 PM PDT 24
Finished Mar 19 03:19:33 PM PDT 24
Peak memory 221928 kb
Host smart-f8523c13-83fa-43f3-ae1a-faca631ee4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587368399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.587368399
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1203882040
Short name T413
Test name
Test status
Simulation time 340553597 ps
CPU time 11.67 seconds
Started Mar 19 03:16:06 PM PDT 24
Finished Mar 19 03:16:18 PM PDT 24
Peak memory 214304 kb
Host smart-52f916e0-c350-4e1a-b8f6-17d5c88081d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203882040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1203882040
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2329849265
Short name T1381
Test name
Test status
Simulation time 289938667 ps
CPU time 7.25 seconds
Started Mar 19 03:19:32 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 214152 kb
Host smart-51108bf2-c070-480c-b9cf-0b66055a579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329849265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2329849265
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.735289925
Short name T1025
Test name
Test status
Simulation time 2831137070 ps
CPU time 10.33 seconds
Started Mar 19 03:19:28 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 219300 kb
Host smart-6f45aad2-1673-4efd-bade-a01fb62883a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735289925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.735289925
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.903920823
Short name T1129
Test name
Test status
Simulation time 270719297 ps
CPU time 10.12 seconds
Started Mar 19 03:16:06 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 226024 kb
Host smart-76c5a09f-4e5b-4758-9333-79b7e6df8b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903920823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.903920823
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1758561
Short name T980
Test name
Test status
Simulation time 340485344 ps
CPU time 13.33 seconds
Started Mar 19 03:16:04 PM PDT 24
Finished Mar 19 03:16:18 PM PDT 24
Peak memory 217900 kb
Host smart-aba50caf-d589-4bfe-8ca0-9af305070c7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_diges
t.1758561
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2305966068
Short name T110
Test name
Test status
Simulation time 203613837 ps
CPU time 9.64 seconds
Started Mar 19 03:19:33 PM PDT 24
Finished Mar 19 03:19:43 PM PDT 24
Peak memory 217828 kb
Host smart-9ce9b315-f0b4-4b3e-84ee-3b54180ee010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305966068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2305966068
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1459868047
Short name T812
Test name
Test status
Simulation time 1135535544 ps
CPU time 13.63 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:17 PM PDT 24
Peak memory 217960 kb
Host smart-a5e33df7-1cbe-41e8-89d2-24fa79ad6c86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459868047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
459868047
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.36343736
Short name T1138
Test name
Test status
Simulation time 318021929 ps
CPU time 9.01 seconds
Started Mar 19 03:19:19 PM PDT 24
Finished Mar 19 03:19:28 PM PDT 24
Peak memory 218028 kb
Host smart-a0a2336f-89f1-492c-a274-25b4bdd03c1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36343736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.36343736
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3898577054
Short name T896
Test name
Test status
Simulation time 1391073611 ps
CPU time 12.86 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 225436 kb
Host smart-af179546-f986-4a06-b2c9-c973c17eeca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898577054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3898577054
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.753364792
Short name T994
Test name
Test status
Simulation time 511883182 ps
CPU time 11.06 seconds
Started Mar 19 03:19:25 PM PDT 24
Finished Mar 19 03:19:36 PM PDT 24
Peak memory 226096 kb
Host smart-a6d6a8ec-204d-49e6-8f1a-daf42d32ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753364792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.753364792
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1808303151
Short name T382
Test name
Test status
Simulation time 192152755 ps
CPU time 2.87 seconds
Started Mar 19 03:15:59 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 214268 kb
Host smart-ad5ac67f-dff4-43ec-ad78-bbec005756b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808303151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1808303151
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.44931445
Short name T496
Test name
Test status
Simulation time 42912589 ps
CPU time 1.1 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 211932 kb
Host smart-64757f66-ae29-4f36-845f-485925cbacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44931445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.44931445
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.166351609
Short name T930
Test name
Test status
Simulation time 348550399 ps
CPU time 23.33 seconds
Started Mar 19 03:19:18 PM PDT 24
Finished Mar 19 03:19:41 PM PDT 24
Peak memory 248584 kb
Host smart-6455a0a1-874b-45b6-84db-cd8aadcf9402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166351609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.166351609
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1784125982
Short name T1400
Test name
Test status
Simulation time 259593286 ps
CPU time 24.5 seconds
Started Mar 19 03:16:00 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 250928 kb
Host smart-b84e7dc2-1b93-4265-83af-c9f69fe596af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784125982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1784125982
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1593276259
Short name T1231
Test name
Test status
Simulation time 124269046 ps
CPU time 10.97 seconds
Started Mar 19 03:19:28 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 250636 kb
Host smart-1d3b3fac-e991-4a3f-9dee-2e5610a0d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593276259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1593276259
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1930984914
Short name T990
Test name
Test status
Simulation time 321879088 ps
CPU time 2.91 seconds
Started Mar 19 03:16:02 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 226376 kb
Host smart-a5ef2a83-ebc9-48a8-8bcb-c36b5e85bb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930984914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1930984914
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1240312826
Short name T181
Test name
Test status
Simulation time 12487722877 ps
CPU time 121.66 seconds
Started Mar 19 03:16:03 PM PDT 24
Finished Mar 19 03:18:06 PM PDT 24
Peak memory 271152 kb
Host smart-0b16577c-ec2b-4783-bb29-fea9933095ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240312826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1240312826
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3975739680
Short name T1097
Test name
Test status
Simulation time 34527825089 ps
CPU time 291.02 seconds
Started Mar 19 03:19:23 PM PDT 24
Finished Mar 19 03:24:15 PM PDT 24
Peak memory 275684 kb
Host smart-69520838-5c32-483f-bbaf-7097bc066e12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975739680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3975739680
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2168748995
Short name T300
Test name
Test status
Simulation time 41440607 ps
CPU time 0.87 seconds
Started Mar 19 03:19:21 PM PDT 24
Finished Mar 19 03:19:22 PM PDT 24
Peak memory 211532 kb
Host smart-3e4eaaa5-443e-4e38-b091-9b5cd3e3cc38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168748995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2168748995
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2923742813
Short name T10
Test name
Test status
Simulation time 37447622 ps
CPU time 0.9 seconds
Started Mar 19 03:16:01 PM PDT 24
Finished Mar 19 03:16:04 PM PDT 24
Peak memory 211660 kb
Host smart-2129c243-be37-4e6c-a1ab-34f068d29f71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923742813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2923742813
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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