Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181027968

1

T1

31041

T2

77030

T3

26144

auto[1]

2686815

1

T1

1188

T4

396

T9

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181022785

1

T1

31239

T2

77030

T3

26144

auto[1]

2691998

1

T1

990

T4

693

T9

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	13839396	1			T1	5698		T2	87		T3	5839
auto[IdleSt]	38674747	1			T1	1849		T2	76943		T3	6253
auto[ClkMuxSt]	68313	1			T1	48		T3	66		T4	95
auto[CntIncrSt]	67810	1			T1	48		T3	66		T4	95
auto[CntProgSt]	2981685	1			T1	9497		T3	1195		T4	782
auto[TransCheckSt]	53394	1			T1	37		T3	66		T4	73
auto[TokenHashSt]	66954078	1			T1	404		T3	1308		T4	658
auto[FlashRmaSt]	55196	1			T1	35		T4	34		T9	59
auto[TokenCheck0St]	24278	1			T1	30		T4	19		T9	20
auto[TokenCheck1St]	17803	1			T1	19		T4	11		T9	9
auto[TransProgSt]	718337	1			T1	4722		T4	105		T9	2478
auto[PostTransSt]	24282047	1			T1	6241		T3	11351		T4	15301
auto[ScrapSt]	205941	1			T16	33		T19	5382		T42	3
auto[EscalateSt]	13058185	1			T1	2782		T4	1632		T9	1489
auto[InvalidSt]	22709777	1			T1	819		T12	9655		T15	5105

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3796	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	22709777	1			T1	819		T12	9655		T15	5105
EscalateSt	13058185	1			T1	2782		T4	1632		T9	1489
ScrapSt	205941	1			T16	33		T19	5382		T42	3
PostTransSt	24282047	1			T1	6241		T3	11351		T4	15301
TransProgSt	718337	1			T1	4722		T4	105		T9	2478
TokenCheck1St	17803	1			T1	19		T4	11		T9	9
TokenCheck0St	24278	1			T1	30		T4	19		T9	20
FlashRmaSt	55196	1			T1	35		T4	34		T9	59
TokenHashSt	66954078	1			T1	404		T3	1308		T4	658
TransCheckSt	53394	1			T1	37		T3	66		T4	73
CntProgSt	2981685	1			T1	9497		T3	1195		T4	782
CntIncrSt	67810	1			T1	48		T3	66		T4	95
ClkMuxSt	68313	1			T1	48		T3	66		T4	95
IdleSt	38674747	1			T1	1849		T2	76943		T3	6253
ResetSt	13839396	1			T1	5698		T2	87		T3	5839
arcs[ResetSt=>IdleSt]	103031	1			T1	60		T2	1		T3	67
arcs[IdleSt=>ScrapSt]	525	1			T16	1		T19	6		T42	1
arcs[IdleSt=>ClkMuxSt]	67931	1			T1	48		T3	66		T4	95
arcs[ClkMuxSt=>CntIncrSt]	67810	1			T1	48		T3	66		T4	95
arcs[CntIncrSt=>PostTransSt]	3061	1			T4	11		T9	11		T6	7
arcs[CntIncrSt=>CntProgSt]	64587	1			T1	48		T3	66		T4	84
arcs[CntProgSt=>PostTransSt]	9007	1			T1	11		T4	11		T9	11
arcs[CntProgSt=>TransCheckSt]	53394	1			T1	37		T3	66		T4	73
arcs[TransCheckSt=>PostTransSt]	7283	1			T4	13		T9	9		T11	23
arcs[TransCheckSt=>TokenHashSt]	45889	1			T1	37		T3	66		T4	60
arcs[TokenHashSt=>PostTransSt]	20124	1			T1	7		T3	66		T4	41
arcs[TokenHashSt=>FlashRmaSt]	24477	1			T1	30		T4	19		T9	20
arcs[FlashRmaSt=>TokenCheck0St]	24278	1			T1	30		T4	19		T9	20
arcs[TokenCheck0St=>PostTransSt]	6414	1			T1	11		T4	8		T9	11
arcs[TokenCheck0St=>TokenCheck1St]	17803	1			T1	19		T4	11		T9	9
arcs[TokenCheck1St=>PostTransSt]	1302	1			T4	1		T9	1		T11	13
arcs[TransProgSt=>PostTransSt]	14718	1			T1	19		T4	10		T9	8
arcs[IdleSt=>EscalateSt]	373	1			T42	9		T56	4		T54	6
arcs[ClkMuxSt=>EscalateSt]	121	1			T42	3		T54	1		T55	2
arcs[CntIncrSt=>EscalateSt]	162	1			T42	3		T56	4		T54	2
arcs[CntProgSt=>EscalateSt]	2186	1			T42	8		T56	27		T54	27
arcs[TransCheckSt=>EscalateSt]	222	1			T42	4		T54	2		T55	9
arcs[TokenHashSt=>EscalateSt]	1288	1			T42	32		T56	10		T60	1
arcs[FlashRmaSt=>EscalateSt]	199	1			T42	2		T56	2		T54	2
arcs[TokenCheck0St=>EscalateSt]	61	1			T42	2		T54	1		T55	2
arcs[TokenCheck1St=>EscalateSt]	283	1			T42	4		T56	5		T55	2
arcs[TransProgSt=>EscalateSt]	1500	1			T42	7		T56	12		T54	15
arcs[PostTransSt=>EscalateSt]	9478	1			T1	11		T4	11		T9	11
arcs[InvalidSt=>EscalateSt]	26497	1			T1	11		T12	53		T15	68

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13839055	1			T1	5698		T2	87		T3	5839
auto[0]	auto[IdleSt]	38674506	1			T1	1849		T2	76943		T3	6253
auto[0]	auto[ClkMuxSt]	68235	1			T1	48		T3	66		T4	95
auto[0]	auto[CntIncrSt]	67707	1			T1	48		T3	66		T4	95
auto[0]	auto[CntProgSt]	2980217	1			T1	9497		T3	1195		T4	782
auto[0]	auto[TransCheckSt]	53244	1			T1	37		T3	66		T4	73
auto[0]	auto[TokenHashSt]	66953209	1			T1	404		T3	1308		T4	658
auto[0]	auto[FlashRmaSt]	55067	1			T1	35		T4	34		T9	59
auto[0]	auto[TokenCheck0St]	24241	1			T1	30		T4	19		T9	20
auto[0]	auto[TokenCheck1St]	17617	1			T1	19		T4	11		T9	9
auto[0]	auto[TransProgSt]	717322	1			T1	4722		T4	105		T9	2478
auto[0]	auto[PostTransSt]	24277248	1			T1	6235		T3	11351		T4	15297
auto[0]	auto[ScrapSt]	205856	1			T16	33		T19	5382		T42	2
auto[0]	auto[EscalateSt]	10394112	1			T1	1606		T4	1240		T9	901
auto[0]	auto[InvalidSt]	22696536	1			T1	813		T12	9637		T15	5070
auto[1]	auto[ResetSt]	341	1			T42	7		T56	6		T54	4
auto[1]	auto[IdleSt]	241	1			T42	4		T56	2		T54	1
auto[1]	auto[ClkMuxSt]	78	1			T54	1		T55	2		T258	1
auto[1]	auto[CntIncrSt]	103	1			T42	2		T56	2		T55	1
auto[1]	auto[CntProgSt]	1468	1			T42	4		T56	19		T54	15
auto[1]	auto[TransCheckSt]	150	1			T42	1		T54	1		T55	6
auto[1]	auto[TokenHashSt]	869	1			T42	24		T56	6		T60	1
auto[1]	auto[FlashRmaSt]	129	1			T42	2		T56	1		T54	2
auto[1]	auto[TokenCheck0St]	37	1			T42	1		T54	1		T259	2
auto[1]	auto[TokenCheck1St]	186	1			T42	2		T56	3		T55	2
auto[1]	auto[TransProgSt]	1015	1			T42	6		T56	6		T54	12
auto[1]	auto[PostTransSt]	4799	1			T1	6		T4	4		T9	6
auto[1]	auto[ScrapSt]	85	1			T42	1		T54	1		T55	1
auto[1]	auto[EscalateSt]	2664073	1			T1	1176		T4	392		T9	588
auto[1]	auto[InvalidSt]	13241	1			T1	6		T12	18		T15	35

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13839080	1			T1	5698		T2	87		T3	5839
auto[0]	auto[IdleSt]	38674494	1			T1	1849		T2	76943		T3	6253
auto[0]	auto[ClkMuxSt]	68231	1			T1	48		T3	66		T4	95
auto[0]	auto[CntIncrSt]	67696	1			T1	48		T3	66		T4	95
auto[0]	auto[CntProgSt]	2980185	1			T1	9497		T3	1195		T4	782
auto[0]	auto[TransCheckSt]	53241	1			T1	37		T3	66		T4	73
auto[0]	auto[TokenHashSt]	66953216	1			T1	404		T3	1308		T4	658
auto[0]	auto[FlashRmaSt]	55072	1			T1	35		T4	34		T9	59
auto[0]	auto[TokenCheck0St]	24234	1			T1	30		T4	19		T9	20
auto[0]	auto[TokenCheck1St]	17614	1			T1	19		T4	11		T9	9
auto[0]	auto[TransProgSt]	717365	1			T1	4722		T4	105		T9	2478
auto[0]	auto[PostTransSt]	24277247	1			T1	6236		T3	11351		T4	15294
auto[0]	auto[ScrapSt]	205855	1			T16	33		T19	5382		T42	3
auto[0]	auto[EscalateSt]	10388938	1			T1	1802		T4	946		T9	999
auto[0]	auto[InvalidSt]	22696521	1			T1	814		T12	9620		T15	5072
auto[1]	auto[ResetSt]	316	1			T42	1		T56	7		T54	8
auto[1]	auto[IdleSt]	253	1			T42	6		T56	3		T54	6
auto[1]	auto[ClkMuxSt]	82	1			T42	3		T54	1		T55	2
auto[1]	auto[CntIncrSt]	114	1			T42	2		T56	4		T54	2
auto[1]	auto[CntProgSt]	1500	1			T42	7		T56	16		T54	18
auto[1]	auto[TransCheckSt]	153	1			T42	4		T54	1		T55	6
auto[1]	auto[TokenHashSt]	862	1			T42	21		T56	8		T54	7
auto[1]	auto[FlashRmaSt]	124	1			T42	1		T56	2		T54	1
auto[1]	auto[TokenCheck0St]	44	1			T42	2		T55	2		T259	1
auto[1]	auto[TokenCheck1St]	189	1			T42	3		T56	3		T55	1
auto[1]	auto[TransProgSt]	972	1			T42	4		T56	9		T54	7
auto[1]	auto[PostTransSt]	4800	1			T1	5		T4	7		T9	5
auto[1]	auto[ScrapSt]	86	1			T56	1		T54	1		T55	1
auto[1]	auto[EscalateSt]	2669247	1			T1	980		T4	686		T9	490
auto[1]	auto[InvalidSt]	13256	1			T1	5		T12	35		T15	33