Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102561 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
47 |
auto[1] |
3643 |
1 |
|
|
T3 |
11 |
|
T10 |
6 |
|
T37 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
104691 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
1513 |
1 |
|
|
T9 |
19 |
|
T11 |
21 |
|
T66 |
14 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102386 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
3818 |
1 |
|
|
T21 |
5 |
|
T24 |
1 |
|
T36 |
8 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102367 |
1 |
|
|
T1 |
75 |
|
T2 |
9 |
|
T3 |
58 |
auto[1] |
3837 |
1 |
|
|
T2 |
1 |
|
T21 |
8 |
|
T24 |
3 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102427 |
1 |
|
|
T1 |
75 |
|
T2 |
9 |
|
T3 |
58 |
auto[1] |
3777 |
1 |
|
|
T2 |
1 |
|
T21 |
8 |
|
T36 |
10 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
96793 |
1 |
|
|
T1 |
75 |
|
T2 |
5 |
|
T3 |
58 |
no_err_inj |
9411 |
1 |
|
|
T2 |
5 |
|
T8 |
16 |
|
T4 |
10 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102663 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
50 |
auto[1] |
3541 |
1 |
|
|
T3 |
8 |
|
T10 |
11 |
|
T37 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
104650 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
1554 |
1 |
|
|
T9 |
20 |
|
T11 |
31 |
|
T66 |
9 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
74107 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
32097 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102387 |
1 |
|
|
T1 |
75 |
|
T2 |
8 |
|
T3 |
58 |
auto[1] |
3817 |
1 |
|
|
T2 |
2 |
|
T21 |
7 |
|
T36 |
11 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102333 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
3871 |
1 |
|
|
T21 |
9 |
|
T36 |
13 |
|
T16 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102367 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
3837 |
1 |
|
|
T21 |
7 |
|
T36 |
11 |
|
T18 |
9 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102659 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
50 |
auto[1] |
3545 |
1 |
|
|
T3 |
8 |
|
T10 |
10 |
|
T37 |
6 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102010 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
4194 |
1 |
|
|
T15 |
17 |
|
T16 |
10 |
|
T19 |
25 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
104739 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
1465 |
1 |
|
|
T9 |
14 |
|
T11 |
12 |
|
T66 |
9 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
104705 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
1499 |
1 |
|
|
T9 |
17 |
|
T11 |
14 |
|
T66 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
104743 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
1461 |
1 |
|
|
T9 |
12 |
|
T11 |
20 |
|
T66 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101091 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[1] |
5113 |
1 |
|
|
T2 |
10 |
|
T24 |
12 |
|
T16 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
98665 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
7539 |
1 |
|
|
T25 |
75 |
|
T54 |
93 |
|
T55 |
62 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102410 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
3794 |
1 |
|
|
T21 |
4 |
|
T24 |
1 |
|
T36 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102420 |
1 |
|
|
T1 |
75 |
|
T2 |
9 |
|
T3 |
58 |
auto[1] |
3784 |
1 |
|
|
T2 |
1 |
|
T21 |
8 |
|
T24 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102439 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[1] |
3765 |
1 |
|
|
T21 |
8 |
|
T36 |
10 |
|
T16 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102627 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
49 |
auto[1] |
3577 |
1 |
|
|
T3 |
9 |
|
T10 |
7 |
|
T37 |
7 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
95337 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
55 |
auto[1] |
10867 |
1 |
|
|
T3 |
3 |
|
T10 |
10 |
|
T13 |
58 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
98721 |
1 |
|
|
T2 |
10 |
|
T3 |
58 |
|
T8 |
16 |
auto[1] |
7483 |
1 |
|
|
T1 |
75 |
|
T14 |
72 |
|
T65 |
67 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
106204 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102701 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
51 |
auto[1] |
3503 |
1 |
|
|
T3 |
7 |
|
T10 |
12 |
|
T37 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102684 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
51 |
auto[1] |
3520 |
1 |
|
|
T3 |
7 |
|
T10 |
10 |
|
T37 |
8 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102615 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
53 |
auto[1] |
3589 |
1 |
|
|
T3 |
5 |
|
T10 |
10 |
|
T37 |
4 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
94158 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T9 |
82 |
auto[0] |
no_err_inj |
6933 |
1 |
|
|
T8 |
16 |
|
T4 |
10 |
|
T16 |
26 |
auto[1] |
err_inj |
2635 |
1 |
|
|
T2 |
5 |
|
T24 |
6 |
|
T16 |
3 |
auto[1] |
no_err_inj |
2478 |
1 |
|
|
T2 |
5 |
|
T24 |
6 |
|
T16 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
97615 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[0] |
auto[1] |
3476 |
1 |
|
|
T21 |
8 |
|
T36 |
7 |
|
T18 |
12 |
auto[1] |
auto[0] |
4805 |
1 |
|
|
T2 |
9 |
|
T24 |
11 |
|
T16 |
10 |
auto[1] |
auto[1] |
308 |
1 |
|
|
T2 |
1 |
|
T24 |
1 |
|
T17 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
97542 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[0] |
auto[1] |
3549 |
1 |
|
|
T21 |
9 |
|
T36 |
13 |
|
T18 |
10 |
auto[1] |
auto[0] |
4791 |
1 |
|
|
T2 |
10 |
|
T24 |
12 |
|
T16 |
9 |
auto[1] |
auto[1] |
322 |
1 |
|
|
T16 |
1 |
|
T17 |
2 |
|
T277 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
97630 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[0] |
auto[1] |
3461 |
1 |
|
|
T21 |
8 |
|
T36 |
10 |
|
T18 |
11 |
auto[1] |
auto[0] |
4809 |
1 |
|
|
T2 |
10 |
|
T24 |
12 |
|
T16 |
9 |
auto[1] |
auto[1] |
304 |
1 |
|
|
T16 |
1 |
|
T17 |
1 |
|
T90 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
97537 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[0] |
auto[1] |
3554 |
1 |
|
|
T21 |
8 |
|
T36 |
6 |
|
T18 |
9 |
auto[1] |
auto[0] |
4830 |
1 |
|
|
T2 |
9 |
|
T24 |
9 |
|
T16 |
10 |
auto[1] |
auto[1] |
283 |
1 |
|
|
T2 |
1 |
|
T24 |
3 |
|
T90 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
97613 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[0] |
auto[1] |
3478 |
1 |
|
|
T21 |
8 |
|
T36 |
10 |
|
T18 |
8 |
auto[1] |
auto[0] |
4814 |
1 |
|
|
T2 |
9 |
|
T24 |
12 |
|
T16 |
9 |
auto[1] |
auto[1] |
299 |
1 |
|
|
T2 |
1 |
|
T16 |
1 |
|
T90 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
97570 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[0] |
auto[1] |
3521 |
1 |
|
|
T21 |
5 |
|
T36 |
8 |
|
T18 |
9 |
auto[1] |
auto[0] |
4816 |
1 |
|
|
T2 |
10 |
|
T24 |
11 |
|
T16 |
10 |
auto[1] |
auto[1] |
297 |
1 |
|
|
T24 |
1 |
|
T17 |
1 |
|
T278 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71989 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
47 |
auto[0] |
auto[1] |
2118 |
1 |
|
|
T3 |
11 |
|
T10 |
6 |
|
T37 |
8 |
auto[1] |
auto[0] |
30572 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1525 |
1 |
|
|
T19 |
15 |
|
T91 |
6 |
|
T49 |
6 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72022 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
50 |
auto[0] |
auto[1] |
2085 |
1 |
|
|
T3 |
8 |
|
T10 |
11 |
|
T37 |
9 |
auto[1] |
auto[0] |
30641 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1456 |
1 |
|
|
T19 |
14 |
|
T91 |
10 |
|
T49 |
5 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71754 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[0] |
auto[1] |
2353 |
1 |
|
|
T16 |
10 |
|
T19 |
25 |
|
T279 |
17 |
auto[1] |
auto[0] |
30256 |
1 |
|
|
T4 |
10 |
|
T16 |
26 |
|
T17 |
10 |
auto[1] |
auto[1] |
1841 |
1 |
|
|
T15 |
17 |
|
T20 |
19 |
|
T42 |
33 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72049 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
50 |
auto[0] |
auto[1] |
2058 |
1 |
|
|
T3 |
8 |
|
T10 |
10 |
|
T37 |
6 |
auto[1] |
auto[0] |
30610 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1487 |
1 |
|
|
T19 |
10 |
|
T91 |
9 |
|
T49 |
9 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
64692 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
55 |
auto[0] |
auto[1] |
9415 |
1 |
|
|
T3 |
3 |
|
T10 |
10 |
|
T13 |
58 |
auto[1] |
auto[0] |
30645 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1452 |
1 |
|
|
T19 |
4 |
|
T91 |
7 |
|
T49 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71864 |
1 |
|
|
T1 |
75 |
|
T2 |
9 |
|
T3 |
58 |
auto[0] |
auto[1] |
2243 |
1 |
|
|
T2 |
1 |
|
T21 |
8 |
|
T24 |
1 |
auto[1] |
auto[0] |
30556 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1541 |
1 |
|
|
T17 |
2 |
|
T18 |
12 |
|
T42 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71848 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[0] |
auto[1] |
2259 |
1 |
|
|
T21 |
4 |
|
T24 |
1 |
|
T36 |
8 |
auto[1] |
auto[0] |
30562 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1535 |
1 |
|
|
T18 |
9 |
|
T280 |
7 |
|
T49 |
3 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71848 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[0] |
auto[1] |
2259 |
1 |
|
|
T21 |
9 |
|
T36 |
13 |
|
T16 |
1 |
auto[1] |
auto[0] |
30485 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1612 |
1 |
|
|
T17 |
2 |
|
T18 |
10 |
|
T42 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71921 |
1 |
|
|
T1 |
75 |
|
T2 |
8 |
|
T3 |
58 |
auto[0] |
auto[1] |
2186 |
1 |
|
|
T2 |
2 |
|
T21 |
7 |
|
T36 |
11 |
auto[1] |
auto[0] |
30466 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1631 |
1 |
|
|
T17 |
1 |
|
T18 |
8 |
|
T42 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71813 |
1 |
|
|
T1 |
75 |
|
T2 |
9 |
|
T3 |
58 |
auto[0] |
auto[1] |
2294 |
1 |
|
|
T2 |
1 |
|
T21 |
8 |
|
T24 |
3 |
auto[1] |
auto[0] |
30554 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1543 |
1 |
|
|
T18 |
9 |
|
T42 |
3 |
|
T280 |
12 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71820 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
58 |
auto[0] |
auto[1] |
2287 |
1 |
|
|
T21 |
5 |
|
T24 |
1 |
|
T36 |
8 |
auto[1] |
auto[0] |
30566 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1531 |
1 |
|
|
T17 |
1 |
|
T18 |
9 |
|
T280 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72046 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
53 |
auto[0] |
auto[1] |
2061 |
1 |
|
|
T3 |
5 |
|
T10 |
10 |
|
T37 |
4 |
auto[1] |
auto[0] |
30569 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1528 |
1 |
|
|
T19 |
15 |
|
T91 |
5 |
|
T49 |
5 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72056 |
1 |
|
|
T1 |
75 |
|
T2 |
10 |
|
T3 |
51 |
auto[0] |
auto[1] |
2051 |
1 |
|
|
T3 |
7 |
|
T10 |
10 |
|
T37 |
8 |
auto[1] |
auto[0] |
30628 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
1469 |
1 |
|
|
T19 |
9 |
|
T91 |
8 |
|
T49 |
8 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71229 |
1 |
|
|
T1 |
75 |
|
T3 |
58 |
|
T8 |
16 |
auto[0] |
auto[1] |
2878 |
1 |
|
|
T2 |
10 |
|
T24 |
12 |
|
T16 |
10 |
auto[1] |
auto[0] |
29862 |
1 |
|
|
T4 |
10 |
|
T15 |
17 |
|
T16 |
26 |
auto[1] |
auto[1] |
2235 |
1 |
|
|
T17 |
10 |
|
T42 |
15 |
|
T49 |
24 |