Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203464149

1

T1

23703

T2

6232

T3

17615

auto[1]

2814838

1

T2

99

T3

495

T9

1683

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203473097

1

T1

23703

T2

5935

T3

17516

auto[1]

2805890

1

T2

396

T3

594

T9

1881

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	14624661	1			T1	8107		T2	937		T3	6022
auto[IdleSt]	43878713	1			T1	2153		T2	1710		T3	1983
auto[ClkMuxSt]	69050	1			T1	75		T2	5		T3	57
auto[CntIncrSt]	68550	1			T1	75		T2	5		T3	57
auto[CntProgSt]	2791914	1			T1	150		T2	225		T3	91
auto[TransCheckSt]	53814	1			T1	75		T2	5		T3	40
auto[TokenHashSt]	79842601	1			T1	1329		T2	56		T3	697
auto[FlashRmaSt]	55981	1			T1	64		T2	5		T3	16
auto[TokenCheck0St]	24988	1			T1	24		T2	5		T3	16
auto[TokenCheck1St]	18443	1			T1	8		T2	5		T3	9
auto[TransProgSt]	703631	1			T2	249		T3	16		T8	50
auto[PostTransSt]	25822218	1			T1	11643		T2	1231		T3	7724
auto[ScrapSt]	432572	1			T8	19		T25	3		T45	26
auto[EscalateSt]	13791799	1			T2	1176		T3	1382		T9	5229
auto[InvalidSt]	24096049	1			T2	717		T9	3202		T11	2089

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	4003	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	24096049	1			T2	717		T9	3202		T11	2089
EscalateSt	13791799	1			T2	1176		T3	1382		T9	5229
ScrapSt	432572	1			T8	19		T25	3		T45	26
PostTransSt	25822218	1			T1	11643		T2	1231		T3	7724
TransProgSt	703631	1			T2	249		T3	16		T8	50
TokenCheck1St	18443	1			T1	8		T2	5		T3	9
TokenCheck0St	24988	1			T1	24		T2	5		T3	16
FlashRmaSt	55981	1			T1	64		T2	5		T3	16
TokenHashSt	79842601	1			T1	1329		T2	56		T3	697
TransCheckSt	53814	1			T1	75		T2	5		T3	40
CntProgSt	2791914	1			T1	150		T2	225		T3	91
CntIncrSt	68550	1			T1	75		T2	5		T3	57
ClkMuxSt	69050	1			T1	75		T2	5		T3	57
IdleSt	43878713	1			T1	2153		T2	1710		T3	1983
ResetSt	14624661	1			T1	8107		T2	937		T3	6022
arcs[ResetSt=>IdleSt]	106446	1			T1	76		T2	11		T3	59
arcs[IdleSt=>ScrapSt]	600	1			T8	1		T25	1		T45	1
arcs[IdleSt=>ClkMuxSt]	68673	1			T1	75		T2	5		T3	57
arcs[ClkMuxSt=>CntIncrSt]	68550	1			T1	75		T2	5		T3	57
arcs[CntIncrSt=>PostTransSt]	3167	1			T3	6		T10	10		T37	5
arcs[CntIncrSt=>CntProgSt]	65244	1			T1	75		T2	5		T3	51
arcs[CntProgSt=>PostTransSt]	9272	1			T3	11		T9	19		T10	6
arcs[CntProgSt=>TransCheckSt]	53814	1			T1	75		T2	5		T3	40
arcs[TransCheckSt=>PostTransSt]	7367	1			T1	40		T3	5		T10	10
arcs[TransCheckSt=>TokenHashSt]	46220	1			T1	35		T2	5		T3	35
arcs[TokenHashSt=>PostTransSt]	19736	1			T1	11		T3	19		T9	6
arcs[TokenHashSt=>FlashRmaSt]	25184	1			T1	24		T2	5		T3	16
arcs[FlashRmaSt=>TokenCheck0St]	24988	1			T1	24		T2	5		T3	16
arcs[TokenCheck0St=>PostTransSt]	6491	1			T1	16		T3	7		T9	19
arcs[TokenCheck0St=>TokenCheck1St]	18443	1			T1	8		T2	5		T3	9
arcs[TokenCheck1St=>PostTransSt]	1334	1			T1	8		T3	1		T11	2
arcs[TransProgSt=>PostTransSt]	15318	1			T2	5		T3	8		T8	15
arcs[IdleSt=>EscalateSt]	459	1			T25	2		T54	3		T55	6
arcs[ClkMuxSt=>EscalateSt]	123	1			T25	4		T54	3		T55	1
arcs[CntIncrSt=>EscalateSt]	139	1			T25	1		T54	1		T55	1
arcs[CntProgSt=>EscalateSt]	2158	1			T25	28		T54	7		T55	6
arcs[TransCheckSt=>EscalateSt]	227	1			T54	10		T55	9		T60	1
arcs[TokenHashSt=>EscalateSt]	1299	1			T25	6		T54	30		T55	13
arcs[FlashRmaSt=>EscalateSt]	196	1			T25	3		T54	6		T55	2
arcs[TokenCheck0St=>EscalateSt]	54	1			T54	1		T55	1		T56	2
arcs[TokenCheck1St=>EscalateSt]	280	1			T54	1		T55	2		T56	2
arcs[TransProgSt=>EscalateSt]	1511	1			T25	23		T54	10		T55	9
arcs[PostTransSt=>EscalateSt]	9766	1			T3	11		T9	19		T10	6
arcs[InvalidSt=>EscalateSt]	28222	1			T2	5		T9	17		T11	14

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14624291	1			T1	8107		T2	937		T3	6022
auto[0]	auto[IdleSt]	43878400	1			T1	2153		T2	1710		T3	1983
auto[0]	auto[ClkMuxSt]	68973	1			T1	75		T2	5		T3	57
auto[0]	auto[CntIncrSt]	68463	1			T1	75		T2	5		T3	57
auto[0]	auto[CntProgSt]	2790455	1			T1	150		T2	225		T3	91
auto[0]	auto[TransCheckSt]	53655	1			T1	75		T2	5		T3	40
auto[0]	auto[TokenHashSt]	79841755	1			T1	1329		T2	56		T3	697
auto[0]	auto[FlashRmaSt]	55855	1			T1	64		T2	5		T3	16
auto[0]	auto[TokenCheck0St]	24954	1			T1	24		T2	5		T3	16
auto[0]	auto[TokenCheck1St]	18244	1			T1	8		T2	5		T3	9
auto[0]	auto[TransProgSt]	702630	1			T2	249		T3	16		T8	50
auto[0]	auto[PostTransSt]	25817294	1			T1	11643		T2	1231		T3	7719
auto[0]	auto[ScrapSt]	432484	1			T8	19		T25	2		T45	26
auto[0]	auto[EscalateSt]	11000842	1			T2	1078		T3	892		T9	3563
auto[0]	auto[InvalidSt]	24081851	1			T2	716		T9	3194		T11	2082
auto[1]	auto[ResetSt]	370	1			T25	3		T54	3		T55	4
auto[1]	auto[IdleSt]	313	1			T54	2		T55	4		T56	3
auto[1]	auto[ClkMuxSt]	77	1			T25	2		T54	2		T55	1
auto[1]	auto[CntIncrSt]	87	1			T25	1		T54	1		T56	1
auto[1]	auto[CntProgSt]	1459	1			T25	19		T54	5		T55	4
auto[1]	auto[TransCheckSt]	159	1			T54	5		T55	6		T60	1
auto[1]	auto[TokenHashSt]	846	1			T25	5		T54	17		T55	6
auto[1]	auto[FlashRmaSt]	126	1			T25	3		T54	3		T273	1
auto[1]	auto[TokenCheck0St]	34	1			T55	1		T56	2		T274	1
auto[1]	auto[TokenCheck1St]	199	1			T54	1		T55	2		T56	2
auto[1]	auto[TransProgSt]	1001	1			T25	16		T54	9		T55	6
auto[1]	auto[PostTransSt]	4924	1			T3	5		T9	9		T10	3
auto[1]	auto[ScrapSt]	88	1			T25	1		T55	1		T56	3
auto[1]	auto[EscalateSt]	2790957	1			T2	98		T3	490		T9	1666
auto[1]	auto[InvalidSt]	14198	1			T2	1		T9	8		T11	7

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14624268	1			T1	8107		T2	937		T3	6022
auto[0]	auto[IdleSt]	43878408	1			T1	2153		T2	1710		T3	1983
auto[0]	auto[ClkMuxSt]	68966	1			T1	75		T2	5		T3	57
auto[0]	auto[CntIncrSt]	68460	1			T1	75		T2	5		T3	57
auto[0]	auto[CntProgSt]	2790496	1			T1	150		T2	225		T3	91
auto[0]	auto[TransCheckSt]	53666	1			T1	75		T2	5		T3	40
auto[0]	auto[TokenHashSt]	79841724	1			T1	1329		T2	56		T3	697
auto[0]	auto[FlashRmaSt]	55846	1			T1	64		T2	5		T3	16
auto[0]	auto[TokenCheck0St]	24953	1			T1	24		T2	5		T3	16
auto[0]	auto[TokenCheck1St]	18258	1			T1	8		T2	5		T3	9
auto[0]	auto[TransProgSt]	702613	1			T2	249		T3	16		T8	50
auto[0]	auto[PostTransSt]	25817227	1			T1	11643		T2	1231		T3	7718
auto[0]	auto[ScrapSt]	432492	1			T8	19		T25	3		T45	26
auto[0]	auto[EscalateSt]	11009692	1			T2	784		T3	794		T9	3367
auto[0]	auto[InvalidSt]	24082025	1			T2	713		T9	3193		T11	2082
auto[1]	auto[ResetSt]	393	1			T25	2		T54	5		T55	2
auto[1]	auto[IdleSt]	305	1			T25	2		T54	3		T55	5
auto[1]	auto[ClkMuxSt]	84	1			T25	2		T54	2		T55	1
auto[1]	auto[CntIncrSt]	90	1			T55	1		T273	1		T274	2
auto[1]	auto[CntProgSt]	1418	1			T25	23		T54	4		T55	3
auto[1]	auto[TransCheckSt]	148	1			T54	7		T55	5		T275	1
auto[1]	auto[TokenHashSt]	877	1			T25	3		T54	20		T55	11
auto[1]	auto[FlashRmaSt]	135	1			T54	3		T55	2		T56	1
auto[1]	auto[TokenCheck0St]	35	1			T54	1		T56	1		T276	1
auto[1]	auto[TokenCheck1St]	185	1			T55	2		T56	1		T273	1
auto[1]	auto[TransProgSt]	1018	1			T25	19		T54	5		T55	6
auto[1]	auto[PostTransSt]	4991	1			T3	6		T9	10		T10	3
auto[1]	auto[ScrapSt]	80	1			T55	1		T56	3		T274	1
auto[1]	auto[EscalateSt]	2782107	1			T2	392		T3	588		T9	1862
auto[1]	auto[InvalidSt]	14024	1			T2	4		T9	9		T11	7