Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217677852

1

T1

37799

T2

531594

T3

3550

auto[1]

2852571

1

T1

3366

T2

6872

T9

13673

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217688245

1

T1

36611

T2

531785

T3

3550

auto[1]

2842178

1

T1

4554

T2

6681

T9

14738

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	14559508	1			T1	14860		T2	53369		T3	1289
auto[IdleSt]	44221096	1			T1	1772		T2	47247		T3	384
auto[ClkMuxSt]	72920	1			T2	145		T3	23		T9	84
auto[CntIncrSt]	72382	1			T2	144		T3	14		T9	83
auto[CntProgSt]	3308367	1			T2	3094		T3	52		T9	2424
auto[TransCheckSt]	56327	1			T2	115		T3	14		T9	43
auto[TokenHashSt]	95802914	1			T2	93265		T3	417		T9	16134
auto[FlashRmaSt]	58933	1			T2	86		T3	14		T9	63
auto[TokenCheck0St]	25970	1			T2	65		T3	14		T9	32
auto[TokenCheck1St]	19337	1			T2	59		T3	14		T9	31
auto[TransProgSt]	844068	1			T2	1498		T3	60		T9	105
auto[PostTransSt]	26352881	1			T2	37076		T3	1255		T9	5
auto[ScrapSt]	265036	1			T2	5061		T9	3		T5	5211
auto[EscalateSt]	13334563	1			T1	11227		T2	75048		T9	20403
auto[InvalidSt]	21532172	1			T1	13295		T2	222174		T5	157316

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3949	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	21532172	1			T1	13295		T2	222174		T5	157316
EscalateSt	13334563	1			T1	11227		T2	75048		T9	20403
ScrapSt	265036	1			T2	5061		T9	3		T5	5211
PostTransSt	26352881	1			T2	37076		T3	1255		T9	5
TransProgSt	844068	1			T2	1498		T3	60		T9	105
TokenCheck1St	19337	1			T2	59		T3	14		T9	31
TokenCheck0St	25970	1			T2	65		T3	14		T9	32
FlashRmaSt	58933	1			T2	86		T3	14		T9	63
TokenHashSt	95802914	1			T2	93265		T3	417		T9	16134
TransCheckSt	56327	1			T2	115		T3	14		T9	43
CntProgSt	3308367	1			T2	3094		T3	52		T9	2424
CntIncrSt	72382	1			T2	144		T3	14		T9	83
ClkMuxSt	72920	1			T2	145		T3	23		T9	84
IdleSt	44221096	1			T1	1772		T2	47247		T3	384
ResetSt	14559508	1			T1	14860		T2	53369		T3	1289
arcs[ResetSt=>IdleSt]	110507	1			T1	92		T2	290		T3	14
arcs[IdleSt=>ScrapSt]	569	1			T2	3		T9	1		T5	11
arcs[IdleSt=>ClkMuxSt]	72496	1			T2	144		T3	14		T9	84
arcs[ClkMuxSt=>CntIncrSt]	72382	1			T2	144		T3	14		T9	83
arcs[CntIncrSt=>PostTransSt]	3502	1			T2	12		T5	76		T16	7
arcs[CntIncrSt=>CntProgSt]	68738	1			T2	132		T3	14		T9	78
arcs[CntProgSt=>PostTransSt]	10255	1			T2	17		T5	196		T13	16
arcs[CntProgSt=>TransCheckSt]	56327	1			T2	115		T3	14		T9	43
arcs[TransCheckSt=>PostTransSt]	7460	1			T2	18		T5	95		T15	27
arcs[TransCheckSt=>TokenHashSt]	48593	1			T2	97		T3	14		T9	42
arcs[TokenHashSt=>PostTransSt]	20957	1			T2	32		T11	63		T5	291
arcs[TokenHashSt=>FlashRmaSt]	26176	1			T2	65		T3	14		T9	36
arcs[FlashRmaSt=>TokenCheck0St]	25970	1			T2	65		T3	14		T9	32
arcs[TokenCheck0St=>PostTransSt]	6580	1			T2	6		T5	100		T13	11
arcs[TokenCheck0St=>TokenCheck1St]	19337	1			T2	59		T3	14		T9	31
arcs[TokenCheck1St=>PostTransSt]	1339	1			T5	10		T15	5		T27	7
arcs[TransProgSt=>PostTransSt]	16207	1			T2	59		T3	14		T9	2
arcs[IdleSt=>EscalateSt]	361	1			T9	10		T48	5		T51	13
arcs[ClkMuxSt=>EscalateSt]	114	1			T9	1		T12	1		T48	1
arcs[CntIncrSt=>EscalateSt]	142	1			T9	5		T49	2		T48	2
arcs[CntProgSt=>EscalateSt]	2156	1			T9	35		T12	44		T49	25
arcs[TransCheckSt=>EscalateSt]	274	1			T9	1		T50	8		T55	12
arcs[TokenHashSt=>EscalateSt]	1458	1			T9	6		T12	10		T19	1
arcs[FlashRmaSt=>EscalateSt]	206	1			T9	4		T12	3		T50	2
arcs[TokenCheck0St=>EscalateSt]	53	1			T9	1		T49	1		T50	1
arcs[TokenCheck1St=>EscalateSt]	304	1			T9	2		T12	2		T48	3
arcs[TransProgSt=>EscalateSt]	1487	1			T9	27		T12	25		T49	8
arcs[PostTransSt=>EscalateSt]	10744	1			T2	17		T9	2		T5	196
arcs[InvalidSt=>EscalateSt]	28388	1			T1	80		T2	121		T5	407

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14559194	1			T1	14860		T2	53369		T3	1289
auto[0]	auto[IdleSt]	44220861	1			T1	1772		T2	47247		T3	384
auto[0]	auto[ClkMuxSt]	72845	1			T2	145		T3	23		T9	83
auto[0]	auto[CntIncrSt]	72292	1			T2	144		T3	14		T9	80
auto[0]	auto[CntProgSt]	3306915	1			T2	3094		T3	52		T9	2401
auto[0]	auto[TransCheckSt]	56141	1			T2	115		T3	14		T9	42
auto[0]	auto[TokenHashSt]	95801977	1			T2	93265		T3	417		T9	16130
auto[0]	auto[FlashRmaSt]	58793	1			T2	86		T3	14		T9	60
auto[0]	auto[TokenCheck0St]	25932	1			T2	65		T3	14		T9	31
auto[0]	auto[TokenCheck1St]	19137	1			T2	59		T3	14		T9	31
auto[0]	auto[TransProgSt]	843082	1			T2	1498		T3	60		T9	86
auto[0]	auto[PostTransSt]	26347389	1			T2	37070		T3	1255		T9	4
auto[0]	auto[ScrapSt]	264952	1			T2	5061		T9	3		T5	5211
auto[0]	auto[EscalateSt]	10506467	1			T1	7895		T2	68246		T9	6797
auto[0]	auto[InvalidSt]	21517926	1			T1	13261		T2	222110		T5	157110
auto[1]	auto[ResetSt]	314	1			T9	3		T12	7		T49	2
auto[1]	auto[IdleSt]	235	1			T9	8		T48	5		T51	7
auto[1]	auto[ClkMuxSt]	75	1			T9	1		T12	1		T51	1
auto[1]	auto[CntIncrSt]	90	1			T9	3		T49	2		T48	1
auto[1]	auto[CntProgSt]	1452	1			T9	23		T12	32		T49	17
auto[1]	auto[TransCheckSt]	186	1			T9	1		T50	6		T55	9
auto[1]	auto[TokenHashSt]	937	1			T9	4		T12	7		T49	8
auto[1]	auto[FlashRmaSt]	140	1			T9	3		T12	2		T50	2
auto[1]	auto[TokenCheck0St]	38	1			T9	1		T50	1		T55	2
auto[1]	auto[TokenCheck1St]	200	1			T12	1		T48	2		T51	3
auto[1]	auto[TransProgSt]	986	1			T9	19		T12	17		T49	5
auto[1]	auto[PostTransSt]	5492	1			T2	6		T9	1		T5	100
auto[1]	auto[ScrapSt]	84	1			T12	2		T49	1		T51	1
auto[1]	auto[EscalateSt]	2828096	1			T1	3332		T2	6802		T9	13606
auto[1]	auto[InvalidSt]	14246	1			T1	34		T2	64		T5	206

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14559183	1			T1	14860		T2	53369		T3	1289
auto[0]	auto[IdleSt]	44220850	1			T1	1772		T2	47247		T3	384
auto[0]	auto[ClkMuxSt]	72846	1			T2	145		T3	23		T9	83
auto[0]	auto[CntIncrSt]	72278	1			T2	144		T3	14		T9	80
auto[0]	auto[CntProgSt]	3306956	1			T2	3094		T3	52		T9	2401
auto[0]	auto[TransCheckSt]	56137	1			T2	115		T3	14		T9	43
auto[0]	auto[TokenHashSt]	95801945	1			T2	93265		T3	417		T9	16130
auto[0]	auto[FlashRmaSt]	58797	1			T2	86		T3	14		T9	59
auto[0]	auto[TokenCheck0St]	25936	1			T2	65		T3	14		T9	31
auto[0]	auto[TokenCheck1St]	19130	1			T2	59		T3	14		T9	29
auto[0]	auto[TransProgSt]	843090	1			T2	1498		T3	60		T9	85
auto[0]	auto[PostTransSt]	26347462	1			T2	37065		T3	1255		T9	3
auto[0]	auto[ScrapSt]	264959	1			T2	5061		T9	2		T5	5211
auto[0]	auto[EscalateSt]	10516697	1			T1	6719		T2	68435		T9	5737
auto[0]	auto[InvalidSt]	21518030	1			T1	13249		T2	222117		T5	157115
auto[1]	auto[ResetSt]	325	1			T9	3		T12	5		T49	4
auto[1]	auto[IdleSt]	246	1			T9	8		T48	3		T51	10
auto[1]	auto[ClkMuxSt]	74	1			T9	1		T48	1		T51	3
auto[1]	auto[CntIncrSt]	104	1			T9	3		T49	2		T48	1
auto[1]	auto[CntProgSt]	1411	1			T9	23		T12	28		T49	16
auto[1]	auto[TransCheckSt]	190	1			T50	6		T55	7		T266	1
auto[1]	auto[TokenHashSt]	969	1			T9	4		T12	7		T19	1
auto[1]	auto[FlashRmaSt]	136	1			T9	4		T12	1		T50	1
auto[1]	auto[TokenCheck0St]	34	1			T9	1		T49	1		T50	1
auto[1]	auto[TokenCheck1St]	207	1			T9	2		T12	1		T48	3
auto[1]	auto[TransProgSt]	978	1			T9	20		T12	16		T49	4
auto[1]	auto[PostTransSt]	5419	1			T2	11		T9	2		T5	96
auto[1]	auto[ScrapSt]	77	1			T9	1		T12	2		T48	1
auto[1]	auto[EscalateSt]	2817866	1			T1	4508		T2	6613		T9	14666
auto[1]	auto[InvalidSt]	14142	1			T1	46		T2	57		T5	201