Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.30 97.79 95.89 93.30 100.00 98.34 99.00 96.79


Total test records in report: 2003
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html
T1778 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2105630704 Mar 26 02:51:52 PM PDT 24 Mar 26 02:51:53 PM PDT 24 216398466 ps
T1779 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3051944148 Mar 26 02:51:22 PM PDT 24 Mar 26 02:51:23 PM PDT 24 19310516 ps
T1780 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2531810370 Mar 26 02:51:50 PM PDT 24 Mar 26 02:52:00 PM PDT 24 2834530534 ps
T1781 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2544236193 Mar 26 02:52:08 PM PDT 24 Mar 26 02:52:09 PM PDT 24 13012285 ps
T155 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2649435769 Mar 26 02:52:07 PM PDT 24 Mar 26 02:52:10 PM PDT 24 106299311 ps
T1782 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1700406413 Mar 26 02:51:59 PM PDT 24 Mar 26 02:52:02 PM PDT 24 70710892 ps
T1783 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1781886117 Mar 26 02:51:15 PM PDT 24 Mar 26 02:51:16 PM PDT 24 24304111 ps
T1784 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2698317764 Mar 26 02:52:13 PM PDT 24 Mar 26 02:52:20 PM PDT 24 300675207 ps
T1785 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.111081371 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:07 PM PDT 24 148929795 ps
T170 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4268706810 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:08 PM PDT 24 167415049 ps
T1786 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.969325815 Mar 26 02:44:09 PM PDT 24 Mar 26 02:44:10 PM PDT 24 34973173 ps
T1787 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3027901997 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:10 PM PDT 24 74664939 ps
T1788 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3081656304 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:44 PM PDT 24 137515773 ps
T1789 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2831915692 Mar 26 02:51:56 PM PDT 24 Mar 26 02:52:02 PM PDT 24 220502821 ps
T1790 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.384178714 Mar 26 02:52:06 PM PDT 24 Mar 26 02:52:08 PM PDT 24 118179279 ps
T1791 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.156371361 Mar 26 02:51:14 PM PDT 24 Mar 26 02:51:16 PM PDT 24 28206332 ps
T1792 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3573819812 Mar 26 02:51:19 PM PDT 24 Mar 26 02:51:21 PM PDT 24 155697423 ps
T1793 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2612263377 Mar 26 02:51:16 PM PDT 24 Mar 26 02:51:18 PM PDT 24 290454895 ps
T1794 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2921575149 Mar 26 02:51:48 PM PDT 24 Mar 26 02:51:49 PM PDT 24 55757308 ps
T1795 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3382700481 Mar 26 02:52:07 PM PDT 24 Mar 26 02:52:09 PM PDT 24 40374308 ps
T1796 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.705162879 Mar 26 02:51:59 PM PDT 24 Mar 26 02:52:01 PM PDT 24 39880201 ps
T1797 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4275306996 Mar 26 02:51:27 PM PDT 24 Mar 26 02:51:31 PM PDT 24 168640688 ps
T1798 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2516734404 Mar 26 02:43:57 PM PDT 24 Mar 26 02:44:00 PM PDT 24 360106717 ps
T159 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1483887955 Mar 26 02:52:10 PM PDT 24 Mar 26 02:52:13 PM PDT 24 45294641 ps
T1799 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2429010005 Mar 26 02:51:50 PM PDT 24 Mar 26 02:51:57 PM PDT 24 425190687 ps
T1800 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1171023228 Mar 26 02:43:48 PM PDT 24 Mar 26 02:43:49 PM PDT 24 56267321 ps
T1801 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.317249007 Mar 26 02:51:50 PM PDT 24 Mar 26 02:51:51 PM PDT 24 18193251 ps
T1802 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1297388837 Mar 26 02:43:46 PM PDT 24 Mar 26 02:43:47 PM PDT 24 17716168 ps
T1803 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2954443220 Mar 26 02:43:34 PM PDT 24 Mar 26 02:43:35 PM PDT 24 29900582 ps
T1804 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3526826022 Mar 26 02:43:24 PM PDT 24 Mar 26 02:43:25 PM PDT 24 23962728 ps
T1805 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3304710522 Mar 26 02:51:55 PM PDT 24 Mar 26 02:51:56 PM PDT 24 17787441 ps
T1806 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3456448565 Mar 26 02:51:45 PM PDT 24 Mar 26 02:51:46 PM PDT 24 28575015 ps
T1807 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2389448108 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:07 PM PDT 24 88449178 ps
T1808 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2819324864 Mar 26 02:43:59 PM PDT 24 Mar 26 02:44:08 PM PDT 24 1279192305 ps
T1809 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3076890447 Mar 26 02:51:25 PM PDT 24 Mar 26 02:51:38 PM PDT 24 1351076594 ps
T1810 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.259644875 Mar 26 02:51:50 PM PDT 24 Mar 26 02:51:52 PM PDT 24 58721776 ps
T168 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.692651606 Mar 26 02:44:00 PM PDT 24 Mar 26 02:44:03 PM PDT 24 235055237 ps
T154 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1257636480 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:10 PM PDT 24 123757979 ps
T1811 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1697980036 Mar 26 02:43:36 PM PDT 24 Mar 26 02:43:38 PM PDT 24 53491755 ps
T1812 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.930242014 Mar 26 02:43:25 PM PDT 24 Mar 26 02:43:28 PM PDT 24 418448934 ps
T1813 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3380626737 Mar 26 02:44:10 PM PDT 24 Mar 26 02:44:13 PM PDT 24 596920356 ps
T1814 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1633078052 Mar 26 02:52:12 PM PDT 24 Mar 26 02:52:13 PM PDT 24 43306123 ps
T1815 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2917920119 Mar 26 02:43:34 PM PDT 24 Mar 26 02:43:41 PM PDT 24 1623733010 ps
T1816 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3028309523 Mar 26 02:44:07 PM PDT 24 Mar 26 02:44:11 PM PDT 24 147550564 ps
T1817 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2914719956 Mar 26 02:51:15 PM PDT 24 Mar 26 02:51:17 PM PDT 24 210973861 ps
T1818 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4245126253 Mar 26 02:51:31 PM PDT 24 Mar 26 02:51:35 PM PDT 24 107271403 ps
T237 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3975883995 Mar 26 02:51:54 PM PDT 24 Mar 26 02:51:55 PM PDT 24 15797013 ps
T1819 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.290554560 Mar 26 02:51:21 PM PDT 24 Mar 26 02:51:23 PM PDT 24 303232420 ps
T160 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4083040031 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:09 PM PDT 24 107805589 ps
T238 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2667703609 Mar 26 02:51:51 PM PDT 24 Mar 26 02:51:53 PM PDT 24 16498426 ps
T1820 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3988514713 Mar 26 02:44:07 PM PDT 24 Mar 26 02:44:09 PM PDT 24 108852006 ps
T1821 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2047806595 Mar 26 02:51:47 PM PDT 24 Mar 26 02:51:50 PM PDT 24 448385274 ps
T1822 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2930768940 Mar 26 02:51:14 PM PDT 24 Mar 26 02:51:17 PM PDT 24 94861195 ps
T1823 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2035384969 Mar 26 02:43:47 PM PDT 24 Mar 26 02:43:48 PM PDT 24 183239758 ps
T1824 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4145158403 Mar 26 02:51:55 PM PDT 24 Mar 26 02:51:56 PM PDT 24 16333238 ps
T1825 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1824352699 Mar 26 02:43:57 PM PDT 24 Mar 26 02:44:07 PM PDT 24 758737578 ps
T1826 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.372008670 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:10 PM PDT 24 60084346 ps
T1827 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3036184985 Mar 26 02:43:37 PM PDT 24 Mar 26 02:43:38 PM PDT 24 57970866 ps
T1828 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1021711369 Mar 26 02:52:10 PM PDT 24 Mar 26 02:52:12 PM PDT 24 110485629 ps
T1829 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3595689411 Mar 26 02:43:58 PM PDT 24 Mar 26 02:44:00 PM PDT 24 100792986 ps
T1830 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2202194283 Mar 26 02:52:05 PM PDT 24 Mar 26 02:52:06 PM PDT 24 103545831 ps
T239 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1901412078 Mar 26 02:52:09 PM PDT 24 Mar 26 02:52:10 PM PDT 24 27839933 ps
T1831 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1512996639 Mar 26 02:51:15 PM PDT 24 Mar 26 02:51:16 PM PDT 24 159176143 ps
T1832 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1047035859 Mar 26 02:51:49 PM PDT 24 Mar 26 02:51:51 PM PDT 24 48732240 ps
T1833 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3146558765 Mar 26 02:52:07 PM PDT 24 Mar 26 02:52:08 PM PDT 24 121962281 ps
T1834 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3165210963 Mar 26 02:51:53 PM PDT 24 Mar 26 02:51:56 PM PDT 24 155831692 ps
T169 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1536470283 Mar 26 02:51:42 PM PDT 24 Mar 26 02:51:44 PM PDT 24 329723085 ps
T1835 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2224838432 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:09 PM PDT 24 94815845 ps
T167 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1403165485 Mar 26 02:51:18 PM PDT 24 Mar 26 02:51:25 PM PDT 24 4480908919 ps
T1836 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2314274226 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:23 PM PDT 24 89540156 ps
T1837 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.139546026 Mar 26 02:44:10 PM PDT 24 Mar 26 02:44:11 PM PDT 24 29538988 ps
T1838 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.333076200 Mar 26 02:52:13 PM PDT 24 Mar 26 02:52:14 PM PDT 24 38727417 ps
T1839 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1478441633 Mar 26 02:44:05 PM PDT 24 Mar 26 02:44:07 PM PDT 24 67152141 ps
T1840 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2513570703 Mar 26 02:43:56 PM PDT 24 Mar 26 02:43:57 PM PDT 24 14991662 ps
T1841 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.754380397 Mar 26 02:51:37 PM PDT 24 Mar 26 02:51:38 PM PDT 24 74267669 ps
T1842 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3657761920 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:08 PM PDT 24 23684705 ps
T1843 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1329881000 Mar 26 02:52:06 PM PDT 24 Mar 26 02:52:07 PM PDT 24 20469910 ps
T1844 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.125924682 Mar 26 02:51:57 PM PDT 24 Mar 26 02:52:08 PM PDT 24 14425121691 ps
T1845 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1822712361 Mar 26 02:43:25 PM PDT 24 Mar 26 02:43:27 PM PDT 24 471054770 ps
T1846 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1081252924 Mar 26 02:43:58 PM PDT 24 Mar 26 02:44:00 PM PDT 24 213061004 ps
T1847 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1742511330 Mar 26 02:51:17 PM PDT 24 Mar 26 02:51:19 PM PDT 24 238800603 ps
T1848 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1182491322 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:23 PM PDT 24 144931628 ps
T1849 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1926077985 Mar 26 02:51:19 PM PDT 24 Mar 26 02:51:21 PM PDT 24 29563560 ps
T1850 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4269425271 Mar 26 02:43:37 PM PDT 24 Mar 26 02:43:58 PM PDT 24 3543980303 ps
T1851 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3689589392 Mar 26 02:44:00 PM PDT 24 Mar 26 02:44:04 PM PDT 24 116140827 ps
T1852 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.475010517 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:09 PM PDT 24 24917660 ps
T1853 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1780126685 Mar 26 02:52:07 PM PDT 24 Mar 26 02:52:11 PM PDT 24 443877092 ps
T1854 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3391870354 Mar 26 02:43:44 PM PDT 24 Mar 26 02:43:47 PM PDT 24 433408596 ps
T1855 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3664071717 Mar 26 02:51:55 PM PDT 24 Mar 26 02:52:00 PM PDT 24 1826859679 ps
T1856 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4292625242 Mar 26 02:51:16 PM PDT 24 Mar 26 02:51:19 PM PDT 24 84222096 ps
T164 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3735808393 Mar 26 02:52:12 PM PDT 24 Mar 26 02:52:16 PM PDT 24 101917169 ps
T241 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.199098708 Mar 26 02:44:07 PM PDT 24 Mar 26 02:44:08 PM PDT 24 16475221 ps
T1857 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.212278151 Mar 26 02:52:01 PM PDT 24 Mar 26 02:52:02 PM PDT 24 15111327 ps
T1858 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.444706873 Mar 26 02:43:35 PM PDT 24 Mar 26 02:43:36 PM PDT 24 24771734 ps
T1859 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1246289403 Mar 26 02:43:59 PM PDT 24 Mar 26 02:44:02 PM PDT 24 168187399 ps
T1860 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1652416546 Mar 26 02:51:44 PM PDT 24 Mar 26 02:51:46 PM PDT 24 66799606 ps
T1861 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.444811539 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:31 PM PDT 24 807190468 ps
T1862 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.244378231 Mar 26 02:44:09 PM PDT 24 Mar 26 02:44:11 PM PDT 24 25952052 ps
T1863 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2659654567 Mar 26 02:43:37 PM PDT 24 Mar 26 02:43:38 PM PDT 24 96215123 ps
T240 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1492658674 Mar 26 02:51:58 PM PDT 24 Mar 26 02:51:59 PM PDT 24 118094267 ps
T234 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1178060893 Mar 26 02:44:05 PM PDT 24 Mar 26 02:44:07 PM PDT 24 47085270 ps
T1864 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2179579542 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:43 PM PDT 24 43368847 ps
T1865 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1902638665 Mar 26 02:43:58 PM PDT 24 Mar 26 02:44:00 PM PDT 24 44372437 ps
T151 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1730996743 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:11 PM PDT 24 1625493402 ps
T143 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.456213801 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:09 PM PDT 24 76325276 ps
T1866 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.226376025 Mar 26 02:44:13 PM PDT 24 Mar 26 02:44:14 PM PDT 24 92598113 ps
T1867 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2967358915 Mar 26 02:51:58 PM PDT 24 Mar 26 02:52:08 PM PDT 24 1745178282 ps
T1868 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1057678525 Mar 26 02:51:22 PM PDT 24 Mar 26 02:51:24 PM PDT 24 93861739 ps
T1869 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2829435416 Mar 26 02:51:14 PM PDT 24 Mar 26 02:51:15 PM PDT 24 13053512 ps
T1870 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3508950893 Mar 26 02:51:54 PM PDT 24 Mar 26 02:51:59 PM PDT 24 802104963 ps
T1871 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3959208710 Mar 26 02:52:13 PM PDT 24 Mar 26 02:52:29 PM PDT 24 703212654 ps
T1872 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.398237206 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:43 PM PDT 24 38306998 ps
T1873 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2580706307 Mar 26 02:51:48 PM PDT 24 Mar 26 02:51:50 PM PDT 24 65362997 ps
T242 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1788564337 Mar 26 02:43:26 PM PDT 24 Mar 26 02:43:27 PM PDT 24 15995013 ps
T1874 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4185704157 Mar 26 02:43:40 PM PDT 24 Mar 26 02:43:42 PM PDT 24 235529653 ps
T1875 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1157251479 Mar 26 02:52:07 PM PDT 24 Mar 26 02:52:10 PM PDT 24 47705272 ps
T1876 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1901376376 Mar 26 02:52:05 PM PDT 24 Mar 26 02:52:07 PM PDT 24 43997622 ps
T1877 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1706077404 Mar 26 02:51:49 PM PDT 24 Mar 26 02:51:51 PM PDT 24 61145554 ps
T1878 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.313617068 Mar 26 02:51:54 PM PDT 24 Mar 26 02:51:56 PM PDT 24 24767200 ps
T1879 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1390702092 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:10 PM PDT 24 228171587 ps
T1880 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4249724086 Mar 26 02:44:14 PM PDT 24 Mar 26 02:44:15 PM PDT 24 43575680 ps
T1881 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1041530804 Mar 26 02:43:46 PM PDT 24 Mar 26 02:43:48 PM PDT 24 214549482 ps
T1882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2609471337 Mar 26 02:43:54 PM PDT 24 Mar 26 02:43:56 PM PDT 24 676921957 ps
T1883 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3756341165 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:42 PM PDT 24 125862698 ps
T1884 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3079397392 Mar 26 02:43:23 PM PDT 24 Mar 26 02:43:24 PM PDT 24 19188774 ps
T1885 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1549869567 Mar 26 02:51:14 PM PDT 24 Mar 26 02:51:17 PM PDT 24 99840020 ps
T1886 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.724052157 Mar 26 02:43:41 PM PDT 24 Mar 26 02:44:04 PM PDT 24 2685123743 ps
T1887 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3885147770 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:09 PM PDT 24 105236073 ps
T1888 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1104326828 Mar 26 02:52:00 PM PDT 24 Mar 26 02:52:01 PM PDT 24 18692026 ps
T1889 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2517360137 Mar 26 02:51:46 PM PDT 24 Mar 26 02:51:59 PM PDT 24 4688150014 ps
T1890 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3524955937 Mar 26 02:43:35 PM PDT 24 Mar 26 02:43:38 PM PDT 24 106803991 ps
T1891 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3318964022 Mar 26 02:43:51 PM PDT 24 Mar 26 02:43:55 PM PDT 24 262637153 ps
T156 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2917317854 Mar 26 02:44:10 PM PDT 24 Mar 26 02:44:13 PM PDT 24 262950003 ps
T1892 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.191446505 Mar 26 02:52:13 PM PDT 24 Mar 26 02:52:15 PM PDT 24 248769382 ps
T1893 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1297228178 Mar 26 02:51:59 PM PDT 24 Mar 26 02:52:00 PM PDT 24 22504212 ps
T1894 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.138145748 Mar 26 02:51:49 PM PDT 24 Mar 26 02:51:50 PM PDT 24 16916178 ps
T1895 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1635548795 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:09 PM PDT 24 47585886 ps
T1896 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2920196026 Mar 26 02:52:06 PM PDT 24 Mar 26 02:52:07 PM PDT 24 66746297 ps
T1897 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2084039173 Mar 26 02:43:57 PM PDT 24 Mar 26 02:43:59 PM PDT 24 270810206 ps
T1898 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2620639881 Mar 26 02:44:09 PM PDT 24 Mar 26 02:44:10 PM PDT 24 36932203 ps
T1899 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2626910232 Mar 26 02:52:14 PM PDT 24 Mar 26 02:52:16 PM PDT 24 14898865 ps
T1900 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.599213941 Mar 26 02:43:23 PM PDT 24 Mar 26 02:43:25 PM PDT 24 44996993 ps
T1901 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.536112844 Mar 26 02:51:53 PM PDT 24 Mar 26 02:51:54 PM PDT 24 20452138 ps
T1902 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3295277735 Mar 26 02:43:38 PM PDT 24 Mar 26 02:43:42 PM PDT 24 88375543 ps
T1903 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1743251649 Mar 26 02:44:10 PM PDT 24 Mar 26 02:44:13 PM PDT 24 65477378 ps
T1904 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.945228988 Mar 26 02:43:47 PM PDT 24 Mar 26 02:43:48 PM PDT 24 62354557 ps
T1905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3272470794 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:43 PM PDT 24 255506168 ps
T1906 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2166187178 Mar 26 02:51:31 PM PDT 24 Mar 26 02:51:33 PM PDT 24 20052977 ps
T166 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4189119057 Mar 26 02:43:48 PM PDT 24 Mar 26 02:43:50 PM PDT 24 265818689 ps
T1907 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1733589960 Mar 26 02:43:36 PM PDT 24 Mar 26 02:43:46 PM PDT 24 6457083072 ps
T1908 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.741031729 Mar 26 02:51:53 PM PDT 24 Mar 26 02:51:55 PM PDT 24 17033750 ps
T1909 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3075417106 Mar 26 02:44:14 PM PDT 24 Mar 26 02:44:17 PM PDT 24 49522924 ps
T1910 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1401225670 Mar 26 02:44:04 PM PDT 24 Mar 26 02:44:05 PM PDT 24 35868943 ps
T1911 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1106675646 Mar 26 02:44:08 PM PDT 24 Mar 26 02:44:10 PM PDT 24 302281784 ps
T1912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.337859441 Mar 26 02:43:19 PM PDT 24 Mar 26 02:43:20 PM PDT 24 190634620 ps
T1913 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4150625612 Mar 26 02:43:39 PM PDT 24 Mar 26 02:43:42 PM PDT 24 460293641 ps
T1914 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2663512049 Mar 26 02:51:47 PM PDT 24 Mar 26 02:52:05 PM PDT 24 786120113 ps
T1915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3926295966 Mar 26 02:43:56 PM PDT 24 Mar 26 02:43:59 PM PDT 24 147162684 ps
T1916 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3669058616 Mar 26 02:43:35 PM PDT 24 Mar 26 02:43:37 PM PDT 24 952854231 ps
T1917 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2854089862 Mar 26 02:52:01 PM PDT 24 Mar 26 02:52:05 PM PDT 24 460294611 ps
T1918 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4273114381 Mar 26 02:51:15 PM PDT 24 Mar 26 02:51:17 PM PDT 24 31786460 ps
T1919 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2705051069 Mar 26 02:43:40 PM PDT 24 Mar 26 02:43:41 PM PDT 24 17537294 ps
T1920 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3651979677 Mar 26 02:43:20 PM PDT 24 Mar 26 02:43:29 PM PDT 24 744513038 ps
T1921 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3015833957 Mar 26 02:51:52 PM PDT 24 Mar 26 02:51:53 PM PDT 24 581733531 ps
T1922 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.942686024 Mar 26 02:44:14 PM PDT 24 Mar 26 02:44:16 PM PDT 24 23105750 ps
T1923 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.870786306 Mar 26 02:52:09 PM PDT 24 Mar 26 02:52:10 PM PDT 24 17485123 ps
T1924 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3394822997 Mar 26 02:43:58 PM PDT 24 Mar 26 02:43:59 PM PDT 24 17551632 ps
T146 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4228772207 Mar 26 02:51:54 PM PDT 24 Mar 26 02:51:56 PM PDT 24 43410343 ps
T1925 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3210793753 Mar 26 02:43:26 PM PDT 24 Mar 26 02:43:27 PM PDT 24 21816671 ps
T1926 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1688846242 Mar 26 02:52:08 PM PDT 24 Mar 26 02:52:10 PM PDT 24 135574686 ps
T1927 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4019626552 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:23 PM PDT 24 32097075 ps
T1928 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3271295788 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:22 PM PDT 24 33509249 ps
T171 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.755748808 Mar 26 02:52:05 PM PDT 24 Mar 26 02:52:08 PM PDT 24 78445663 ps
T1929 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.525932397 Mar 26 02:43:52 PM PDT 24 Mar 26 02:43:53 PM PDT 24 45881145 ps
T1930 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4267110444 Mar 26 02:43:37 PM PDT 24 Mar 26 02:43:39 PM PDT 24 35648465 ps
T1931 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3407830254 Mar 26 02:51:14 PM PDT 24 Mar 26 02:51:19 PM PDT 24 1773101548 ps
T1932 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.344052452 Mar 26 02:51:50 PM PDT 24 Mar 26 02:51:51 PM PDT 24 144868537 ps
T1933 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3028509791 Mar 26 02:43:47 PM PDT 24 Mar 26 02:44:04 PM PDT 24 7467047760 ps
T1934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.667078742 Mar 26 02:51:43 PM PDT 24 Mar 26 02:51:45 PM PDT 24 101425054 ps
T1935 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2465014475 Mar 26 02:52:03 PM PDT 24 Mar 26 02:52:04 PM PDT 24 87742095 ps
T1936 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.710576055 Mar 26 02:51:17 PM PDT 24 Mar 26 02:51:18 PM PDT 24 20332104 ps
T235 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2084425892 Mar 26 02:51:27 PM PDT 24 Mar 26 02:51:28 PM PDT 24 148506599 ps
T152 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3780440301 Mar 26 02:44:07 PM PDT 24 Mar 26 02:44:10 PM PDT 24 72708485 ps
T1937 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1150978016 Mar 26 02:52:05 PM PDT 24 Mar 26 02:52:06 PM PDT 24 39756161 ps
T1938 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1015284648 Mar 26 02:51:31 PM PDT 24 Mar 26 02:51:32 PM PDT 24 15077564 ps
T1939 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4054578619 Mar 26 02:51:20 PM PDT 24 Mar 26 02:51:27 PM PDT 24 167449274 ps
T1940 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.441373727 Mar 26 02:51:15 PM PDT 24 Mar 26 02:51:17 PM PDT 24 64507068 ps
T1941 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2500108720 Mar 26 02:51:52 PM PDT 24 Mar 26 02:51:54 PM PDT 24 230211639 ps
T1942 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.748968321 Mar 26 02:51:17 PM PDT 24 Mar 26 02:51:19 PM PDT 24 96898025 ps
T1943 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3573749756 Mar 26 02:51:19 PM PDT 24 Mar 26 02:51:29 PM PDT 24 359434580 ps
T1944 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.357300205 Mar 26 02:51:15 PM PDT 24 Mar 26 02:51:21 PM PDT 24 844193122 ps
T1945 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4216333804 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:42 PM PDT 24 13283866 ps
T1946 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.343435413 Mar 26 02:44:04 PM PDT 24 Mar 26 02:44:06 PM PDT 24 24462487 ps
T1947 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.434750322 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:29 PM PDT 24 296792956 ps
T1948 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2620566368 Mar 26 02:44:05 PM PDT 24 Mar 26 02:44:08 PM PDT 24 160552172 ps
T1949 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1539302457 Mar 26 02:51:23 PM PDT 24 Mar 26 02:51:33 PM PDT 24 1722513688 ps
T1950 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.80701539 Mar 26 02:52:06 PM PDT 24 Mar 26 02:52:07 PM PDT 24 24489088 ps
T1951 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3872108913 Mar 26 02:51:51 PM PDT 24 Mar 26 02:51:52 PM PDT 24 18846963 ps
T1952 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2263210988 Mar 26 02:51:22 PM PDT 24 Mar 26 02:51:51 PM PDT 24 5065567745 ps
T1953 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.415697780 Mar 26 02:43:48 PM PDT 24 Mar 26 02:43:49 PM PDT 24 38710519 ps
T1954 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4073178338 Mar 26 02:43:25 PM PDT 24 Mar 26 02:43:26 PM PDT 24 48344769 ps
T1955 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2086087694 Mar 26 02:52:09 PM PDT 24 Mar 26 02:52:11 PM PDT 24 42373492 ps
T1956 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3651243814 Mar 26 02:44:09 PM PDT 24 Mar 26 02:44:12 PM PDT 24 79100256 ps
T1957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2067450950 Mar 26 02:51:46 PM PDT 24 Mar 26 02:51:48 PM PDT 24 75844113 ps
T1958 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.888082646 Mar 26 02:51:32 PM PDT 24 Mar 26 02:51:34 PM PDT 24 32730310 ps
T1959 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1744704555 Mar 26 02:43:59 PM PDT 24 Mar 26 02:44:01 PM PDT 24 428002466 ps
T1960 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2779737174 Mar 26 02:43:48 PM PDT 24 Mar 26 02:43:51 PM PDT 24 154685600 ps
T1961 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3087987716 Mar 26 02:43:37 PM PDT 24 Mar 26 02:43:38 PM PDT 24 39117627 ps
T1962 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3740845177 Mar 26 02:44:05 PM PDT 24 Mar 26 02:44:11 PM PDT 24 1189716809 ps
T1963 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1839356590 Mar 26 02:51:22 PM PDT 24 Mar 26 02:51:25 PM PDT 24 59851388 ps
T1964 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2156396614 Mar 26 02:51:20 PM PDT 24 Mar 26 02:51:23 PM PDT 24 245380189 ps
T1965 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1204600918 Mar 26 02:43:55 PM PDT 24 Mar 26 02:43:57 PM PDT 24 33856919 ps
T165 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2189315686 Mar 26 02:51:55 PM PDT 24 Mar 26 02:51:58 PM PDT 24 382434811 ps
T1966 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3030899573 Mar 26 02:51:44 PM PDT 24 Mar 26 02:51:46 PM PDT 24 23722364 ps
T1967 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3385351480 Mar 26 02:43:33 PM PDT 24 Mar 26 02:43:36 PM PDT 24 477558769 ps
T1968 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1635234679 Mar 26 02:44:09 PM PDT 24 Mar 26 02:44:16 PM PDT 24 60046781 ps
T1969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.274416491 Mar 26 02:51:20 PM PDT 24 Mar 26 02:51:22 PM PDT 24 328807770 ps
T1970 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2612160826 Mar 26 02:43:56 PM PDT 24 Mar 26 02:44:14 PM PDT 24 676106764 ps
T1971 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3687878899 Mar 26 02:51:14 PM PDT 24 Mar 26 02:51:20 PM PDT 24 218252740 ps
T1972 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2667204422 Mar 26 02:51:51 PM PDT 24 Mar 26 02:51:53 PM PDT 24 143391949 ps
T1973 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2351474556 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:08 PM PDT 24 19720954 ps
T1974 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3080138198 Mar 26 02:52:06 PM PDT 24 Mar 26 02:52:09 PM PDT 24 50508582 ps
T1975 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1921627649 Mar 26 02:51:53 PM PDT 24 Mar 26 02:51:55 PM PDT 24 29226046 ps
T147 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3692213912 Mar 26 02:51:20 PM PDT 24 Mar 26 02:51:22 PM PDT 24 45741375 ps
T1976 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1634938860 Mar 26 02:43:49 PM PDT 24 Mar 26 02:43:50 PM PDT 24 52128831 ps
T1977 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.969823573 Mar 26 02:43:50 PM PDT 24 Mar 26 02:43:53 PM PDT 24 93613652 ps
T1978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.97646301 Mar 26 02:43:59 PM PDT 24 Mar 26 02:44:01 PM PDT 24 45973567 ps
T1979 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2050864649 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:43 PM PDT 24 55749441 ps
T1980 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2077303329 Mar 26 02:51:15 PM PDT 24 Mar 26 02:51:17 PM PDT 24 47337825 ps
T1981 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2324603797 Mar 26 02:52:07 PM PDT 24 Mar 26 02:52:08 PM PDT 24 35645148 ps
T1982 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2130237046 Mar 26 02:52:10 PM PDT 24 Mar 26 02:52:11 PM PDT 24 32240572 ps
T1983 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1924149792 Mar 26 02:43:25 PM PDT 24 Mar 26 02:43:28 PM PDT 24 466601364 ps
T1984 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.737418443 Mar 26 02:43:48 PM PDT 24 Mar 26 02:43:49 PM PDT 24 46676097 ps
T1985 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2118545560 Mar 26 02:44:09 PM PDT 24 Mar 26 02:44:10 PM PDT 24 43637299 ps
T1986 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.529446639 Mar 26 02:51:10 PM PDT 24 Mar 26 02:51:11 PM PDT 24 55719659 ps
T1987 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3986426759 Mar 26 02:44:07 PM PDT 24 Mar 26 02:44:22 PM PDT 24 644446727 ps
T1988 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3399204631 Mar 26 02:43:23 PM PDT 24 Mar 26 02:43:30 PM PDT 24 323860220 ps
T1989 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2736381323 Mar 26 02:52:13 PM PDT 24 Mar 26 02:52:15 PM PDT 24 92524745 ps
T1990 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1371745055 Mar 26 02:43:41 PM PDT 24 Mar 26 02:43:43 PM PDT 24 179300527 ps
T1991 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3305145530 Mar 26 02:44:11 PM PDT 24 Mar 26 02:44:12 PM PDT 24 44272683 ps
T1992 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1438514906 Mar 26 02:43:56 PM PDT 24 Mar 26 02:43:58 PM PDT 24 38807558 ps
T144 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2037679802 Mar 26 02:51:31 PM PDT 24 Mar 26 02:51:34 PM PDT 24 130604440 ps
T1993 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1174230434 Mar 26 02:51:52 PM PDT 24 Mar 26 02:51:54 PM PDT 24 287815970 ps
T1994 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2359972837 Mar 26 02:52:08 PM PDT 24 Mar 26 02:52:11 PM PDT 24 373137850 ps
T1995 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1426939021 Mar 26 02:51:14 PM PDT 24 Mar 26 02:51:18 PM PDT 24 425409254 ps
T1996 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1503072990 Mar 26 02:51:19 PM PDT 24 Mar 26 02:51:37 PM PDT 24 5804000581 ps
T1997 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1472361275 Mar 26 02:51:37 PM PDT 24 Mar 26 02:51:38 PM PDT 24 76146068 ps
T1998 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2059779741 Mar 26 02:43:39 PM PDT 24 Mar 26 02:43:41 PM PDT 24 44697272 ps
T1999 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4115965877 Mar 26 02:51:54 PM PDT 24 Mar 26 02:51:55 PM PDT 24 15755089 ps
T2000 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1398131124 Mar 26 02:44:06 PM PDT 24 Mar 26 02:44:07 PM PDT 24 13364201 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%