Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84794991

1

T1

9524

T2

158393

T3

152337

auto[1]

1262410

1

T1

198

T2

198

T3

693

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84808385

1

T1

9524

T2

157799

T3

151941

auto[1]

1249016

1

T1

198

T2

792

T3

1089

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6269030	1			T1	1671		T2	9261		T3	8806
auto[IdleSt]	22443097	1			T1	2068		T2	76315		T3	64271
auto[ClkMuxSt]	32398	1			T1	5		T2	96		T3	94
auto[CntIncrSt]	32053	1			T1	5		T2	96		T3	94
auto[CntProgSt]	1059857	1			T1	1316		T2	1366		T3	14994
auto[TransCheckSt]	24867	1			T1	5		T2	74		T3	62
auto[TokenHashSt]	29876778	1			T1	109		T2	700		T3	2029
auto[FlashRmaSt]	24808	1			T1	5		T2	86		T3	56
auto[TokenCheck0St]	11355	1			T1	5		T2	28		T3	18
auto[TokenCheck1St]	8309	1			T1	5		T2	12		T3	9
auto[TransProgSt]	271159	1			T1	994		T2	275		T3	2481
auto[PostTransSt]	11360394	1			T1	1585		T2	66637		T3	54284
auto[ScrapSt]	141542	1			T8	10		T4	612		T14	48
auto[EscalateSt]	5693514	1			T1	1219		T2	3645		T3	5832
auto[InvalidSt]	8806624	1			T1	729		T8	4922		T4	492245

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1616	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8806624	1			T1	729		T8	4922		T4	492245
EscalateSt	5693514	1			T1	1219		T2	3645		T3	5832
ScrapSt	141542	1			T8	10		T4	612		T14	48
PostTransSt	11360394	1			T1	1585		T2	66637		T3	54284
TransProgSt	271159	1			T1	994		T2	275		T3	2481
TokenCheck1St	8309	1			T1	5		T2	12		T3	9
TokenCheck0St	11355	1			T1	5		T2	28		T3	18
FlashRmaSt	24808	1			T1	5		T2	86		T3	56
TokenHashSt	29876778	1			T1	109		T2	700		T3	2029
TransCheckSt	24867	1			T1	5		T2	74		T3	62
CntProgSt	1059857	1			T1	1316		T2	1366		T3	14994
CntIncrSt	32053	1			T1	5		T2	96		T3	94
ClkMuxSt	32398	1			T1	5		T2	96		T3	94
IdleSt	22443097	1			T1	2068		T2	76315		T3	64271
ResetSt	6269030	1			T1	1671		T2	9261		T3	8806
arcs[ResetSt=>IdleSt]	48226	1			T1	12		T2	100		T3	95
arcs[IdleSt=>ScrapSt]	274	1			T8	4		T4	1		T14	1
arcs[IdleSt=>ClkMuxSt]	32131	1			T1	5		T2	96		T3	94
arcs[ClkMuxSt=>CntIncrSt]	32053	1			T1	5		T2	96		T3	94
arcs[CntIncrSt=>PostTransSt]	1400	1			T2	12		T3	14		T4	25
arcs[CntIncrSt=>CntProgSt]	30597	1			T1	5		T2	84		T3	80
arcs[CntProgSt=>PostTransSt]	4464	1			T2	10		T3	18		T4	64
arcs[CntProgSt=>TransCheckSt]	24867	1			T1	5		T2	74		T3	62
arcs[TransCheckSt=>PostTransSt]	3498	1			T2	11		T3	10		T4	30
arcs[TransCheckSt=>TokenHashSt]	21282	1			T1	5		T2	63		T3	52
arcs[TokenHashSt=>PostTransSt]	9212	1			T2	35		T3	34		T4	86
arcs[TokenHashSt=>FlashRmaSt]	11464	1			T1	5		T2	28		T3	18
arcs[FlashRmaSt=>TokenCheck0St]	11355	1			T1	5		T2	28		T3	18
arcs[TokenCheck0St=>PostTransSt]	3020	1			T2	16		T3	9		T4	28
arcs[TokenCheck0St=>TokenCheck1St]	8309	1			T1	5		T2	12		T3	9
arcs[TokenCheck1St=>PostTransSt]	626	1			T4	1		T11	12		T15	2
arcs[TransProgSt=>PostTransSt]	6743	1			T1	5		T2	12		T3	9
arcs[IdleSt=>EscalateSt]	175	1			T30	5		T53	5		T54	6
arcs[ClkMuxSt=>EscalateSt]	78	1			T30	1		T36	1		T52	2
arcs[CntIncrSt=>EscalateSt]	56	1			T30	1		T36	1		T52	1
arcs[CntProgSt=>EscalateSt]	1266	1			T30	21		T36	6		T52	35
arcs[TransCheckSt=>EscalateSt]	87	1			T36	8		T57	10		T54	1
arcs[TokenHashSt=>EscalateSt]	606	1			T15	1		T44	1		T30	5
arcs[FlashRmaSt=>EscalateSt]	109	1			T30	2		T36	2		T52	2
arcs[TokenCheck0St=>EscalateSt]	26	1			T52	1		T53	1		T57	1
arcs[TokenCheck1St=>EscalateSt]	147	1			T36	5		T52	2		T53	5
arcs[TransProgSt=>EscalateSt]	793	1			T30	11		T36	9		T52	10
arcs[PostTransSt=>EscalateSt]	4654	1			T2	10		T3	18		T4	64
arcs[InvalidSt=>EscalateSt]	11345	1			T1	4		T4	253		T13	54

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6268848	1			T1	1671		T2	9261		T3	8806
auto[0]	auto[IdleSt]	22442980	1			T1	2068		T2	76315		T3	64271
auto[0]	auto[ClkMuxSt]	32347	1			T1	5		T2	96		T3	94
auto[0]	auto[CntIncrSt]	32017	1			T1	5		T2	96		T3	94
auto[0]	auto[CntProgSt]	1058976	1			T1	1316		T2	1366		T3	14994
auto[0]	auto[TransCheckSt]	24811	1			T1	5		T2	74		T3	62
auto[0]	auto[TokenHashSt]	29876365	1			T1	109		T2	700		T3	2029
auto[0]	auto[FlashRmaSt]	24743	1			T1	5		T2	86		T3	56
auto[0]	auto[TokenCheck0St]	11340	1			T1	5		T2	28		T3	18
auto[0]	auto[TokenCheck1St]	8206	1			T1	5		T2	12		T3	9
auto[0]	auto[TransProgSt]	270633	1			T1	994		T2	275		T3	2481
auto[0]	auto[PostTransSt]	11358027	1			T1	1585		T2	66635		T3	54277
auto[0]	auto[ScrapSt]	141498	1			T8	10		T4	612		T14	48
auto[0]	auto[EscalateSt]	4441644	1			T1	1023		T2	3449		T3	5146
auto[0]	auto[InvalidSt]	8800940	1			T1	727		T8	4922		T4	492122
auto[1]	auto[ResetSt]	182	1			T30	3		T36	4		T52	5
auto[1]	auto[IdleSt]	117	1			T30	4		T53	5		T54	4
auto[1]	auto[ClkMuxSt]	51	1			T30	1		T36	1		T52	2
auto[1]	auto[CntIncrSt]	36	1			T30	1		T36	1		T52	1
auto[1]	auto[CntProgSt]	881	1			T30	12		T36	6		T52	28
auto[1]	auto[TransCheckSt]	56	1			T36	6		T57	6		T54	1
auto[1]	auto[TokenHashSt]	413	1			T30	2		T36	21		T52	6
auto[1]	auto[FlashRmaSt]	65	1			T30	1		T36	2		T52	2
auto[1]	auto[TokenCheck0St]	15	1			T52	1		T218	1		T54	1
auto[1]	auto[TokenCheck1St]	103	1			T36	4		T52	2		T53	4
auto[1]	auto[TransProgSt]	526	1			T30	7		T36	3		T52	8
auto[1]	auto[PostTransSt]	2367	1			T2	2		T3	7		T4	32
auto[1]	auto[ScrapSt]	44	1			T36	1		T52	1		T218	1
auto[1]	auto[EscalateSt]	1251870	1			T1	196		T2	196		T3	686
auto[1]	auto[InvalidSt]	5684	1			T1	2		T4	123		T13	30

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6268837	1			T1	1671		T2	9261		T3	8806
auto[0]	auto[IdleSt]	22442981	1			T1	2068		T2	76315		T3	64271
auto[0]	auto[ClkMuxSt]	32353	1			T1	5		T2	96		T3	94
auto[0]	auto[CntIncrSt]	32013	1			T1	5		T2	96		T3	94
auto[0]	auto[CntProgSt]	1059038	1			T1	1316		T2	1366		T3	14994
auto[0]	auto[TransCheckSt]	24809	1			T1	5		T2	74		T3	62
auto[0]	auto[TokenHashSt]	29876383	1			T1	109		T2	700		T3	2029
auto[0]	auto[FlashRmaSt]	24726	1			T1	5		T2	86		T3	56
auto[0]	auto[TokenCheck0St]	11337	1			T1	5		T2	28		T3	18
auto[0]	auto[TokenCheck1St]	8213	1			T1	5		T2	12		T3	9
auto[0]	auto[TransProgSt]	270624	1			T1	994		T2	275		T3	2481
auto[0]	auto[PostTransSt]	11358062	1			T1	1585		T2	66629		T3	54273
auto[0]	auto[ScrapSt]	141492	1			T8	10		T4	612		T14	48
auto[0]	auto[EscalateSt]	4454938	1			T1	1023		T2	2861		T3	4754
auto[0]	auto[InvalidSt]	8800963	1			T1	727		T8	4922		T4	492115
auto[1]	auto[ResetSt]	193	1			T30	4		T36	6		T52	6
auto[1]	auto[IdleSt]	116	1			T30	2		T53	4		T54	4
auto[1]	auto[ClkMuxSt]	45	1			T30	1		T52	1		T53	2
auto[1]	auto[CntIncrSt]	40	1			T30	1		T52	1		T218	1
auto[1]	auto[CntProgSt]	819	1			T30	12		T36	2		T52	22
auto[1]	auto[TransCheckSt]	58	1			T36	6		T57	8		T54	1
auto[1]	auto[TokenHashSt]	395	1			T15	1		T44	1		T30	4
auto[1]	auto[FlashRmaSt]	82	1			T30	2		T36	2		T52	2
auto[1]	auto[TokenCheck0St]	18	1			T53	1		T57	1		T218	1
auto[1]	auto[TokenCheck1St]	96	1			T36	2		T52	2		T53	2
auto[1]	auto[TransProgSt]	535	1			T30	6		T36	8		T52	6
auto[1]	auto[PostTransSt]	2332	1			T2	8		T3	11		T4	32
auto[1]	auto[ScrapSt]	50	1			T36	2		T53	1		T57	1
auto[1]	auto[EscalateSt]	1238576	1			T1	196		T2	784		T3	1078
auto[1]	auto[InvalidSt]	5661	1			T1	2		T4	130		T13	24