| T830 |
/workspace/coverage/default/33.lc_ctrl_sec_mubi.2685937763 |
|
|
Mar 28 01:41:09 PM PDT 24 |
Mar 28 01:41:26 PM PDT 24 |
1382576653 ps |
| T831 |
/workspace/coverage/default/1.lc_ctrl_jtag_priority.1578154889 |
|
|
Mar 28 01:38:54 PM PDT 24 |
Mar 28 01:39:06 PM PDT 24 |
3562998802 ps |
| T832 |
/workspace/coverage/default/0.lc_ctrl_state_failure.365254538 |
|
|
Mar 28 01:38:54 PM PDT 24 |
Mar 28 01:39:10 PM PDT 24 |
733611456 ps |
| T833 |
/workspace/coverage/default/5.lc_ctrl_state_post_trans.1958071619 |
|
|
Mar 28 01:39:08 PM PDT 24 |
Mar 28 01:39:15 PM PDT 24 |
78990519 ps |
| T834 |
/workspace/coverage/default/31.lc_ctrl_jtag_access.367171137 |
|
|
Mar 28 01:41:03 PM PDT 24 |
Mar 28 01:41:06 PM PDT 24 |
192349592 ps |
| T835 |
/workspace/coverage/default/30.lc_ctrl_smoke.56520972 |
|
|
Mar 28 01:40:41 PM PDT 24 |
Mar 28 01:40:44 PM PDT 24 |
165536193 ps |
| T836 |
/workspace/coverage/default/2.lc_ctrl_alert_test.1848353390 |
|
|
Mar 28 01:39:02 PM PDT 24 |
Mar 28 01:39:04 PM PDT 24 |
29385152 ps |
| T837 |
/workspace/coverage/default/23.lc_ctrl_alert_test.2699743454 |
|
|
Mar 28 01:40:20 PM PDT 24 |
Mar 28 01:40:21 PM PDT 24 |
35118699 ps |
| T838 |
/workspace/coverage/default/0.lc_ctrl_jtag_errors.2270815393 |
|
|
Mar 28 01:38:49 PM PDT 24 |
Mar 28 01:40:22 PM PDT 24 |
3463111191 ps |
| T839 |
/workspace/coverage/default/47.lc_ctrl_state_failure.1802621471 |
|
|
Mar 28 01:41:40 PM PDT 24 |
Mar 28 01:42:07 PM PDT 24 |
274401645 ps |
| T840 |
/workspace/coverage/default/49.lc_ctrl_stress_all.3577866637 |
|
|
Mar 28 01:41:40 PM PDT 24 |
Mar 28 01:44:35 PM PDT 24 |
4761168117 ps |
| T841 |
/workspace/coverage/default/16.lc_ctrl_errors.3173109715 |
|
|
Mar 28 01:40:15 PM PDT 24 |
Mar 28 01:40:24 PM PDT 24 |
227730000 ps |
| T842 |
/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.440091185 |
|
|
Mar 28 01:40:26 PM PDT 24 |
Mar 28 01:40:27 PM PDT 24 |
39334068 ps |
| T843 |
/workspace/coverage/default/1.lc_ctrl_jtag_smoke.2764753781 |
|
|
Mar 28 01:38:52 PM PDT 24 |
Mar 28 01:39:04 PM PDT 24 |
438419907 ps |
| T844 |
/workspace/coverage/default/16.lc_ctrl_sec_token_mux.1794528115 |
|
|
Mar 28 01:40:10 PM PDT 24 |
Mar 28 01:40:17 PM PDT 24 |
748436665 ps |
| T845 |
/workspace/coverage/default/25.lc_ctrl_security_escalation.1203575606 |
|
|
Mar 28 01:40:21 PM PDT 24 |
Mar 28 01:40:32 PM PDT 24 |
242601786 ps |
| T846 |
/workspace/coverage/default/32.lc_ctrl_sec_token_digest.3951151672 |
|
|
Mar 28 01:41:07 PM PDT 24 |
Mar 28 01:41:18 PM PDT 24 |
392188186 ps |
| T159 |
/workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.763246728 |
|
|
Mar 28 01:40:05 PM PDT 24 |
Mar 28 01:50:06 PM PDT 24 |
128929024042 ps |
| T847 |
/workspace/coverage/default/2.lc_ctrl_state_post_trans.2907571921 |
|
|
Mar 28 01:38:56 PM PDT 24 |
Mar 28 01:39:03 PM PDT 24 |
200946979 ps |
| T848 |
/workspace/coverage/default/25.lc_ctrl_alert_test.2352794291 |
|
|
Mar 28 01:40:40 PM PDT 24 |
Mar 28 01:40:41 PM PDT 24 |
67010453 ps |
| T849 |
/workspace/coverage/default/44.lc_ctrl_security_escalation.3780227185 |
|
|
Mar 28 01:41:21 PM PDT 24 |
Mar 28 01:41:31 PM PDT 24 |
859420603 ps |
| T850 |
/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.683753109 |
|
|
Mar 28 01:41:08 PM PDT 24 |
Mar 28 01:41:09 PM PDT 24 |
19211846 ps |
| T851 |
/workspace/coverage/default/37.lc_ctrl_errors.905802576 |
|
|
Mar 28 01:41:24 PM PDT 24 |
Mar 28 01:41:38 PM PDT 24 |
358651111 ps |
| T852 |
/workspace/coverage/default/34.lc_ctrl_errors.2978014912 |
|
|
Mar 28 01:41:01 PM PDT 24 |
Mar 28 01:41:14 PM PDT 24 |
1677869524 ps |
| T853 |
/workspace/coverage/default/39.lc_ctrl_alert_test.3717972591 |
|
|
Mar 28 01:41:23 PM PDT 24 |
Mar 28 01:41:24 PM PDT 24 |
18882865 ps |
| T854 |
/workspace/coverage/default/20.lc_ctrl_sec_token_mux.2858772503 |
|
|
Mar 28 01:40:22 PM PDT 24 |
Mar 28 01:40:30 PM PDT 24 |
547789619 ps |
| T855 |
/workspace/coverage/default/7.lc_ctrl_sec_mubi.953088134 |
|
|
Mar 28 01:39:41 PM PDT 24 |
Mar 28 01:39:52 PM PDT 24 |
1324104725 ps |
| T856 |
/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.998599537 |
|
|
Mar 28 01:40:14 PM PDT 24 |
Mar 28 01:40:15 PM PDT 24 |
14957816 ps |
| T857 |
/workspace/coverage/default/5.lc_ctrl_jtag_priority.2820084978 |
|
|
Mar 28 01:39:08 PM PDT 24 |
Mar 28 01:39:15 PM PDT 24 |
2451182916 ps |
| T858 |
/workspace/coverage/default/22.lc_ctrl_security_escalation.3201899659 |
|
|
Mar 28 01:40:17 PM PDT 24 |
Mar 28 01:40:29 PM PDT 24 |
448001563 ps |
| T859 |
/workspace/coverage/default/13.lc_ctrl_sec_token_digest.3574279691 |
|
|
Mar 28 01:40:09 PM PDT 24 |
Mar 28 01:40:19 PM PDT 24 |
2181777809 ps |
| T214 |
/workspace/coverage/default/4.lc_ctrl_claim_transition_if.202405042 |
|
|
Mar 28 01:39:06 PM PDT 24 |
Mar 28 01:39:07 PM PDT 24 |
11511437 ps |
| T860 |
/workspace/coverage/default/10.lc_ctrl_jtag_smoke.2905148443 |
|
|
Mar 28 01:39:41 PM PDT 24 |
Mar 28 01:39:45 PM PDT 24 |
128847211 ps |
| T861 |
/workspace/coverage/default/29.lc_ctrl_stress_all.412268558 |
|
|
Mar 28 01:40:43 PM PDT 24 |
Mar 28 01:42:30 PM PDT 24 |
25470545585 ps |
| T215 |
/workspace/coverage/default/7.lc_ctrl_claim_transition_if.2343233595 |
|
|
Mar 28 01:39:42 PM PDT 24 |
Mar 28 01:39:44 PM PDT 24 |
41453398 ps |
| T862 |
/workspace/coverage/default/15.lc_ctrl_security_escalation.1713390824 |
|
|
Mar 28 01:40:12 PM PDT 24 |
Mar 28 01:40:18 PM PDT 24 |
199699606 ps |
| T863 |
/workspace/coverage/default/15.lc_ctrl_stress_all.3347994321 |
|
|
Mar 28 01:40:10 PM PDT 24 |
Mar 28 01:41:43 PM PDT 24 |
4197253581 ps |
| T864 |
/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1089356462 |
|
|
Mar 28 01:40:05 PM PDT 24 |
Mar 28 01:40:11 PM PDT 24 |
180658105 ps |
| T865 |
/workspace/coverage/default/8.lc_ctrl_prog_failure.978280006 |
|
|
Mar 28 01:39:43 PM PDT 24 |
Mar 28 01:39:46 PM PDT 24 |
89455731 ps |
| T866 |
/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1336936351 |
|
|
Mar 28 01:39:38 PM PDT 24 |
Mar 28 01:40:13 PM PDT 24 |
6096247709 ps |
| T181 |
/workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4290475805 |
|
|
Mar 28 01:39:01 PM PDT 24 |
Mar 28 01:49:17 PM PDT 24 |
99010459945 ps |
| T867 |
/workspace/coverage/default/38.lc_ctrl_sec_token_digest.511874013 |
|
|
Mar 28 01:41:26 PM PDT 24 |
Mar 28 01:41:36 PM PDT 24 |
431258601 ps |
| T868 |
/workspace/coverage/default/1.lc_ctrl_prog_failure.2101152225 |
|
|
Mar 28 01:38:53 PM PDT 24 |
Mar 28 01:38:56 PM PDT 24 |
44606998 ps |
| T869 |
/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1426893818 |
|
|
Mar 28 01:38:56 PM PDT 24 |
Mar 28 01:39:08 PM PDT 24 |
259266168 ps |
| T870 |
/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.683474556 |
|
|
Mar 28 01:40:28 PM PDT 24 |
Mar 28 01:40:29 PM PDT 24 |
14675002 ps |
| T871 |
/workspace/coverage/default/31.lc_ctrl_state_post_trans.2202793197 |
|
|
Mar 28 01:41:00 PM PDT 24 |
Mar 28 01:41:07 PM PDT 24 |
608041702 ps |
| T872 |
/workspace/coverage/default/7.lc_ctrl_stress_all.1791794654 |
|
|
Mar 28 01:39:43 PM PDT 24 |
Mar 28 01:43:15 PM PDT 24 |
13545096439 ps |
| T873 |
/workspace/coverage/default/34.lc_ctrl_security_escalation.1439751528 |
|
|
Mar 28 01:41:07 PM PDT 24 |
Mar 28 01:41:20 PM PDT 24 |
1639679654 ps |
| T874 |
/workspace/coverage/default/11.lc_ctrl_jtag_access.4145348338 |
|
|
Mar 28 01:40:09 PM PDT 24 |
Mar 28 01:40:12 PM PDT 24 |
110309374 ps |
| T875 |
/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3931592982 |
|
|
Mar 28 01:39:44 PM PDT 24 |
Mar 28 01:41:42 PM PDT 24 |
4330336979 ps |
| T876 |
/workspace/coverage/default/32.lc_ctrl_alert_test.2396540207 |
|
|
Mar 28 01:41:05 PM PDT 24 |
Mar 28 01:41:06 PM PDT 24 |
21243972 ps |
| T877 |
/workspace/coverage/default/47.lc_ctrl_sec_token_digest.2346267140 |
|
|
Mar 28 01:41:43 PM PDT 24 |
Mar 28 01:41:57 PM PDT 24 |
305911101 ps |
| T878 |
/workspace/coverage/default/16.lc_ctrl_security_escalation.2995934836 |
|
|
Mar 28 01:40:14 PM PDT 24 |
Mar 28 01:40:28 PM PDT 24 |
554262128 ps |
| T879 |
/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.327267423 |
|
|
Mar 28 01:41:06 PM PDT 24 |
Mar 28 01:41:07 PM PDT 24 |
56237076 ps |
| T880 |
/workspace/coverage/default/47.lc_ctrl_prog_failure.2519731281 |
|
|
Mar 28 01:41:46 PM PDT 24 |
Mar 28 01:41:49 PM PDT 24 |
104082712 ps |
| T881 |
/workspace/coverage/default/27.lc_ctrl_state_post_trans.3708054576 |
|
|
Mar 28 01:40:42 PM PDT 24 |
Mar 28 01:40:50 PM PDT 24 |
167730741 ps |
| T882 |
/workspace/coverage/default/10.lc_ctrl_alert_test.2740890493 |
|
|
Mar 28 01:40:10 PM PDT 24 |
Mar 28 01:40:12 PM PDT 24 |
241729247 ps |
| T883 |
/workspace/coverage/default/19.lc_ctrl_errors.3654474976 |
|
|
Mar 28 01:40:14 PM PDT 24 |
Mar 28 01:40:25 PM PDT 24 |
1787319030 ps |
| T884 |
/workspace/coverage/default/11.lc_ctrl_sec_mubi.2289103623 |
|
|
Mar 28 01:40:08 PM PDT 24 |
Mar 28 01:40:26 PM PDT 24 |
376233394 ps |
| T885 |
/workspace/coverage/default/8.lc_ctrl_smoke.448153443 |
|
|
Mar 28 01:39:43 PM PDT 24 |
Mar 28 01:39:47 PM PDT 24 |
205835369 ps |
| T886 |
/workspace/coverage/default/14.lc_ctrl_state_failure.4168695301 |
|
|
Mar 28 01:40:11 PM PDT 24 |
Mar 28 01:40:40 PM PDT 24 |
391515898 ps |
| T887 |
/workspace/coverage/default/16.lc_ctrl_prog_failure.2844899210 |
|
|
Mar 28 01:40:14 PM PDT 24 |
Mar 28 01:40:17 PM PDT 24 |
262646891 ps |
| T106 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1334348084 |
|
|
Mar 28 12:45:45 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
915757983 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1842533496 |
|
|
Mar 28 12:34:46 PM PDT 24 |
Mar 28 12:34:53 PM PDT 24 |
355793127 ps |
| T98 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1302419785 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:26 PM PDT 24 |
201127879 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2470321580 |
|
|
Mar 28 12:34:37 PM PDT 24 |
Mar 28 12:34:41 PM PDT 24 |
184843749 ps |
| T95 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1514599107 |
|
|
Mar 28 12:34:44 PM PDT 24 |
Mar 28 12:34:46 PM PDT 24 |
96149005 ps |
| T100 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2880983484 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:53 PM PDT 24 |
609478323 ps |
| T96 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2725075546 |
|
|
Mar 28 12:35:01 PM PDT 24 |
Mar 28 12:35:05 PM PDT 24 |
201422791 ps |
| T212 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2743586742 |
|
|
Mar 28 12:34:29 PM PDT 24 |
Mar 28 12:34:48 PM PDT 24 |
3221340720 ps |
| T142 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2108779719 |
|
|
Mar 28 12:34:38 PM PDT 24 |
Mar 28 12:34:40 PM PDT 24 |
130817838 ps |
| T888 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.44992795 |
|
|
Mar 28 12:45:47 PM PDT 24 |
Mar 28 12:45:49 PM PDT 24 |
200295450 ps |
| T160 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.814999662 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:45 PM PDT 24 |
27584558 ps |
| T149 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2480217776 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:49 PM PDT 24 |
45456040 ps |
| T103 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3258972723 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
20425546 ps |
| T189 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3708366741 |
|
|
Mar 28 12:45:39 PM PDT 24 |
Mar 28 12:45:41 PM PDT 24 |
10953310 ps |
| T161 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2315315399 |
|
|
Mar 28 12:45:13 PM PDT 24 |
Mar 28 12:45:14 PM PDT 24 |
294191223 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1969041609 |
|
|
Mar 28 12:45:47 PM PDT 24 |
Mar 28 12:45:50 PM PDT 24 |
499521644 ps |
| T889 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3027751866 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
2053314067 ps |
| T890 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3832502432 |
|
|
Mar 28 12:45:37 PM PDT 24 |
Mar 28 12:45:39 PM PDT 24 |
41673452 ps |
| T205 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.411908180 |
|
|
Mar 28 12:45:44 PM PDT 24 |
Mar 28 12:45:47 PM PDT 24 |
41509281 ps |
| T140 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.746481765 |
|
|
Mar 28 12:34:23 PM PDT 24 |
Mar 28 12:34:24 PM PDT 24 |
155953177 ps |
| T891 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3355248731 |
|
|
Mar 28 12:34:46 PM PDT 24 |
Mar 28 12:34:54 PM PDT 24 |
1495765783 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3707538591 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:46 PM PDT 24 |
103295625 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.282593084 |
|
|
Mar 28 12:34:25 PM PDT 24 |
Mar 28 12:34:28 PM PDT 24 |
69006854 ps |
| T206 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.917044758 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
35639688 ps |
| T892 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2080055923 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:46 PM PDT 24 |
304237422 ps |
| T150 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.193885785 |
|
|
Mar 28 12:45:45 PM PDT 24 |
Mar 28 12:45:47 PM PDT 24 |
159629792 ps |
| T207 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2449240310 |
|
|
Mar 28 12:45:09 PM PDT 24 |
Mar 28 12:45:10 PM PDT 24 |
130867615 ps |
| T102 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3715481110 |
|
|
Mar 28 12:34:29 PM PDT 24 |
Mar 28 12:34:31 PM PDT 24 |
204304505 ps |
| T125 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.572653918 |
|
|
Mar 28 12:45:40 PM PDT 24 |
Mar 28 12:45:46 PM PDT 24 |
172101124 ps |
| T208 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1160822412 |
|
|
Mar 28 12:34:28 PM PDT 24 |
Mar 28 12:34:29 PM PDT 24 |
42283338 ps |
| T893 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2175724106 |
|
|
Mar 28 12:45:39 PM PDT 24 |
Mar 28 12:45:41 PM PDT 24 |
424275701 ps |
| T894 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1085303509 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
56810823 ps |
| T190 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4245219427 |
|
|
Mar 28 12:34:19 PM PDT 24 |
Mar 28 12:34:20 PM PDT 24 |
46436307 ps |
| T141 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.65206560 |
|
|
Mar 28 12:45:12 PM PDT 24 |
Mar 28 12:45:14 PM PDT 24 |
430583634 ps |
| T895 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.5544483 |
|
|
Mar 28 12:34:26 PM PDT 24 |
Mar 28 12:34:28 PM PDT 24 |
34158163 ps |
| T209 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3934795307 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
18232010 ps |
| T896 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3663206124 |
|
|
Mar 28 12:45:10 PM PDT 24 |
Mar 28 12:45:11 PM PDT 24 |
170469320 ps |
| T897 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3214785742 |
|
|
Mar 28 12:46:13 PM PDT 24 |
Mar 28 12:46:15 PM PDT 24 |
28724687 ps |
| T120 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.802968686 |
|
|
Mar 28 12:34:22 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
301344583 ps |
| T191 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2436855604 |
|
|
Mar 28 12:34:27 PM PDT 24 |
Mar 28 12:34:29 PM PDT 24 |
356678506 ps |
| T110 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1780089432 |
|
|
Mar 28 12:34:27 PM PDT 24 |
Mar 28 12:34:28 PM PDT 24 |
257781304 ps |
| T898 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3548163374 |
|
|
Mar 28 12:34:26 PM PDT 24 |
Mar 28 12:34:28 PM PDT 24 |
140814371 ps |
| T112 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1585098795 |
|
|
Mar 28 12:34:39 PM PDT 24 |
Mar 28 12:34:44 PM PDT 24 |
106241121 ps |
| T899 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1114724817 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:48 PM PDT 24 |
79310803 ps |
| T117 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1682625901 |
|
|
Mar 28 12:34:46 PM PDT 24 |
Mar 28 12:34:51 PM PDT 24 |
92178175 ps |
| T900 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1896866337 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:26 PM PDT 24 |
51082593 ps |
| T901 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2156230684 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:54 PM PDT 24 |
217042240 ps |
| T210 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1481073791 |
|
|
Mar 28 12:34:22 PM PDT 24 |
Mar 28 12:34:23 PM PDT 24 |
24778170 ps |
| T902 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2867065979 |
|
|
Mar 28 12:45:40 PM PDT 24 |
Mar 28 12:45:42 PM PDT 24 |
195186473 ps |
| T903 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.880791294 |
|
|
Mar 28 12:45:53 PM PDT 24 |
Mar 28 12:45:55 PM PDT 24 |
273263870 ps |
| T127 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3294387510 |
|
|
Mar 28 12:34:20 PM PDT 24 |
Mar 28 12:34:24 PM PDT 24 |
99620852 ps |
| T904 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3335410415 |
|
|
Mar 28 12:45:41 PM PDT 24 |
Mar 28 12:45:42 PM PDT 24 |
14699115 ps |
| T111 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3039019165 |
|
|
Mar 28 12:34:29 PM PDT 24 |
Mar 28 12:34:31 PM PDT 24 |
198703480 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.302634552 |
|
|
Mar 28 12:34:31 PM PDT 24 |
Mar 28 12:34:34 PM PDT 24 |
371725842 ps |
| T905 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2365580390 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:49 PM PDT 24 |
543788625 ps |
| T126 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2700972194 |
|
|
Mar 28 12:34:30 PM PDT 24 |
Mar 28 12:34:34 PM PDT 24 |
388064733 ps |
| T906 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3201857315 |
|
|
Mar 28 12:34:27 PM PDT 24 |
Mar 28 12:34:30 PM PDT 24 |
119819180 ps |
| T907 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2135941596 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
332695015 ps |
| T908 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1892091759 |
|
|
Mar 28 12:34:30 PM PDT 24 |
Mar 28 12:34:31 PM PDT 24 |
55224497 ps |
| T909 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3021328476 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:35 PM PDT 24 |
1274239968 ps |
| T910 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3180064490 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:26 PM PDT 24 |
191036241 ps |
| T911 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1750674484 |
|
|
Mar 28 12:34:26 PM PDT 24 |
Mar 28 12:34:28 PM PDT 24 |
102584048 ps |
| T912 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2493038258 |
|
|
Mar 28 12:45:10 PM PDT 24 |
Mar 28 12:45:12 PM PDT 24 |
27569147 ps |
| T913 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1139952956 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:49 PM PDT 24 |
83670425 ps |
| T108 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3985801700 |
|
|
Mar 28 12:34:50 PM PDT 24 |
Mar 28 12:34:53 PM PDT 24 |
44055623 ps |
| T914 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.374238472 |
|
|
Mar 28 12:45:42 PM PDT 24 |
Mar 28 12:45:44 PM PDT 24 |
82800701 ps |
| T915 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2351101368 |
|
|
Mar 28 12:45:41 PM PDT 24 |
Mar 28 12:45:42 PM PDT 24 |
26419105 ps |
| T916 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.865941156 |
|
|
Mar 28 12:45:41 PM PDT 24 |
Mar 28 12:45:44 PM PDT 24 |
59452118 ps |
| T917 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.658491486 |
|
|
Mar 28 12:34:34 PM PDT 24 |
Mar 28 12:34:35 PM PDT 24 |
24317862 ps |
| T918 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2442921384 |
|
|
Mar 28 12:34:49 PM PDT 24 |
Mar 28 12:34:51 PM PDT 24 |
2096766420 ps |
| T919 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3138000886 |
|
|
Mar 28 12:34:53 PM PDT 24 |
Mar 28 12:34:54 PM PDT 24 |
122005380 ps |
| T920 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4002610850 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:47 PM PDT 24 |
92820642 ps |
| T921 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1032052981 |
|
|
Mar 28 12:45:38 PM PDT 24 |
Mar 28 12:45:40 PM PDT 24 |
219400132 ps |
| T922 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3027187800 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:45 PM PDT 24 |
25111786 ps |
| T923 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.954286129 |
|
|
Mar 28 12:34:28 PM PDT 24 |
Mar 28 12:34:30 PM PDT 24 |
59523240 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.776936791 |
|
|
Mar 28 12:34:27 PM PDT 24 |
Mar 28 12:34:31 PM PDT 24 |
66674228 ps |
| T924 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1413031432 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:26 PM PDT 24 |
530442027 ps |
| T925 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2449754773 |
|
|
Mar 28 12:45:47 PM PDT 24 |
Mar 28 12:45:48 PM PDT 24 |
15324753 ps |
| T926 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3372819331 |
|
|
Mar 28 12:34:51 PM PDT 24 |
Mar 28 12:34:57 PM PDT 24 |
425446151 ps |
| T927 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.647545532 |
|
|
Mar 28 12:34:26 PM PDT 24 |
Mar 28 12:34:31 PM PDT 24 |
64908778 ps |
| T928 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.374572968 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:53 PM PDT 24 |
31682773 ps |
| T929 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2763864276 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:45 PM PDT 24 |
15315298 ps |
| T930 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1065998354 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:37 PM PDT 24 |
576352207 ps |
| T931 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1908365573 |
|
|
Mar 28 12:45:35 PM PDT 24 |
Mar 28 12:45:40 PM PDT 24 |
341977544 ps |
| T932 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3366142484 |
|
|
Mar 28 12:34:21 PM PDT 24 |
Mar 28 12:34:22 PM PDT 24 |
15745512 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3361238486 |
|
|
Mar 28 12:45:10 PM PDT 24 |
Mar 28 12:45:13 PM PDT 24 |
865155762 ps |
| T933 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2309156049 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
61624565 ps |
| T934 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3325582917 |
|
|
Mar 28 12:34:26 PM PDT 24 |
Mar 28 12:34:33 PM PDT 24 |
93413877 ps |
| T192 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1516624051 |
|
|
Mar 28 12:45:10 PM PDT 24 |
Mar 28 12:45:11 PM PDT 24 |
12448542 ps |
| T118 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4255846073 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:49 PM PDT 24 |
1051904045 ps |
| T935 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1482072925 |
|
|
Mar 28 12:34:27 PM PDT 24 |
Mar 28 12:34:29 PM PDT 24 |
59278148 ps |
| T936 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2793073130 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:26 PM PDT 24 |
31715042 ps |
| T937 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3570553394 |
|
|
Mar 28 12:45:59 PM PDT 24 |
Mar 28 12:46:16 PM PDT 24 |
1332292798 ps |
| T938 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3761116896 |
|
|
Mar 28 12:45:39 PM PDT 24 |
Mar 28 12:45:42 PM PDT 24 |
49994185 ps |
| T119 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2903562907 |
|
|
Mar 28 12:45:43 PM PDT 24 |
Mar 28 12:45:46 PM PDT 24 |
1065378299 ps |
| T939 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2925210834 |
|
|
Mar 28 12:45:39 PM PDT 24 |
Mar 28 12:45:42 PM PDT 24 |
477522546 ps |
| T940 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3139591525 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
912348353 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.953501251 |
|
|
Mar 28 12:34:53 PM PDT 24 |
Mar 28 12:34:55 PM PDT 24 |
123720106 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.177202016 |
|
|
Mar 28 12:45:45 PM PDT 24 |
Mar 28 12:46:09 PM PDT 24 |
4220298326 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3009348149 |
|
|
Mar 28 12:34:20 PM PDT 24 |
Mar 28 12:34:25 PM PDT 24 |
609833676 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2637235458 |
|
|
Mar 28 12:34:19 PM PDT 24 |
Mar 28 12:34:20 PM PDT 24 |
304871600 ps |
| T945 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1704802794 |
|
|
Mar 28 12:34:23 PM PDT 24 |
Mar 28 12:34:24 PM PDT 24 |
44030125 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2526306586 |
|
|
Mar 28 12:34:50 PM PDT 24 |
Mar 28 12:34:52 PM PDT 24 |
69167577 ps |
| T947 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4275943459 |
|
|
Mar 28 12:45:35 PM PDT 24 |
Mar 28 12:45:37 PM PDT 24 |
31854669 ps |
| T948 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2377729181 |
|
|
Mar 28 12:45:13 PM PDT 24 |
Mar 28 12:45:38 PM PDT 24 |
1083371804 ps |
| T949 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.137403841 |
|
|
Mar 28 12:45:11 PM PDT 24 |
Mar 28 12:45:13 PM PDT 24 |
296674848 ps |
| T138 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2029866772 |
|
|
Mar 28 12:45:53 PM PDT 24 |
Mar 28 12:45:56 PM PDT 24 |
311376081 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2358311122 |
|
|
Mar 28 12:34:30 PM PDT 24 |
Mar 28 12:34:34 PM PDT 24 |
116436943 ps |
| T951 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.868858469 |
|
|
Mar 28 12:45:44 PM PDT 24 |
Mar 28 12:45:47 PM PDT 24 |
19236465 ps |
| T952 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.829522110 |
|
|
Mar 28 12:34:31 PM PDT 24 |
Mar 28 12:34:32 PM PDT 24 |
16731245 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2684400409 |
|
|
Mar 28 12:45:47 PM PDT 24 |
Mar 28 12:45:50 PM PDT 24 |
141859088 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3174170596 |
|
|
Mar 28 12:45:41 PM PDT 24 |
Mar 28 12:45:43 PM PDT 24 |
24767296 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.599340870 |
|
|
Mar 28 12:34:27 PM PDT 24 |
Mar 28 12:34:28 PM PDT 24 |
33407884 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.556162962 |
|
|
Mar 28 12:34:37 PM PDT 24 |
Mar 28 12:34:38 PM PDT 24 |
26038594 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2728294369 |
|
|
Mar 28 12:34:21 PM PDT 24 |
Mar 28 12:34:30 PM PDT 24 |
1487947802 ps |
| T137 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3864535116 |
|
|
Mar 28 12:46:04 PM PDT 24 |
Mar 28 12:46:07 PM PDT 24 |
255537135 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1523271918 |
|
|
Mar 28 12:45:40 PM PDT 24 |
Mar 28 12:45:41 PM PDT 24 |
93415285 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.109229907 |
|
|
Mar 28 12:34:27 PM PDT 24 |
Mar 28 12:34:30 PM PDT 24 |
192792592 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3890125415 |
|
|
Mar 28 12:34:22 PM PDT 24 |
Mar 28 12:34:23 PM PDT 24 |
164833206 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1837679285 |
|
|
Mar 28 12:34:30 PM PDT 24 |
Mar 28 12:34:31 PM PDT 24 |
28166796 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2796841949 |
|
|
Mar 28 12:34:24 PM PDT 24 |
Mar 28 12:34:25 PM PDT 24 |
161084528 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2743023116 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
24233445 ps |
| T964 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.932918939 |
|
|
Mar 28 12:45:45 PM PDT 24 |
Mar 28 12:45:48 PM PDT 24 |
936797738 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4286096383 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
107867434 ps |
| T966 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3521911864 |
|
|
Mar 28 12:45:48 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
209816590 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3825752300 |
|
|
Mar 28 12:34:21 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
295413862 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.287921958 |
|
|
Mar 28 12:45:09 PM PDT 24 |
Mar 28 12:45:11 PM PDT 24 |
154747030 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2245831832 |
|
|
Mar 28 12:34:23 PM PDT 24 |
Mar 28 12:34:29 PM PDT 24 |
18369583 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1780960135 |
|
|
Mar 28 12:45:42 PM PDT 24 |
Mar 28 12:45:54 PM PDT 24 |
886530566 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2790754785 |
|
|
Mar 28 12:34:52 PM PDT 24 |
Mar 28 12:34:53 PM PDT 24 |
24513479 ps |
| T193 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3282628883 |
|
|
Mar 28 12:45:10 PM PDT 24 |
Mar 28 12:45:12 PM PDT 24 |
16636528 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4163718590 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:49 PM PDT 24 |
70324695 ps |
| T115 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4283475494 |
|
|
Mar 28 12:34:55 PM PDT 24 |
Mar 28 12:35:01 PM PDT 24 |
284405015 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.972680894 |
|
|
Mar 28 12:45:47 PM PDT 24 |
Mar 28 12:46:06 PM PDT 24 |
1603224956 ps |
| T974 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2664861784 |
|
|
Mar 28 12:34:51 PM PDT 24 |
Mar 28 12:34:53 PM PDT 24 |
37774000 ps |
| T194 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3807559258 |
|
|
Mar 28 12:34:29 PM PDT 24 |
Mar 28 12:34:31 PM PDT 24 |
151757528 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3400665025 |
|
|
Mar 28 12:45:38 PM PDT 24 |
Mar 28 12:45:46 PM PDT 24 |
2412906081 ps |
| T976 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1605480979 |
|
|
Mar 28 12:34:38 PM PDT 24 |
Mar 28 12:34:40 PM PDT 24 |
69323081 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1285464739 |
|
|
Mar 28 12:34:21 PM PDT 24 |
Mar 28 12:34:23 PM PDT 24 |
114289847 ps |
| T195 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1663453721 |
|
|
Mar 28 12:45:52 PM PDT 24 |
Mar 28 12:45:53 PM PDT 24 |
16072356 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2292013324 |
|
|
Mar 28 12:45:47 PM PDT 24 |
Mar 28 12:45:48 PM PDT 24 |
41827332 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1877358320 |
|
|
Mar 28 12:34:25 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
31697471 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2962142123 |
|
|
Mar 28 12:45:44 PM PDT 24 |
Mar 28 12:45:48 PM PDT 24 |
158492976 ps |
| T981 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1216978480 |
|
|
Mar 28 12:45:46 PM PDT 24 |
Mar 28 12:45:50 PM PDT 24 |
858478252 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3362094198 |
|
|
Mar 28 12:34:25 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
23559467 ps |
| T983 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3879512516 |
|
|
Mar 28 12:45:39 PM PDT 24 |
Mar 28 12:45:41 PM PDT 24 |
257729115 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1470433252 |
|
|
Mar 28 12:45:49 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
27993706 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2201106727 |
|
|
Mar 28 12:45:41 PM PDT 24 |
Mar 28 12:45:42 PM PDT 24 |
21536289 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4082972092 |
|
|
Mar 28 12:34:29 PM PDT 24 |
Mar 28 12:34:32 PM PDT 24 |
55845044 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2779608112 |
|
|
Mar 28 12:45:52 PM PDT 24 |
Mar 28 12:45:53 PM PDT 24 |
14195534 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2729366015 |
|
|
Mar 28 12:45:54 PM PDT 24 |
Mar 28 12:45:56 PM PDT 24 |
35839464 ps |
| T989 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3396827905 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:53 PM PDT 24 |
19973052 ps |
| T990 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1878245671 |
|
|
Mar 28 12:34:53 PM PDT 24 |
Mar 28 12:34:57 PM PDT 24 |
131045630 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2331846937 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:55 PM PDT 24 |
130875744 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3079635493 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
84877518 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3705343776 |
|
|
Mar 28 12:34:25 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
41228253 ps |
| T994 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2175336524 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
30471528 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.371288381 |
|
|
Mar 28 12:34:26 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
26065558 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3779026142 |
|
|
Mar 28 12:34:23 PM PDT 24 |
Mar 28 12:34:25 PM PDT 24 |
38910870 ps |
| T196 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2087672691 |
|
|
Mar 28 12:34:25 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
15441864 ps |
| T997 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3151043082 |
|
|
Mar 28 12:45:47 PM PDT 24 |
Mar 28 12:45:49 PM PDT 24 |
20482394 ps |
| T121 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3292038639 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:54 PM PDT 24 |
208808539 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3328187846 |
|
|
Mar 28 12:34:37 PM PDT 24 |
Mar 28 12:34:43 PM PDT 24 |
501974582 ps |
| T999 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2533011593 |
|
|
Mar 28 12:34:50 PM PDT 24 |
Mar 28 12:34:51 PM PDT 24 |
103509431 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2449541942 |
|
|
Mar 28 12:45:42 PM PDT 24 |
Mar 28 12:45:44 PM PDT 24 |
33450294 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3684326890 |
|
|
Mar 28 12:45:42 PM PDT 24 |
Mar 28 12:45:45 PM PDT 24 |
227815329 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3645533745 |
|
|
Mar 28 12:45:40 PM PDT 24 |
Mar 28 12:45:42 PM PDT 24 |
13795421 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.944632396 |
|
|
Mar 28 12:45:37 PM PDT 24 |
Mar 28 12:45:39 PM PDT 24 |
132263291 ps |
| T1004 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3303722111 |
|
|
Mar 28 12:34:56 PM PDT 24 |
Mar 28 12:34:59 PM PDT 24 |
14737720 ps |
| T1005 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2441767182 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
40251212 ps |
| T1006 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.730990362 |
|
|
Mar 28 12:45:50 PM PDT 24 |
Mar 28 12:45:51 PM PDT 24 |
185774136 ps |
| T1007 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1006315430 |
|
|
Mar 28 12:45:42 PM PDT 24 |
Mar 28 12:45:44 PM PDT 24 |
158769435 ps |
| T1008 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3862921019 |
|
|
Mar 28 12:45:12 PM PDT 24 |
Mar 28 12:45:14 PM PDT 24 |
54461480 ps |
| T134 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1501922422 |
|
|
Mar 28 12:34:50 PM PDT 24 |
Mar 28 12:34:54 PM PDT 24 |
117490078 ps |
| T1009 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1718433310 |
|
|
Mar 28 12:34:25 PM PDT 24 |
Mar 28 12:34:29 PM PDT 24 |
219908040 ps |
| T1010 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3337803835 |
|
|
Mar 28 12:35:00 PM PDT 24 |
Mar 28 12:35:04 PM PDT 24 |
54151298 ps |
| T1011 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3517970214 |
|
|
Mar 28 12:45:13 PM PDT 24 |
Mar 28 12:45:16 PM PDT 24 |
403688746 ps |
| T1012 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.414772852 |
|
|
Mar 28 12:34:36 PM PDT 24 |
Mar 28 12:34:37 PM PDT 24 |
27327960 ps |
| T197 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.246298024 |
|
|
Mar 28 12:34:23 PM PDT 24 |
Mar 28 12:34:24 PM PDT 24 |
20780100 ps |
| T1013 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.430432198 |
|
|
Mar 28 12:34:25 PM PDT 24 |
Mar 28 12:34:28 PM PDT 24 |
56852378 ps |
| T1014 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3196447059 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:52 PM PDT 24 |
26227467 ps |
| T1015 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.977669057 |
|
|
Mar 28 12:45:51 PM PDT 24 |
Mar 28 12:45:56 PM PDT 24 |
186014909 ps |
| T1016 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1502609691 |
|
|
Mar 28 12:34:19 PM PDT 24 |
Mar 28 12:34:21 PM PDT 24 |
23476587 ps |
| T1017 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3068026726 |
|
|
Mar 28 12:45:41 PM PDT 24 |
Mar 28 12:45:43 PM PDT 24 |
49269692 ps |
| T1018 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1357340555 |
|
|
Mar 28 12:35:01 PM PDT 24 |
Mar 28 12:35:05 PM PDT 24 |
39423070 ps |
| T1019 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1733814475 |
|
|
Mar 28 12:45:39 PM PDT 24 |
Mar 28 12:45:40 PM PDT 24 |
11510785 ps |
| T198 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2806514159 |
|
|
Mar 28 12:34:26 PM PDT 24 |
Mar 28 12:34:27 PM PDT 24 |
20147037 ps |
| T1020 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1172569973 |
|
|
Mar 28 12:45:40 PM PDT 24 |
Mar 28 12:45:43 PM PDT 24 |
207571258 ps |