Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

215876660

1

T1

87037

T2

4846

T3

18042

auto[1]

2946254

1

T1

4444

T2

198

T3

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

215831470

1

T1

88418

T2

4747

T3

17844

auto[1]

2991444

1

T1

3063

T2

297

T3

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	15321259	1			T1	10978		T2	1437		T3	5289
auto[IdleSt]	44986051	1			T1	35589		T2	849		T3	1938
auto[ClkMuxSt]	73739	1			T1	28		T2	8		T3	55
auto[CntIncrSt]	73190	1			T1	28		T2	8		T3	55
auto[CntProgSt]	4143195	1			T1	56		T2	16		T3	1325
auto[TransCheckSt]	56821	1			T1	11		T2	8		T3	43
auto[TokenHashSt]	87422772	1			T1	183		T2	90		T3	691
auto[FlashRmaSt]	57402	1			T1	46		T2	46		T3	35
auto[TokenCheck0St]	26418	1			T1	11		T2	8		T3	16
auto[TokenCheck1St]	19751	1			T1	11		T2	8		T3	10
auto[TransProgSt]	1076008	1			T1	22		T2	16		T3	270
auto[PostTransSt]	26509842	1			T1	17320		T2	1351		T3	7626
auto[ScrapSt]	273411	1			T12	36		T5	713		T21	278
auto[EscalateSt]	14380655	1			T1	19110		T2	871		T3	986
auto[InvalidSt]	24398197	1			T1	8082		T2	326		T11	8221

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	4203	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	24398197	1			T1	8082		T2	326		T11	8221
EscalateSt	14380655	1			T1	19110		T2	871		T3	986
ScrapSt	273411	1			T12	36		T5	713		T21	278
PostTransSt	26509842	1			T1	17320		T2	1351		T3	7626
TransProgSt	1076008	1			T1	22		T2	16		T3	270
TokenCheck1St	19751	1			T1	11		T2	8		T3	10
TokenCheck0St	26418	1			T1	11		T2	8		T3	16
FlashRmaSt	57402	1			T1	46		T2	46		T3	35
TokenHashSt	87422772	1			T1	183		T2	90		T3	691
TransCheckSt	56821	1			T1	11		T2	8		T3	43
CntProgSt	4143195	1			T1	56		T2	16		T3	1325
CntIncrSt	73190	1			T1	28		T2	8		T3	55
ClkMuxSt	73739	1			T1	28		T2	8		T3	55
IdleSt	44986051	1			T1	35589		T2	849		T3	1938
ResetSt	15321259	1			T1	10978		T2	1437		T3	5289
arcs[ResetSt=>IdleSt]	113418	1			T1	97		T2	14		T3	56
arcs[IdleSt=>ScrapSt]	616	1			T12	1		T5	4		T21	1
arcs[IdleSt=>ClkMuxSt]	73295	1			T1	28		T2	8		T3	55
arcs[ClkMuxSt=>CntIncrSt]	73190	1			T1	28		T2	8		T3	55
arcs[CntIncrSt=>PostTransSt]	3495	1			T3	4		T4	5		T5	39
arcs[CntIncrSt=>CntProgSt]	69578	1			T1	28		T2	8		T3	51
arcs[CntProgSt=>PostTransSt]	10545	1			T1	17		T3	8		T4	11
arcs[CntProgSt=>TransCheckSt]	56821	1			T1	11		T2	8		T3	43
arcs[TransCheckSt=>PostTransSt]	7609	1			T3	9		T4	9		T5	41
arcs[TransCheckSt=>TokenHashSt]	48959	1			T1	11		T2	8		T3	34
arcs[TokenHashSt=>PostTransSt]	20998	1			T3	18		T4	25		T10	78
arcs[TokenHashSt=>FlashRmaSt]	26609	1			T1	11		T2	8		T3	16
arcs[FlashRmaSt=>TokenCheck0St]	26418	1			T1	11		T2	8		T3	16
arcs[TokenCheck0St=>PostTransSt]	6605	1			T3	6		T4	2		T5	35
arcs[TokenCheck0St=>TokenCheck1St]	19751	1			T1	11		T2	8		T3	10
arcs[TokenCheck1St=>PostTransSt]	1322	1			T5	8		T20	7		T48	6
arcs[TransProgSt=>PostTransSt]	16533	1			T1	11		T2	8		T3	10
arcs[IdleSt=>EscalateSt]	401	1			T52	4		T49	3		T53	6
arcs[ClkMuxSt=>EscalateSt]	105	1			T34	2		T49	2		T50	1
arcs[CntIncrSt=>EscalateSt]	117	1			T34	2		T51	2		T52	1
arcs[CntProgSt=>EscalateSt]	2212	1			T34	37		T51	24		T52	6
arcs[TransCheckSt=>EscalateSt]	253	1			T34	1		T52	6		T49	6
arcs[TokenHashSt=>EscalateSt]	1352	1			T34	10		T51	6		T52	16
arcs[FlashRmaSt=>EscalateSt]	191	1			T34	2		T51	2		T52	2
arcs[TokenCheck0St=>EscalateSt]	62	1			T34	1		T52	1		T57	1
arcs[TokenCheck1St=>EscalateSt]	310	1			T34	1		T51	5		T49	3
arcs[TransProgSt=>EscalateSt]	1586	1			T34	24		T51	24		T52	8
arcs[PostTransSt=>EscalateSt]	10989	1			T1	17		T3	8		T4	11
arcs[InvalidSt=>EscalateSt]	30085	1			T1	59		T2	5		T11	58

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	15320899	1			T1	10978		T2	1437		T3	5289
auto[0]	auto[IdleSt]	44985795	1			T1	35589		T2	849		T3	1938
auto[0]	auto[ClkMuxSt]	73673	1			T1	28		T2	8		T3	55
auto[0]	auto[CntIncrSt]	73111	1			T1	28		T2	8		T3	55
auto[0]	auto[CntProgSt]	4141724	1			T1	56		T2	16		T3	1325
auto[0]	auto[TransCheckSt]	56649	1			T1	11		T2	8		T3	43
auto[0]	auto[TokenHashSt]	87421903	1			T1	183		T2	90		T3	691
auto[0]	auto[FlashRmaSt]	57268	1			T1	46		T2	46		T3	35
auto[0]	auto[TokenCheck0St]	26379	1			T1	11		T2	8		T3	16
auto[0]	auto[TokenCheck1St]	19533	1			T1	11		T2	8		T3	10
auto[0]	auto[TransProgSt]	1074960	1			T1	22		T2	16		T3	270
auto[0]	auto[PostTransSt]	26504411	1			T1	17309		T2	1351		T3	7623
auto[0]	auto[ScrapSt]	273326	1			T12	36		T5	713		T21	278
auto[0]	auto[EscalateSt]	11459594	1			T1	14711		T2	675		T3	692
auto[0]	auto[InvalidSt]	24383232	1			T1	8048		T2	324		T11	8197
auto[1]	auto[ResetSt]	360	1			T34	4		T51	6		T52	1
auto[1]	auto[IdleSt]	256	1			T52	4		T49	1		T53	5
auto[1]	auto[ClkMuxSt]	66	1			T34	2		T50	1		T271	1
auto[1]	auto[CntIncrSt]	79	1			T34	1		T51	1		T49	1
auto[1]	auto[CntProgSt]	1471	1			T34	21		T51	17		T52	4
auto[1]	auto[TransCheckSt]	172	1			T34	1		T52	5		T49	4
auto[1]	auto[TokenHashSt]	869	1			T34	4		T51	1		T52	11
auto[1]	auto[FlashRmaSt]	134	1			T34	1		T51	1		T52	2
auto[1]	auto[TokenCheck0St]	39	1			T57	1		T272	1		T273	1
auto[1]	auto[TokenCheck1St]	218	1			T34	1		T51	2		T49	3
auto[1]	auto[TransProgSt]	1048	1			T34	11		T51	18		T52	4
auto[1]	auto[PostTransSt]	5431	1			T1	11		T3	3		T4	5
auto[1]	auto[ScrapSt]	85	1			T34	2		T51	3		T52	1
auto[1]	auto[EscalateSt]	2921061	1			T1	4399		T2	196		T3	294
auto[1]	auto[InvalidSt]	14965	1			T1	34		T2	2		T11	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	15320911	1			T1	10978		T2	1437		T3	5289
auto[0]	auto[IdleSt]	44985786	1			T1	35589		T2	849		T3	1938
auto[0]	auto[ClkMuxSt]	73674	1			T1	28		T2	8		T3	55
auto[0]	auto[CntIncrSt]	73116	1			T1	28		T2	8		T3	55
auto[0]	auto[CntProgSt]	4141726	1			T1	56		T2	16		T3	1325
auto[0]	auto[TransCheckSt]	56654	1			T1	11		T2	8		T3	43
auto[0]	auto[TokenHashSt]	87421852	1			T1	183		T2	90		T3	691
auto[0]	auto[FlashRmaSt]	57277	1			T1	46		T2	46		T3	35
auto[0]	auto[TokenCheck0St]	26378	1			T1	11		T2	8		T3	16
auto[0]	auto[TokenCheck1St]	19553	1			T1	11		T2	8		T3	10
auto[0]	auto[TransProgSt]	1074941	1			T1	22		T2	16		T3	270
auto[0]	auto[PostTransSt]	26504146	1			T1	17314		T2	1351		T3	7621
auto[0]	auto[ScrapSt]	273317	1			T12	36		T5	713		T21	278
auto[0]	auto[EscalateSt]	11414859	1			T1	16078		T2	577		T3	496
auto[0]	auto[InvalidSt]	24383077	1			T1	8057		T2	323		T11	8187
auto[1]	auto[ResetSt]	348	1			T34	2		T51	4		T52	1
auto[1]	auto[IdleSt]	265	1			T52	1		T49	2		T53	4
auto[1]	auto[ClkMuxSt]	65	1			T34	1		T49	2		T50	1
auto[1]	auto[CntIncrSt]	74	1			T34	2		T51	1		T52	1
auto[1]	auto[CntProgSt]	1469	1			T34	32		T51	17		T52	2
auto[1]	auto[TransCheckSt]	167	1			T34	1		T52	5		T49	6
auto[1]	auto[TokenHashSt]	920	1			T34	7		T51	6		T52	13
auto[1]	auto[FlashRmaSt]	125	1			T34	1		T51	1		T52	1
auto[1]	auto[TokenCheck0St]	40	1			T34	1		T52	1		T57	1
auto[1]	auto[TokenCheck1St]	198	1			T34	1		T51	5		T49	2
auto[1]	auto[TransProgSt]	1067	1			T34	22		T51	16		T52	6
auto[1]	auto[PostTransSt]	5696	1			T1	6		T3	5		T4	6
auto[1]	auto[ScrapSt]	94	1			T34	1		T51	2		T49	2
auto[1]	auto[EscalateSt]	2965796	1			T1	3032		T2	294		T3	490
auto[1]	auto[InvalidSt]	15120	1			T1	25		T2	3		T11	34