| T140 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3189101407 |
|
|
Mar 31 12:25:38 PM PDT 24 |
Mar 31 12:25:42 PM PDT 24 |
100674992 ps |
| T1782 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4015304206 |
|
|
Mar 31 12:25:49 PM PDT 24 |
Mar 31 12:25:50 PM PDT 24 |
28069353 ps |
| T1783 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.343090748 |
|
|
Mar 31 12:36:49 PM PDT 24 |
Mar 31 12:36:50 PM PDT 24 |
65717235 ps |
| T1784 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.32755700 |
|
|
Mar 31 12:25:42 PM PDT 24 |
Mar 31 12:25:43 PM PDT 24 |
120849775 ps |
| T1785 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3055239068 |
|
|
Mar 31 12:25:46 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
64103174 ps |
| T1786 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.786028012 |
|
|
Mar 31 12:36:55 PM PDT 24 |
Mar 31 12:37:28 PM PDT 24 |
2813326811 ps |
| T1787 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1571349035 |
|
|
Mar 31 12:25:50 PM PDT 24 |
Mar 31 12:25:51 PM PDT 24 |
37998108 ps |
| T240 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2469639490 |
|
|
Mar 31 12:37:28 PM PDT 24 |
Mar 31 12:37:29 PM PDT 24 |
18360061 ps |
| T1788 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.231728757 |
|
|
Mar 31 12:25:42 PM PDT 24 |
Mar 31 12:25:44 PM PDT 24 |
367503957 ps |
| T1789 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1661033552 |
|
|
Mar 31 12:25:38 PM PDT 24 |
Mar 31 12:25:50 PM PDT 24 |
923842265 ps |
| T1790 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3640354267 |
|
|
Mar 31 12:37:29 PM PDT 24 |
Mar 31 12:37:30 PM PDT 24 |
461798384 ps |
| T1791 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3289583980 |
|
|
Mar 31 12:36:59 PM PDT 24 |
Mar 31 12:37:01 PM PDT 24 |
140676518 ps |
| T1792 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1609261025 |
|
|
Mar 31 12:37:10 PM PDT 24 |
Mar 31 12:37:11 PM PDT 24 |
49235116 ps |
| T1793 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.260344550 |
|
|
Mar 31 12:25:49 PM PDT 24 |
Mar 31 12:25:51 PM PDT 24 |
35544331 ps |
| T166 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2886589204 |
|
|
Mar 31 12:25:48 PM PDT 24 |
Mar 31 12:25:50 PM PDT 24 |
318069704 ps |
| T1794 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2725827682 |
|
|
Mar 31 12:37:19 PM PDT 24 |
Mar 31 12:37:21 PM PDT 24 |
182449821 ps |
| T1795 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.885135240 |
|
|
Mar 31 12:25:16 PM PDT 24 |
Mar 31 12:25:17 PM PDT 24 |
83114159 ps |
| T241 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1551146116 |
|
|
Mar 31 12:37:04 PM PDT 24 |
Mar 31 12:37:05 PM PDT 24 |
119317421 ps |
| T1796 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3001691913 |
|
|
Mar 31 12:36:53 PM PDT 24 |
Mar 31 12:36:54 PM PDT 24 |
71447516 ps |
| T1797 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1513133741 |
|
|
Mar 31 12:25:58 PM PDT 24 |
Mar 31 12:25:59 PM PDT 24 |
29149128 ps |
| T141 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.639763372 |
|
|
Mar 31 12:25:44 PM PDT 24 |
Mar 31 12:25:47 PM PDT 24 |
154369992 ps |
| T1798 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1780098047 |
|
|
Mar 31 12:37:19 PM PDT 24 |
Mar 31 12:37:21 PM PDT 24 |
36889974 ps |
| T242 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4049143858 |
|
|
Mar 31 12:25:43 PM PDT 24 |
Mar 31 12:25:44 PM PDT 24 |
55523292 ps |
| T1799 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.406818635 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:51 PM PDT 24 |
328537955 ps |
| T1800 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3893572518 |
|
|
Mar 31 12:37:23 PM PDT 24 |
Mar 31 12:37:25 PM PDT 24 |
15078326 ps |
| T162 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3721626394 |
|
|
Mar 31 12:25:49 PM PDT 24 |
Mar 31 12:25:54 PM PDT 24 |
271502344 ps |
| T1801 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3849282783 |
|
|
Mar 31 12:26:05 PM PDT 24 |
Mar 31 12:26:14 PM PDT 24 |
115851026 ps |
| T1802 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.816806941 |
|
|
Mar 31 12:25:52 PM PDT 24 |
Mar 31 12:25:54 PM PDT 24 |
767142312 ps |
| T1803 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2324092311 |
|
|
Mar 31 12:36:50 PM PDT 24 |
Mar 31 12:36:52 PM PDT 24 |
679320076 ps |
| T1804 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.632834889 |
|
|
Mar 31 12:25:58 PM PDT 24 |
Mar 31 12:26:01 PM PDT 24 |
247510621 ps |
| T1805 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2963896991 |
|
|
Mar 31 12:37:03 PM PDT 24 |
Mar 31 12:37:06 PM PDT 24 |
73569807 ps |
| T1806 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3727937735 |
|
|
Mar 31 12:37:13 PM PDT 24 |
Mar 31 12:37:45 PM PDT 24 |
1357991442 ps |
| T1807 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3056221721 |
|
|
Mar 31 12:37:18 PM PDT 24 |
Mar 31 12:37:23 PM PDT 24 |
1415550435 ps |
| T1808 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2687839965 |
|
|
Mar 31 12:37:21 PM PDT 24 |
Mar 31 12:37:23 PM PDT 24 |
80150125 ps |
| T1809 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.629721582 |
|
|
Mar 31 12:37:27 PM PDT 24 |
Mar 31 12:37:30 PM PDT 24 |
254493888 ps |
| T1810 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3536066516 |
|
|
Mar 31 12:37:13 PM PDT 24 |
Mar 31 12:37:14 PM PDT 24 |
46883283 ps |
| T1811 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1687588235 |
|
|
Mar 31 12:25:07 PM PDT 24 |
Mar 31 12:25:08 PM PDT 24 |
33666327 ps |
| T1812 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2055287579 |
|
|
Mar 31 12:37:06 PM PDT 24 |
Mar 31 12:37:12 PM PDT 24 |
971896150 ps |
| T1813 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4090978917 |
|
|
Mar 31 12:37:11 PM PDT 24 |
Mar 31 12:37:25 PM PDT 24 |
2386211365 ps |
| T243 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2678975717 |
|
|
Mar 31 12:25:49 PM PDT 24 |
Mar 31 12:25:49 PM PDT 24 |
38801768 ps |
| T1814 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.353200871 |
|
|
Mar 31 12:26:09 PM PDT 24 |
Mar 31 12:26:12 PM PDT 24 |
141608840 ps |
| T1815 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2257016382 |
|
|
Mar 31 12:36:42 PM PDT 24 |
Mar 31 12:36:43 PM PDT 24 |
225530742 ps |
| T1816 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3989558774 |
|
|
Mar 31 12:37:15 PM PDT 24 |
Mar 31 12:37:19 PM PDT 24 |
703765890 ps |
| T1817 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3868820163 |
|
|
Mar 31 12:37:28 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
52273306 ps |
| T1818 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.27789188 |
|
|
Mar 31 12:37:02 PM PDT 24 |
Mar 31 12:37:04 PM PDT 24 |
22350932 ps |
| T1819 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3502322197 |
|
|
Mar 31 12:36:48 PM PDT 24 |
Mar 31 12:36:54 PM PDT 24 |
614176929 ps |
| T1820 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.391316785 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
46470951 ps |
| T1821 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2799791043 |
|
|
Mar 31 12:25:34 PM PDT 24 |
Mar 31 12:25:35 PM PDT 24 |
45473748 ps |
| T1822 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1617533690 |
|
|
Mar 31 12:25:33 PM PDT 24 |
Mar 31 12:25:34 PM PDT 24 |
130218806 ps |
| T1823 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4136596198 |
|
|
Mar 31 12:25:51 PM PDT 24 |
Mar 31 12:25:53 PM PDT 24 |
280802050 ps |
| T1824 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1715352684 |
|
|
Mar 31 12:25:26 PM PDT 24 |
Mar 31 12:25:27 PM PDT 24 |
41986053 ps |
| T1825 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2401660284 |
|
|
Mar 31 12:25:56 PM PDT 24 |
Mar 31 12:25:57 PM PDT 24 |
56872547 ps |
| T153 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.832074163 |
|
|
Mar 31 12:25:36 PM PDT 24 |
Mar 31 12:25:40 PM PDT 24 |
443444375 ps |
| T1826 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1751510971 |
|
|
Mar 31 12:36:50 PM PDT 24 |
Mar 31 12:36:51 PM PDT 24 |
88521774 ps |
| T1827 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3077875354 |
|
|
Mar 31 12:25:53 PM PDT 24 |
Mar 31 12:25:54 PM PDT 24 |
37646987 ps |
| T1828 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1781229882 |
|
|
Mar 31 12:37:20 PM PDT 24 |
Mar 31 12:37:22 PM PDT 24 |
25173599 ps |
| T1829 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3979933963 |
|
|
Mar 31 12:37:14 PM PDT 24 |
Mar 31 12:37:16 PM PDT 24 |
43373301 ps |
| T1830 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1208941969 |
|
|
Mar 31 12:25:43 PM PDT 24 |
Mar 31 12:26:00 PM PDT 24 |
2142322584 ps |
| T1831 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1756594295 |
|
|
Mar 31 12:25:15 PM PDT 24 |
Mar 31 12:25:17 PM PDT 24 |
105256968 ps |
| T1832 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3113515445 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:50 PM PDT 24 |
857744507 ps |
| T244 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3964726109 |
|
|
Mar 31 12:37:03 PM PDT 24 |
Mar 31 12:37:04 PM PDT 24 |
17921203 ps |
| T1833 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1376113544 |
|
|
Mar 31 12:37:06 PM PDT 24 |
Mar 31 12:37:07 PM PDT 24 |
78834693 ps |
| T1834 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3229704390 |
|
|
Mar 31 12:26:02 PM PDT 24 |
Mar 31 12:26:07 PM PDT 24 |
101262711 ps |
| T1835 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2556446452 |
|
|
Mar 31 12:25:59 PM PDT 24 |
Mar 31 12:26:01 PM PDT 24 |
75710933 ps |
| T1836 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3104342788 |
|
|
Mar 31 12:25:49 PM PDT 24 |
Mar 31 12:25:53 PM PDT 24 |
145984947 ps |
| T1837 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3479286627 |
|
|
Mar 31 12:25:45 PM PDT 24 |
Mar 31 12:25:55 PM PDT 24 |
940817032 ps |
| T1838 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3114296158 |
|
|
Mar 31 12:36:54 PM PDT 24 |
Mar 31 12:36:56 PM PDT 24 |
166236015 ps |
| T1839 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1148674149 |
|
|
Mar 31 12:25:38 PM PDT 24 |
Mar 31 12:25:40 PM PDT 24 |
75713677 ps |
| T1840 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1158770453 |
|
|
Mar 31 12:25:20 PM PDT 24 |
Mar 31 12:25:22 PM PDT 24 |
55569653 ps |
| T1841 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.867341510 |
|
|
Mar 31 12:37:06 PM PDT 24 |
Mar 31 12:37:07 PM PDT 24 |
77671034 ps |
| T1842 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.977619524 |
|
|
Mar 31 12:26:00 PM PDT 24 |
Mar 31 12:26:08 PM PDT 24 |
300107464 ps |
| T1843 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3149319714 |
|
|
Mar 31 12:25:55 PM PDT 24 |
Mar 31 12:25:57 PM PDT 24 |
197129151 ps |
| T1844 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2700647942 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
14407820 ps |
| T1845 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1810727849 |
|
|
Mar 31 12:25:41 PM PDT 24 |
Mar 31 12:25:43 PM PDT 24 |
65017168 ps |
| T164 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2603500041 |
|
|
Mar 31 12:37:08 PM PDT 24 |
Mar 31 12:37:12 PM PDT 24 |
103702865 ps |
| T1846 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2676376263 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
16094164 ps |
| T1847 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1072198938 |
|
|
Mar 31 12:26:04 PM PDT 24 |
Mar 31 12:26:05 PM PDT 24 |
15322090 ps |
| T1848 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.67740192 |
|
|
Mar 31 12:25:14 PM PDT 24 |
Mar 31 12:25:23 PM PDT 24 |
1525459289 ps |
| T1849 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3011122958 |
|
|
Mar 31 12:25:54 PM PDT 24 |
Mar 31 12:25:55 PM PDT 24 |
54109549 ps |
| T1850 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.588861588 |
|
|
Mar 31 12:37:29 PM PDT 24 |
Mar 31 12:37:36 PM PDT 24 |
100674129 ps |
| T1851 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1611986818 |
|
|
Mar 31 12:37:19 PM PDT 24 |
Mar 31 12:37:20 PM PDT 24 |
57007647 ps |
| T1852 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.55261410 |
|
|
Mar 31 12:25:58 PM PDT 24 |
Mar 31 12:25:59 PM PDT 24 |
101338445 ps |
| T1853 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3717641378 |
|
|
Mar 31 12:37:30 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
14919976 ps |
| T1854 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1234795059 |
|
|
Mar 31 12:37:12 PM PDT 24 |
Mar 31 12:37:13 PM PDT 24 |
61137781 ps |
| T1855 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1947681647 |
|
|
Mar 31 12:37:24 PM PDT 24 |
Mar 31 12:37:42 PM PDT 24 |
1604170843 ps |
| T1856 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3092480107 |
|
|
Mar 31 12:37:29 PM PDT 24 |
Mar 31 12:37:30 PM PDT 24 |
368257413 ps |
| T1857 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2831958384 |
|
|
Mar 31 12:26:46 PM PDT 24 |
Mar 31 12:26:48 PM PDT 24 |
108900779 ps |
| T1858 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1786846373 |
|
|
Mar 31 12:25:49 PM PDT 24 |
Mar 31 12:25:52 PM PDT 24 |
125402167 ps |
| T1859 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2585088069 |
|
|
Mar 31 12:25:20 PM PDT 24 |
Mar 31 12:25:21 PM PDT 24 |
21752714 ps |
| T1860 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2837207620 |
|
|
Mar 31 12:37:19 PM PDT 24 |
Mar 31 12:37:23 PM PDT 24 |
537449692 ps |
| T1861 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.971889208 |
|
|
Mar 31 12:26:06 PM PDT 24 |
Mar 31 12:26:07 PM PDT 24 |
58850666 ps |
| T1862 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1241727235 |
|
|
Mar 31 12:37:31 PM PDT 24 |
Mar 31 12:37:32 PM PDT 24 |
51668570 ps |
| T1863 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1146424079 |
|
|
Mar 31 12:25:39 PM PDT 24 |
Mar 31 12:25:40 PM PDT 24 |
88121890 ps |
| T1864 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3597330503 |
|
|
Mar 31 12:25:36 PM PDT 24 |
Mar 31 12:25:37 PM PDT 24 |
669553084 ps |
| T1865 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3786637887 |
|
|
Mar 31 12:37:07 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
1654610174 ps |
| T245 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3545594483 |
|
|
Mar 31 12:25:44 PM PDT 24 |
Mar 31 12:25:45 PM PDT 24 |
50010402 ps |
| T1866 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3554199105 |
|
|
Mar 31 12:25:45 PM PDT 24 |
Mar 31 12:25:49 PM PDT 24 |
689027368 ps |
| T1867 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4109277832 |
|
|
Mar 31 12:26:06 PM PDT 24 |
Mar 31 12:26:18 PM PDT 24 |
88878057 ps |
| T1868 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3788454272 |
|
|
Mar 31 12:37:34 PM PDT 24 |
Mar 31 12:37:35 PM PDT 24 |
52615828 ps |
| T1869 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3714769457 |
|
|
Mar 31 12:37:28 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
64202836 ps |
| T1870 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3872916949 |
|
|
Mar 31 12:25:48 PM PDT 24 |
Mar 31 12:25:49 PM PDT 24 |
55402987 ps |
| T1871 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2160765462 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:50 PM PDT 24 |
129441764 ps |
| T1872 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.936478938 |
|
|
Mar 31 12:26:00 PM PDT 24 |
Mar 31 12:26:02 PM PDT 24 |
26259058 ps |
| T1873 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3880125189 |
|
|
Mar 31 12:37:22 PM PDT 24 |
Mar 31 12:37:25 PM PDT 24 |
108171866 ps |
| T1874 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3251503944 |
|
|
Mar 31 12:26:07 PM PDT 24 |
Mar 31 12:26:08 PM PDT 24 |
23105153 ps |
| T1875 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3010126768 |
|
|
Mar 31 12:37:13 PM PDT 24 |
Mar 31 12:37:15 PM PDT 24 |
125847819 ps |
| T1876 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2921658105 |
|
|
Mar 31 12:37:13 PM PDT 24 |
Mar 31 12:37:25 PM PDT 24 |
1958557853 ps |
| T146 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.641354976 |
|
|
Mar 31 12:25:46 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
81860956 ps |
| T1877 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3995073925 |
|
|
Mar 31 12:36:56 PM PDT 24 |
Mar 31 12:37:02 PM PDT 24 |
183302086 ps |
| T247 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1656198325 |
|
|
Mar 31 12:37:22 PM PDT 24 |
Mar 31 12:37:25 PM PDT 24 |
31813383 ps |
| T1878 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.75657457 |
|
|
Mar 31 12:36:44 PM PDT 24 |
Mar 31 12:36:47 PM PDT 24 |
101005471 ps |
| T1879 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.191357540 |
|
|
Mar 31 12:25:46 PM PDT 24 |
Mar 31 12:25:49 PM PDT 24 |
230368924 ps |
| T248 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3280319638 |
|
|
Mar 31 12:37:21 PM PDT 24 |
Mar 31 12:37:25 PM PDT 24 |
351677968 ps |
| T250 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2645453292 |
|
|
Mar 31 12:25:42 PM PDT 24 |
Mar 31 12:25:43 PM PDT 24 |
33618444 ps |
| T1880 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.594892943 |
|
|
Mar 31 12:25:41 PM PDT 24 |
Mar 31 12:25:44 PM PDT 24 |
480169667 ps |
| T1881 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1645948246 |
|
|
Mar 31 12:25:58 PM PDT 24 |
Mar 31 12:26:04 PM PDT 24 |
23294204 ps |
| T1882 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4054281309 |
|
|
Mar 31 12:37:31 PM PDT 24 |
Mar 31 12:37:34 PM PDT 24 |
101274522 ps |
| T1883 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3208313800 |
|
|
Mar 31 12:36:52 PM PDT 24 |
Mar 31 12:36:54 PM PDT 24 |
15691554 ps |
| T1884 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.623523390 |
|
|
Mar 31 12:25:38 PM PDT 24 |
Mar 31 12:25:41 PM PDT 24 |
262949049 ps |
| T1885 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.326511982 |
|
|
Mar 31 12:37:04 PM PDT 24 |
Mar 31 12:37:06 PM PDT 24 |
386262107 ps |
| T1886 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4271704522 |
|
|
Mar 31 12:26:05 PM PDT 24 |
Mar 31 12:26:07 PM PDT 24 |
91584179 ps |
| T1887 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4218736914 |
|
|
Mar 31 12:37:06 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
401799907 ps |
| T1888 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1885920634 |
|
|
Mar 31 12:25:32 PM PDT 24 |
Mar 31 12:25:33 PM PDT 24 |
106507650 ps |
| T1889 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1184056789 |
|
|
Mar 31 12:37:17 PM PDT 24 |
Mar 31 12:37:18 PM PDT 24 |
17597793 ps |
| T1890 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1636503814 |
|
|
Mar 31 12:37:18 PM PDT 24 |
Mar 31 12:37:20 PM PDT 24 |
108102312 ps |
| T1891 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2867660207 |
|
|
Mar 31 12:37:25 PM PDT 24 |
Mar 31 12:37:26 PM PDT 24 |
12809894 ps |
| T1892 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2398975826 |
|
|
Mar 31 12:25:52 PM PDT 24 |
Mar 31 12:25:55 PM PDT 24 |
302452491 ps |
| T1893 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1712461266 |
|
|
Mar 31 12:25:50 PM PDT 24 |
Mar 31 12:25:52 PM PDT 24 |
48483977 ps |
| T1894 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.803304405 |
|
|
Mar 31 12:36:51 PM PDT 24 |
Mar 31 12:36:52 PM PDT 24 |
48340754 ps |
| T1895 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.717695054 |
|
|
Mar 31 12:37:16 PM PDT 24 |
Mar 31 12:37:18 PM PDT 24 |
226985487 ps |
| T1896 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3536356474 |
|
|
Mar 31 12:36:46 PM PDT 24 |
Mar 31 12:37:03 PM PDT 24 |
2694987058 ps |
| T1897 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.483794086 |
|
|
Mar 31 12:26:04 PM PDT 24 |
Mar 31 12:26:05 PM PDT 24 |
31092590 ps |
| T249 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.798352588 |
|
|
Mar 31 12:25:37 PM PDT 24 |
Mar 31 12:25:38 PM PDT 24 |
20546659 ps |
| T1898 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2449221014 |
|
|
Mar 31 12:37:07 PM PDT 24 |
Mar 31 12:37:09 PM PDT 24 |
17887895 ps |
| T251 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3573403231 |
|
|
Mar 31 12:36:47 PM PDT 24 |
Mar 31 12:36:48 PM PDT 24 |
21795488 ps |
| T1899 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2146525294 |
|
|
Mar 31 12:37:25 PM PDT 24 |
Mar 31 12:37:26 PM PDT 24 |
29081915 ps |
| T1900 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.948263463 |
|
|
Mar 31 12:37:17 PM PDT 24 |
Mar 31 12:37:19 PM PDT 24 |
61962930 ps |
| T1901 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2270510253 |
|
|
Mar 31 12:25:50 PM PDT 24 |
Mar 31 12:25:51 PM PDT 24 |
39400548 ps |
| T154 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3356592294 |
|
|
Mar 31 12:37:29 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
44621496 ps |
| T1902 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.485209167 |
|
|
Mar 31 12:37:24 PM PDT 24 |
Mar 31 12:37:26 PM PDT 24 |
229777562 ps |
| T1903 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2692231359 |
|
|
Mar 31 12:25:48 PM PDT 24 |
Mar 31 12:25:49 PM PDT 24 |
20636398 ps |
| T1904 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2638390512 |
|
|
Mar 31 12:25:40 PM PDT 24 |
Mar 31 12:25:42 PM PDT 24 |
94146599 ps |
| T1905 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1412044764 |
|
|
Mar 31 12:25:53 PM PDT 24 |
Mar 31 12:25:56 PM PDT 24 |
305946361 ps |
| T1906 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4209419192 |
|
|
Mar 31 12:36:56 PM PDT 24 |
Mar 31 12:36:57 PM PDT 24 |
58459741 ps |
| T1907 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2479958206 |
|
|
Mar 31 12:25:31 PM PDT 24 |
Mar 31 12:25:33 PM PDT 24 |
216493946 ps |
| T1908 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.182719488 |
|
|
Mar 31 12:25:31 PM PDT 24 |
Mar 31 12:25:33 PM PDT 24 |
612226614 ps |
| T1909 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3781687582 |
|
|
Mar 31 12:37:09 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
14902048 ps |
| T1910 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.855257922 |
|
|
Mar 31 12:26:09 PM PDT 24 |
Mar 31 12:26:12 PM PDT 24 |
106436384 ps |
| T1911 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2412613480 |
|
|
Mar 31 12:25:41 PM PDT 24 |
Mar 31 12:25:46 PM PDT 24 |
224174794 ps |
| T1912 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3579035742 |
|
|
Mar 31 12:26:03 PM PDT 24 |
Mar 31 12:26:23 PM PDT 24 |
3734106794 ps |
| T1913 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4149193654 |
|
|
Mar 31 12:25:45 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
389835678 ps |
| T1914 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.925561295 |
|
|
Mar 31 12:36:48 PM PDT 24 |
Mar 31 12:36:49 PM PDT 24 |
20283171 ps |
| T1915 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.189158490 |
|
|
Mar 31 12:36:48 PM PDT 24 |
Mar 31 12:36:51 PM PDT 24 |
592464165 ps |
| T1916 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2215004717 |
|
|
Mar 31 12:37:09 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
16304653 ps |
| T1917 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1570654681 |
|
|
Mar 31 12:37:24 PM PDT 24 |
Mar 31 12:37:29 PM PDT 24 |
412647258 ps |
| T1918 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1987418563 |
|
|
Mar 31 12:37:24 PM PDT 24 |
Mar 31 12:37:26 PM PDT 24 |
66442289 ps |
| T1919 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.329136462 |
|
|
Mar 31 12:25:59 PM PDT 24 |
Mar 31 12:26:01 PM PDT 24 |
48346331 ps |
| T136 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1883838635 |
|
|
Mar 31 12:26:00 PM PDT 24 |
Mar 31 12:26:02 PM PDT 24 |
141164325 ps |
| T169 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3379034472 |
|
|
Mar 31 12:25:15 PM PDT 24 |
Mar 31 12:25:18 PM PDT 24 |
773612083 ps |
| T159 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4070230664 |
|
|
Mar 31 12:37:21 PM PDT 24 |
Mar 31 12:37:26 PM PDT 24 |
404582730 ps |
| T150 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3717461058 |
|
|
Mar 31 12:25:43 PM PDT 24 |
Mar 31 12:25:46 PM PDT 24 |
549273440 ps |
| T1920 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.726395987 |
|
|
Mar 31 12:37:20 PM PDT 24 |
Mar 31 12:37:22 PM PDT 24 |
43490934 ps |
| T1921 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.69124384 |
|
|
Mar 31 12:25:20 PM PDT 24 |
Mar 31 12:25:22 PM PDT 24 |
27376487 ps |
| T1922 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1680197498 |
|
|
Mar 31 12:25:45 PM PDT 24 |
Mar 31 12:25:45 PM PDT 24 |
169348109 ps |
| T1923 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.313393004 |
|
|
Mar 31 12:37:28 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
173028872 ps |
| T147 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3476380352 |
|
|
Mar 31 12:37:27 PM PDT 24 |
Mar 31 12:37:30 PM PDT 24 |
208276334 ps |
| T168 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.113097167 |
|
|
Mar 31 12:25:51 PM PDT 24 |
Mar 31 12:25:54 PM PDT 24 |
598951058 ps |
| T1924 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.627354415 |
|
|
Mar 31 12:37:07 PM PDT 24 |
Mar 31 12:37:09 PM PDT 24 |
31008031 ps |
| T1925 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1768598583 |
|
|
Mar 31 12:37:07 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
525176295 ps |
| T1926 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1260691089 |
|
|
Mar 31 12:37:16 PM PDT 24 |
Mar 31 12:37:17 PM PDT 24 |
95357476 ps |
| T1927 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.231501928 |
|
|
Mar 31 12:25:53 PM PDT 24 |
Mar 31 12:25:54 PM PDT 24 |
17573530 ps |
| T172 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1946225824 |
|
|
Mar 31 12:36:46 PM PDT 24 |
Mar 31 12:36:50 PM PDT 24 |
115895509 ps |
| T1928 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3771256471 |
|
|
Mar 31 12:36:56 PM PDT 24 |
Mar 31 12:36:58 PM PDT 24 |
27054925 ps |
| T1929 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2390562871 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
19748255 ps |
| T170 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2406765818 |
|
|
Mar 31 12:25:11 PM PDT 24 |
Mar 31 12:25:14 PM PDT 24 |
88002105 ps |
| T1930 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1952704835 |
|
|
Mar 31 12:37:08 PM PDT 24 |
Mar 31 12:37:09 PM PDT 24 |
16004989 ps |
| T1931 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2467322294 |
|
|
Mar 31 12:25:09 PM PDT 24 |
Mar 31 12:25:11 PM PDT 24 |
126926996 ps |
| T1932 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3403858070 |
|
|
Mar 31 12:25:17 PM PDT 24 |
Mar 31 12:26:12 PM PDT 24 |
3727029461 ps |
| T1933 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.470946040 |
|
|
Mar 31 12:37:17 PM PDT 24 |
Mar 31 12:37:19 PM PDT 24 |
79655930 ps |
| T1934 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2201808662 |
|
|
Mar 31 12:37:19 PM PDT 24 |
Mar 31 12:37:22 PM PDT 24 |
84506768 ps |
| T1935 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3760371021 |
|
|
Mar 31 12:25:44 PM PDT 24 |
Mar 31 12:25:45 PM PDT 24 |
16047534 ps |
| T1936 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.404379051 |
|
|
Mar 31 12:37:31 PM PDT 24 |
Mar 31 12:37:33 PM PDT 24 |
37014514 ps |
| T173 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.36826529 |
|
|
Mar 31 12:25:56 PM PDT 24 |
Mar 31 12:25:59 PM PDT 24 |
79893074 ps |
| T1937 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3580789873 |
|
|
Mar 31 12:36:38 PM PDT 24 |
Mar 31 12:36:40 PM PDT 24 |
190252016 ps |
| T1938 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1151966905 |
|
|
Mar 31 12:25:43 PM PDT 24 |
Mar 31 12:26:12 PM PDT 24 |
5347313245 ps |
| T1939 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1890769217 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
176694787 ps |
| T1940 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.123040672 |
|
|
Mar 31 12:26:05 PM PDT 24 |
Mar 31 12:26:06 PM PDT 24 |
33387629 ps |
| T1941 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1399591211 |
|
|
Mar 31 12:26:00 PM PDT 24 |
Mar 31 12:26:03 PM PDT 24 |
1021770007 ps |
| T1942 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2307981397 |
|
|
Mar 31 12:36:56 PM PDT 24 |
Mar 31 12:37:01 PM PDT 24 |
930225747 ps |
| T1943 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.466157035 |
|
|
Mar 31 12:37:16 PM PDT 24 |
Mar 31 12:37:19 PM PDT 24 |
145198818 ps |
| T1944 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1689381331 |
|
|
Mar 31 12:25:40 PM PDT 24 |
Mar 31 12:25:41 PM PDT 24 |
81114814 ps |
| T1945 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3820311983 |
|
|
Mar 31 12:37:34 PM PDT 24 |
Mar 31 12:37:36 PM PDT 24 |
40587091 ps |
| T1946 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3297557612 |
|
|
Mar 31 12:36:46 PM PDT 24 |
Mar 31 12:36:49 PM PDT 24 |
61257204 ps |
| T1947 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1710733701 |
|
|
Mar 31 12:25:41 PM PDT 24 |
Mar 31 12:25:44 PM PDT 24 |
54928133 ps |
| T1948 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4237701230 |
|
|
Mar 31 12:25:35 PM PDT 24 |
Mar 31 12:25:42 PM PDT 24 |
800146100 ps |
| T1949 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2910353588 |
|
|
Mar 31 12:37:28 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
90801384 ps |
| T1950 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.510817695 |
|
|
Mar 31 12:37:07 PM PDT 24 |
Mar 31 12:37:08 PM PDT 24 |
15058052 ps |
| T1951 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3601244427 |
|
|
Mar 31 12:25:42 PM PDT 24 |
Mar 31 12:25:44 PM PDT 24 |
256454595 ps |
| T1952 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1060323142 |
|
|
Mar 31 12:25:38 PM PDT 24 |
Mar 31 12:25:39 PM PDT 24 |
315847846 ps |
| T1953 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3252614839 |
|
|
Mar 31 12:25:34 PM PDT 24 |
Mar 31 12:25:38 PM PDT 24 |
204587450 ps |
| T1954 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.722144117 |
|
|
Mar 31 12:25:41 PM PDT 24 |
Mar 31 12:25:45 PM PDT 24 |
185999406 ps |
| T1955 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3768203097 |
|
|
Mar 31 12:37:25 PM PDT 24 |
Mar 31 12:37:32 PM PDT 24 |
3175401114 ps |
| T1956 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3751971763 |
|
|
Mar 31 12:37:08 PM PDT 24 |
Mar 31 12:37:09 PM PDT 24 |
17827380 ps |
| T1957 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2209834196 |
|
|
Mar 31 12:25:38 PM PDT 24 |
Mar 31 12:25:44 PM PDT 24 |
477674801 ps |
| T1958 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2271707750 |
|
|
Mar 31 12:36:57 PM PDT 24 |
Mar 31 12:36:59 PM PDT 24 |
37926704 ps |
| T1959 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2789140640 |
|
|
Mar 31 12:25:50 PM PDT 24 |
Mar 31 12:25:52 PM PDT 24 |
31112541 ps |
| T1960 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.969490393 |
|
|
Mar 31 12:25:45 PM PDT 24 |
Mar 31 12:25:46 PM PDT 24 |
254864414 ps |
| T1961 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.21637225 |
|
|
Mar 31 12:37:11 PM PDT 24 |
Mar 31 12:37:14 PM PDT 24 |
221459967 ps |
| T1962 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3449127021 |
|
|
Mar 31 12:37:25 PM PDT 24 |
Mar 31 12:37:26 PM PDT 24 |
16565046 ps |
| T1963 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2654468825 |
|
|
Mar 31 12:37:16 PM PDT 24 |
Mar 31 12:37:18 PM PDT 24 |
63453324 ps |
| T1964 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.713649156 |
|
|
Mar 31 12:37:08 PM PDT 24 |
Mar 31 12:37:09 PM PDT 24 |
79506324 ps |
| T1965 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3673604520 |
|
|
Mar 31 12:36:56 PM PDT 24 |
Mar 31 12:36:57 PM PDT 24 |
54260631 ps |
| T1966 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3466707358 |
|
|
Mar 31 12:37:08 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
127619869 ps |
| T1967 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3030776982 |
|
|
Mar 31 12:25:44 PM PDT 24 |
Mar 31 12:25:47 PM PDT 24 |
76685499 ps |
| T1968 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3625471362 |
|
|
Mar 31 12:25:46 PM PDT 24 |
Mar 31 12:25:47 PM PDT 24 |
24228372 ps |
| T1969 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3337521032 |
|
|
Mar 31 12:25:56 PM PDT 24 |
Mar 31 12:26:18 PM PDT 24 |
3611635354 ps |
| T1970 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3901029187 |
|
|
Mar 31 12:37:23 PM PDT 24 |
Mar 31 12:37:45 PM PDT 24 |
5356480597 ps |
| T1971 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3133362027 |
|
|
Mar 31 12:37:04 PM PDT 24 |
Mar 31 12:37:05 PM PDT 24 |
18602371 ps |
| T1972 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1789974519 |
|
|
Mar 31 12:25:38 PM PDT 24 |
Mar 31 12:25:40 PM PDT 24 |
38464955 ps |
| T1973 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.328987105 |
|
|
Mar 31 12:25:48 PM PDT 24 |
Mar 31 12:25:49 PM PDT 24 |
24581007 ps |
| T1974 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3215860079 |
|
|
Mar 31 12:25:48 PM PDT 24 |
Mar 31 12:25:50 PM PDT 24 |
89752053 ps |
| T1975 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1145752730 |
|
|
Mar 31 12:25:56 PM PDT 24 |
Mar 31 12:25:58 PM PDT 24 |
95209521 ps |
| T1976 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1078732214 |
|
|
Mar 31 12:37:05 PM PDT 24 |
Mar 31 12:37:07 PM PDT 24 |
21814642 ps |
| T1977 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.43665279 |
|
|
Mar 31 12:37:29 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
31731120 ps |
| T1978 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3329967368 |
|
|
Mar 31 12:37:06 PM PDT 24 |
Mar 31 12:37:08 PM PDT 24 |
198436375 ps |
| T1979 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.404276728 |
|
|
Mar 31 12:38:02 PM PDT 24 |
Mar 31 12:38:03 PM PDT 24 |
42504067 ps |
| T1980 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3942509831 |
|
|
Mar 31 12:37:04 PM PDT 24 |
Mar 31 12:37:05 PM PDT 24 |
15427806 ps |
| T1981 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2164986647 |
|
|
Mar 31 12:36:57 PM PDT 24 |
Mar 31 12:36:58 PM PDT 24 |
129638857 ps |
| T1982 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4122338757 |
|
|
Mar 31 12:37:23 PM PDT 24 |
Mar 31 12:37:26 PM PDT 24 |
133456256 ps |
| T1983 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1055368356 |
|
|
Mar 31 12:37:16 PM PDT 24 |
Mar 31 12:37:18 PM PDT 24 |
424863434 ps |
| T1984 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.187631496 |
|
|
Mar 31 12:25:28 PM PDT 24 |
Mar 31 12:25:29 PM PDT 24 |
125762654 ps |
| T1985 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2223052691 |
|
|
Mar 31 12:25:59 PM PDT 24 |
Mar 31 12:26:01 PM PDT 24 |
167833243 ps |
| T1986 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1473999443 |
|
|
Mar 31 12:25:12 PM PDT 24 |
Mar 31 12:25:13 PM PDT 24 |
45127834 ps |
| T1987 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4213566207 |
|
|
Mar 31 12:37:15 PM PDT 24 |
Mar 31 12:37:16 PM PDT 24 |
25396952 ps |
| T1988 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.14664511 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
53904320 ps |
| T1989 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.961360494 |
|
|
Mar 31 12:37:03 PM PDT 24 |
Mar 31 12:37:05 PM PDT 24 |
118798733 ps |
| T1990 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1363431261 |
|
|
Mar 31 12:37:22 PM PDT 24 |
Mar 31 12:37:25 PM PDT 24 |
31793454 ps |
| T1991 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3635649501 |
|
|
Mar 31 12:37:32 PM PDT 24 |
Mar 31 12:37:39 PM PDT 24 |
14466228 ps |
| T156 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3728747853 |
|
|
Mar 31 12:37:14 PM PDT 24 |
Mar 31 12:37:18 PM PDT 24 |
420925566 ps |
| T1992 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2641104127 |
|
|
Mar 31 12:37:09 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
26219185 ps |
| T1993 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1683771733 |
|
|
Mar 31 12:37:13 PM PDT 24 |
Mar 31 12:37:14 PM PDT 24 |
84044676 ps |
| T1994 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3434007766 |
|
|
Mar 31 12:37:30 PM PDT 24 |
Mar 31 12:37:32 PM PDT 24 |
62994746 ps |
| T1995 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2303061445 |
|
|
Mar 31 12:25:13 PM PDT 24 |
Mar 31 12:25:15 PM PDT 24 |
125094014 ps |
| T1996 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3281475911 |
|
|
Mar 31 12:37:28 PM PDT 24 |
Mar 31 12:37:31 PM PDT 24 |
151324041 ps |
| T1997 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.604257777 |
|
|
Mar 31 12:25:53 PM PDT 24 |
Mar 31 12:25:54 PM PDT 24 |
23207008 ps |
| T1998 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.218797500 |
|
|
Mar 31 12:37:24 PM PDT 24 |
Mar 31 12:37:27 PM PDT 24 |
222579615 ps |
| T167 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.714778858 |
|
|
Mar 31 12:25:54 PM PDT 24 |
Mar 31 12:25:57 PM PDT 24 |
94578326 ps |
| T1999 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3104636445 |
|
|
Mar 31 12:37:04 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
255999392 ps |
| T2000 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.38013291 |
|
|
Mar 31 12:26:00 PM PDT 24 |
Mar 31 12:26:01 PM PDT 24 |
44233011 ps |
| T2001 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3986336517 |
|
|
Mar 31 12:25:54 PM PDT 24 |
Mar 31 12:26:07 PM PDT 24 |
46921247 ps |