Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115773277

1

T1

645606

T2

48991

T3

14295

auto[1]

1412767

1

T1

2749

T2

1176

T3

7231

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115774122

1

T1

646100

T2

49579

T3

14408

auto[1]

1411922

1

T1

2255

T2

588

T3

7118

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7459932	1			T1	36721		T2	1622		T3	6113
auto[IdleSt]	25637048	1			T1	77349		T2	25167		T3	2191
auto[ClkMuxSt]	37954	1			T1	70		T2	18		T3	64
auto[CntIncrSt]	37648	1			T1	66		T2	18		T3	63
auto[CntProgSt]	1661919	1			T1	132		T2	2131		T3	1242
auto[TransCheckSt]	29190	1			T1	61		T3	32		T8	25
auto[TokenHashSt]	49445129	1			T1	412072		T3	759		T8	361
auto[FlashRmaSt]	30884	1			T1	156		T3	75		T8	45
auto[TokenCheck0St]	13487	1			T1	61		T3	22		T8	17
auto[TokenCheck1St]	10159	1			T1	61		T3	22		T8	17
auto[TransProgSt]	464220	1			T1	122		T3	91		T8	36
auto[PostTransSt]	14405688	1			T1	12780		T2	11989		T3	11
auto[ScrapSt]	275313	1			T1	452		T3	6		T8	3
auto[EscalateSt]	6927364	1			T1	24811		T2	9222		T3	10835
auto[InvalidSt]	10748153	1			T1	83432		T14	1220		T15	380

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1956	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10748153	1			T1	83432		T14	1220		T15	380
EscalateSt	6927364	1			T1	24811		T2	9222		T3	10835
ScrapSt	275313	1			T1	452		T3	6		T8	3
PostTransSt	14405688	1			T1	12780		T2	11989		T3	11
TransProgSt	464220	1			T1	122		T3	91		T8	36
TokenCheck1St	10159	1			T1	61		T3	22		T8	17
TokenCheck0St	13487	1			T1	61		T3	22		T8	17
FlashRmaSt	30884	1			T1	156		T3	75		T8	45
TokenHashSt	49445129	1			T1	412072		T3	759		T8	361
TransCheckSt	29190	1			T1	61		T3	32		T8	25
CntProgSt	1661919	1			T1	132		T2	2131		T3	1242
CntIncrSt	37648	1			T1	66		T2	18		T3	63
ClkMuxSt	37954	1			T1	70		T2	18		T3	64
IdleSt	25637048	1			T1	77349		T2	25167		T3	2191
ResetSt	7459932	1			T1	36721		T2	1622		T3	6113
arcs[ResetSt=>IdleSt]	57061	1			T1	125		T2	19		T3	67
arcs[IdleSt=>ScrapSt]	354	1			T1	2		T3	2		T8	1
arcs[IdleSt=>ClkMuxSt]	37733	1			T1	66		T2	18		T3	64
arcs[ClkMuxSt=>CntIncrSt]	37648	1			T1	66		T2	18		T3	63
arcs[CntIncrSt=>PostTransSt]	1821	1			T30	16		T18	7		T36	3
arcs[CntIncrSt=>CntProgSt]	35759	1			T1	66		T2	18		T3	63
arcs[CntProgSt=>PostTransSt]	5403	1			T1	5		T2	18		T4	7
arcs[CntProgSt=>TransCheckSt]	29190	1			T1	61		T3	32		T8	25
arcs[TransCheckSt=>PostTransSt]	4037	1			T10	36		T30	11		T18	4
arcs[TransCheckSt=>TokenHashSt]	25055	1			T1	61		T3	31		T8	25
arcs[TokenHashSt=>PostTransSt]	10831	1			T10	5		T30	22		T18	17
arcs[TokenHashSt=>FlashRmaSt]	13564	1			T1	61		T3	23		T8	17
arcs[FlashRmaSt=>TokenCheck0St]	13487	1			T1	61		T3	22		T8	17
arcs[TokenCheck0St=>PostTransSt]	3307	1			T10	5		T30	11		T18	10
arcs[TokenCheck0St=>TokenCheck1St]	10159	1			T1	61		T3	22		T8	17
arcs[TokenCheck1St=>PostTransSt]	662	1			T10	7		T30	3		T18	2
arcs[TransProgSt=>PostTransSt]	8598	1			T1	61		T3	4		T8	2
arcs[IdleSt=>EscalateSt]	171	1			T8	6		T40	7		T52	3
arcs[ClkMuxSt=>EscalateSt]	85	1			T3	1		T8	1		T40	1
arcs[CntIncrSt=>EscalateSt]	68	1			T40	2		T51	1		T52	3
arcs[CntProgSt=>EscalateSt]	1166	1			T3	31		T8	14		T40	15
arcs[TransCheckSt=>EscalateSt]	98	1			T3	1		T51	9		T58	3
arcs[TokenHashSt=>EscalateSt]	660	1			T3	8		T8	8		T40	4
arcs[FlashRmaSt=>EscalateSt]	77	1			T3	1		T38	2		T53	3
arcs[TokenCheck0St=>EscalateSt]	21	1			T51	2		T56	1		T57	1
arcs[TokenCheck1St=>EscalateSt]	127	1			T3	3		T8	1		T40	2
arcs[TransProgSt=>EscalateSt]	772	1			T3	15		T8	14		T40	14
arcs[PostTransSt=>EscalateSt]	5627	1			T1	5		T2	18		T3	4
arcs[InvalidSt=>EscalateSt]	13890	1			T1	46		T14	8		T15	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7459756	1			T1	36721		T2	1622		T3	6112
auto[0]	auto[IdleSt]	25636941	1			T1	77349		T2	25167		T3	2191
auto[0]	auto[ClkMuxSt]	37897	1			T1	70		T2	18		T3	63
auto[0]	auto[CntIncrSt]	37607	1			T1	66		T2	18		T3	63
auto[0]	auto[CntProgSt]	1661134	1			T1	132		T2	2131		T3	1219
auto[0]	auto[TransCheckSt]	29127	1			T1	61		T3	31		T8	25
auto[0]	auto[TokenHashSt]	49444686	1			T1	412072		T3	755		T8	358
auto[0]	auto[FlashRmaSt]	30840	1			T1	156		T3	75		T8	45
auto[0]	auto[TokenCheck0St]	13474	1			T1	61		T3	22		T8	17
auto[0]	auto[TokenCheck1St]	10082	1			T1	61		T3	20		T8	17
auto[0]	auto[TransProgSt]	463713	1			T1	122		T3	82		T8	25
auto[0]	auto[PostTransSt]	14402808	1			T1	12776		T2	11977		T3	7
auto[0]	auto[ScrapSt]	275256	1			T1	452		T3	5		T8	2
auto[0]	auto[EscalateSt]	5526801	1			T1	22090		T2	8058		T3	3650
auto[0]	auto[InvalidSt]	10741199	1			T1	83408		T14	1217		T15	379
auto[1]	auto[ResetSt]	176	1			T3	1		T8	3		T40	4
auto[1]	auto[IdleSt]	107	1			T8	5		T40	5		T52	1
auto[1]	auto[ClkMuxSt]	57	1			T3	1		T40	1		T52	2
auto[1]	auto[CntIncrSt]	41	1			T40	1		T51	1		T52	2
auto[1]	auto[CntProgSt]	785	1			T3	23		T8	8		T40	10
auto[1]	auto[TransCheckSt]	63	1			T3	1		T51	7		T58	2
auto[1]	auto[TokenHashSt]	443	1			T3	4		T8	3		T40	3
auto[1]	auto[FlashRmaSt]	44	1			T38	1		T249	1		T250	1
auto[1]	auto[TokenCheck0St]	13	1			T51	1		T56	1		T251	1
auto[1]	auto[TokenCheck1St]	77	1			T3	2		T40	1		T51	2
auto[1]	auto[TransProgSt]	507	1			T3	9		T8	11		T40	9
auto[1]	auto[PostTransSt]	2880	1			T1	4		T2	12		T3	4
auto[1]	auto[ScrapSt]	57	1			T3	1		T8	1		T40	2
auto[1]	auto[EscalateSt]	1400563	1			T1	2721		T2	1164		T3	7185
auto[1]	auto[InvalidSt]	6954	1			T1	24		T14	3		T15	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7459764	1			T1	36721		T2	1622		T3	6111
auto[0]	auto[IdleSt]	25636928	1			T1	77349		T2	25167		T3	2191
auto[0]	auto[ClkMuxSt]	37898	1			T1	70		T2	18		T3	64
auto[0]	auto[CntIncrSt]	37594	1			T1	66		T2	18		T3	63
auto[0]	auto[CntProgSt]	1661121	1			T1	132		T2	2131		T3	1226
auto[0]	auto[TransCheckSt]	29122	1			T1	61		T3	31		T8	25
auto[0]	auto[TokenHashSt]	49444687	1			T1	412072		T3	751		T8	354
auto[0]	auto[FlashRmaSt]	30829	1			T1	156		T3	74		T8	45
auto[0]	auto[TokenCheck0St]	13472	1			T1	61		T3	22		T8	17
auto[0]	auto[TokenCheck1St]	10067	1			T1	61		T3	19		T8	16
auto[0]	auto[TransProgSt]	463715	1			T1	122		T3	80		T8	28
auto[0]	auto[PostTransSt]	14402870	1			T1	12779		T2	11983		T3	9
auto[0]	auto[ScrapSt]	275266	1			T1	452		T3	4		T8	3
auto[0]	auto[EscalateSt]	5527616	1			T1	22579		T2	8640		T3	3763
auto[0]	auto[InvalidSt]	10741217	1			T1	83410		T14	1215		T15	376
auto[1]	auto[ResetSt]	168	1			T3	2		T8	2		T40	3
auto[1]	auto[IdleSt]	120	1			T8	3		T40	6		T52	2
auto[1]	auto[ClkMuxSt]	56	1			T8	1		T51	1		T52	1
auto[1]	auto[CntIncrSt]	54	1			T40	1		T51	1		T52	1
auto[1]	auto[CntProgSt]	798	1			T3	16		T8	9		T40	6
auto[1]	auto[TransCheckSt]	68	1			T3	1		T51	6		T58	2
auto[1]	auto[TokenHashSt]	442	1			T3	8		T8	7		T40	2
auto[1]	auto[FlashRmaSt]	55	1			T3	1		T38	1		T53	3
auto[1]	auto[TokenCheck0St]	15	1			T51	2		T57	1		T251	2
auto[1]	auto[TokenCheck1St]	92	1			T3	3		T8	1		T40	2
auto[1]	auto[TransProgSt]	505	1			T3	11		T8	8		T40	10
auto[1]	auto[PostTransSt]	2818	1			T1	1		T2	6		T3	2
auto[1]	auto[ScrapSt]	47	1			T3	2		T40	1		T53	1
auto[1]	auto[EscalateSt]	1399748	1			T1	2232		T2	582		T3	7072
auto[1]	auto[InvalidSt]	6936	1			T1	22		T14	5		T15	4