| T839 |
/workspace/coverage/default/21.lc_ctrl_prog_failure.2248070612 |
|
|
Apr 02 01:49:33 PM PDT 24 |
Apr 02 01:49:36 PM PDT 24 |
54014829 ps |
| T840 |
/workspace/coverage/default/36.lc_ctrl_jtag_access.2557003889 |
|
|
Apr 02 01:50:28 PM PDT 24 |
Apr 02 01:50:38 PM PDT 24 |
1986997802 ps |
| T841 |
/workspace/coverage/default/36.lc_ctrl_sec_token_digest.4169722111 |
|
|
Apr 02 01:50:26 PM PDT 24 |
Apr 02 01:50:42 PM PDT 24 |
479659155 ps |
| T842 |
/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3725312022 |
|
|
Apr 02 01:48:13 PM PDT 24 |
Apr 02 01:48:49 PM PDT 24 |
751032141 ps |
| T843 |
/workspace/coverage/default/7.lc_ctrl_jtag_errors.266102878 |
|
|
Apr 02 01:48:24 PM PDT 24 |
Apr 02 01:49:06 PM PDT 24 |
1289735298 ps |
| T844 |
/workspace/coverage/default/27.lc_ctrl_errors.1273580312 |
|
|
Apr 02 01:49:54 PM PDT 24 |
Apr 02 01:50:06 PM PDT 24 |
270573025 ps |
| T845 |
/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1589475739 |
|
|
Apr 02 01:48:19 PM PDT 24 |
Apr 02 01:48:34 PM PDT 24 |
915557841 ps |
| T846 |
/workspace/coverage/default/25.lc_ctrl_smoke.323972883 |
|
|
Apr 02 01:49:46 PM PDT 24 |
Apr 02 01:49:51 PM PDT 24 |
212737533 ps |
| T847 |
/workspace/coverage/default/2.lc_ctrl_alert_test.1813713323 |
|
|
Apr 02 01:48:01 PM PDT 24 |
Apr 02 01:48:02 PM PDT 24 |
30338393 ps |
| T848 |
/workspace/coverage/default/26.lc_ctrl_prog_failure.2095555581 |
|
|
Apr 02 01:49:49 PM PDT 24 |
Apr 02 01:49:51 PM PDT 24 |
148328913 ps |
| T86 |
/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3082949002 |
|
|
Apr 02 01:49:40 PM PDT 24 |
Apr 02 01:49:41 PM PDT 24 |
43438017 ps |
| T849 |
/workspace/coverage/default/9.lc_ctrl_security_escalation.1702766842 |
|
|
Apr 02 01:48:37 PM PDT 24 |
Apr 02 01:48:44 PM PDT 24 |
477798583 ps |
| T850 |
/workspace/coverage/default/38.lc_ctrl_security_escalation.3135733387 |
|
|
Apr 02 01:50:36 PM PDT 24 |
Apr 02 01:50:46 PM PDT 24 |
340519286 ps |
| T851 |
/workspace/coverage/default/48.lc_ctrl_stress_all.1850552529 |
|
|
Apr 02 01:51:12 PM PDT 24 |
Apr 02 01:51:48 PM PDT 24 |
13057478270 ps |
| T852 |
/workspace/coverage/default/4.lc_ctrl_stress_all.1911545867 |
|
|
Apr 02 01:48:10 PM PDT 24 |
Apr 02 01:49:58 PM PDT 24 |
4847839737 ps |
| T853 |
/workspace/coverage/default/30.lc_ctrl_smoke.253390529 |
|
|
Apr 02 01:50:10 PM PDT 24 |
Apr 02 01:50:12 PM PDT 24 |
15498619 ps |
| T854 |
/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3224083500 |
|
|
Apr 02 01:49:15 PM PDT 24 |
Apr 02 01:49:20 PM PDT 24 |
134051621 ps |
| T855 |
/workspace/coverage/default/6.lc_ctrl_jtag_access.2757851604 |
|
|
Apr 02 01:48:22 PM PDT 24 |
Apr 02 01:48:24 PM PDT 24 |
860329491 ps |
| T856 |
/workspace/coverage/default/18.lc_ctrl_jtag_access.1155022988 |
|
|
Apr 02 01:49:19 PM PDT 24 |
Apr 02 01:49:25 PM PDT 24 |
1342759765 ps |
| T857 |
/workspace/coverage/default/7.lc_ctrl_stress_all.3116752489 |
|
|
Apr 02 01:48:29 PM PDT 24 |
Apr 02 01:49:29 PM PDT 24 |
2709790913 ps |
| T858 |
/workspace/coverage/default/4.lc_ctrl_regwen_during_op.1156237701 |
|
|
Apr 02 01:48:10 PM PDT 24 |
Apr 02 01:48:23 PM PDT 24 |
1275220046 ps |
| T859 |
/workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3141104471 |
|
|
Apr 02 01:48:54 PM PDT 24 |
Apr 02 02:04:25 PM PDT 24 |
119688134136 ps |
| T860 |
/workspace/coverage/default/30.lc_ctrl_stress_all.2242907276 |
|
|
Apr 02 01:50:10 PM PDT 24 |
Apr 02 01:50:57 PM PDT 24 |
2088780943 ps |
| T861 |
/workspace/coverage/default/27.lc_ctrl_sec_token_mux.1401224654 |
|
|
Apr 02 01:49:54 PM PDT 24 |
Apr 02 01:50:03 PM PDT 24 |
236226125 ps |
| T862 |
/workspace/coverage/default/13.lc_ctrl_security_escalation.2545299657 |
|
|
Apr 02 01:48:58 PM PDT 24 |
Apr 02 01:49:07 PM PDT 24 |
475896670 ps |
| T863 |
/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3186329607 |
|
|
Apr 02 01:50:16 PM PDT 24 |
Apr 02 01:50:17 PM PDT 24 |
23289339 ps |
| T864 |
/workspace/coverage/default/10.lc_ctrl_errors.2107762939 |
|
|
Apr 02 01:48:42 PM PDT 24 |
Apr 02 01:48:54 PM PDT 24 |
1075179471 ps |
| T865 |
/workspace/coverage/default/20.lc_ctrl_errors.3629142449 |
|
|
Apr 02 01:49:30 PM PDT 24 |
Apr 02 01:49:47 PM PDT 24 |
1437486794 ps |
| T866 |
/workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.724342839 |
|
|
Apr 02 01:50:46 PM PDT 24 |
Apr 02 02:13:05 PM PDT 24 |
43361327036 ps |
| T867 |
/workspace/coverage/default/47.lc_ctrl_security_escalation.1163950656 |
|
|
Apr 02 01:51:09 PM PDT 24 |
Apr 02 01:51:22 PM PDT 24 |
353254330 ps |
| T868 |
/workspace/coverage/default/19.lc_ctrl_alert_test.2248542088 |
|
|
Apr 02 01:49:28 PM PDT 24 |
Apr 02 01:49:30 PM PDT 24 |
21840995 ps |
| T869 |
/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1274376847 |
|
|
Apr 02 01:47:50 PM PDT 24 |
Apr 02 01:48:04 PM PDT 24 |
4813278213 ps |
| T870 |
/workspace/coverage/default/43.lc_ctrl_sec_token_mux.3194108151 |
|
|
Apr 02 01:50:53 PM PDT 24 |
Apr 02 01:51:05 PM PDT 24 |
1572971888 ps |
| T176 |
/workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1436653247 |
|
|
Apr 02 01:50:13 PM PDT 24 |
Apr 02 01:54:41 PM PDT 24 |
15179346405 ps |
| T871 |
/workspace/coverage/default/29.lc_ctrl_security_escalation.2553705998 |
|
|
Apr 02 01:50:09 PM PDT 24 |
Apr 02 01:50:24 PM PDT 24 |
3831865428 ps |
| T872 |
/workspace/coverage/default/48.lc_ctrl_state_failure.814559721 |
|
|
Apr 02 01:51:10 PM PDT 24 |
Apr 02 01:51:41 PM PDT 24 |
613838567 ps |
| T873 |
/workspace/coverage/default/11.lc_ctrl_sec_mubi.3048270141 |
|
|
Apr 02 01:48:49 PM PDT 24 |
Apr 02 01:49:03 PM PDT 24 |
1225417082 ps |
| T874 |
/workspace/coverage/default/43.lc_ctrl_state_failure.2218890575 |
|
|
Apr 02 01:50:51 PM PDT 24 |
Apr 02 01:51:20 PM PDT 24 |
212578854 ps |
| T875 |
/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3301422024 |
|
|
Apr 02 01:48:00 PM PDT 24 |
Apr 02 01:49:15 PM PDT 24 |
2149017933 ps |
| T876 |
/workspace/coverage/default/3.lc_ctrl_state_failure.3312178553 |
|
|
Apr 02 01:48:03 PM PDT 24 |
Apr 02 01:48:24 PM PDT 24 |
734753537 ps |
| T877 |
/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1845991301 |
|
|
Apr 02 01:48:37 PM PDT 24 |
Apr 02 01:48:43 PM PDT 24 |
510853906 ps |
| T878 |
/workspace/coverage/default/42.lc_ctrl_sec_mubi.479222994 |
|
|
Apr 02 01:50:48 PM PDT 24 |
Apr 02 01:50:55 PM PDT 24 |
1733047999 ps |
| T177 |
/workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1447049459 |
|
|
Apr 02 01:48:42 PM PDT 24 |
Apr 02 01:58:37 PM PDT 24 |
57556881439 ps |
| T879 |
/workspace/coverage/default/7.lc_ctrl_prog_failure.2041694597 |
|
|
Apr 02 01:48:19 PM PDT 24 |
Apr 02 01:48:22 PM PDT 24 |
130697801 ps |
| T880 |
/workspace/coverage/default/11.lc_ctrl_security_escalation.2610026784 |
|
|
Apr 02 01:48:47 PM PDT 24 |
Apr 02 01:48:59 PM PDT 24 |
2831975972 ps |
| T881 |
/workspace/coverage/default/3.lc_ctrl_jtag_access.213699896 |
|
|
Apr 02 01:48:03 PM PDT 24 |
Apr 02 01:48:08 PM PDT 24 |
2514615086 ps |
| T882 |
/workspace/coverage/default/12.lc_ctrl_jtag_smoke.491335224 |
|
|
Apr 02 01:48:55 PM PDT 24 |
Apr 02 01:49:02 PM PDT 24 |
5473004294 ps |
| T883 |
/workspace/coverage/default/16.lc_ctrl_jtag_errors.1395319680 |
|
|
Apr 02 01:49:13 PM PDT 24 |
Apr 02 01:49:47 PM PDT 24 |
2139410707 ps |
| T884 |
/workspace/coverage/default/11.lc_ctrl_sec_token_digest.636166190 |
|
|
Apr 02 01:48:48 PM PDT 24 |
Apr 02 01:48:57 PM PDT 24 |
1065475398 ps |
| T885 |
/workspace/coverage/default/40.lc_ctrl_sec_mubi.2878688054 |
|
|
Apr 02 01:50:42 PM PDT 24 |
Apr 02 01:50:54 PM PDT 24 |
1015621524 ps |
| T886 |
/workspace/coverage/default/34.lc_ctrl_sec_token_mux.4116606514 |
|
|
Apr 02 01:50:20 PM PDT 24 |
Apr 02 01:50:34 PM PDT 24 |
375412064 ps |
| T887 |
/workspace/coverage/default/19.lc_ctrl_prog_failure.896924531 |
|
|
Apr 02 01:49:22 PM PDT 24 |
Apr 02 01:49:25 PM PDT 24 |
67225532 ps |
| T888 |
/workspace/coverage/default/27.lc_ctrl_state_post_trans.2283103798 |
|
|
Apr 02 01:49:53 PM PDT 24 |
Apr 02 01:50:00 PM PDT 24 |
67920484 ps |
| T889 |
/workspace/coverage/default/0.lc_ctrl_jtag_smoke.2988420908 |
|
|
Apr 02 01:47:52 PM PDT 24 |
Apr 02 01:48:00 PM PDT 24 |
230163191 ps |
| T890 |
/workspace/coverage/default/22.lc_ctrl_smoke.902945768 |
|
|
Apr 02 01:49:38 PM PDT 24 |
Apr 02 01:49:39 PM PDT 24 |
42773055 ps |
| T891 |
/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3207770125 |
|
|
Apr 02 01:48:37 PM PDT 24 |
Apr 02 01:49:02 PM PDT 24 |
3995206218 ps |
| T892 |
/workspace/coverage/default/29.lc_ctrl_sec_token_digest.1274905510 |
|
|
Apr 02 01:50:04 PM PDT 24 |
Apr 02 01:50:18 PM PDT 24 |
330926335 ps |
| T893 |
/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1556046657 |
|
|
Apr 02 01:49:55 PM PDT 24 |
Apr 02 01:49:55 PM PDT 24 |
106481882 ps |
| T894 |
/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2238305781 |
|
|
Apr 02 01:50:21 PM PDT 24 |
Apr 02 01:50:22 PM PDT 24 |
38643433 ps |
| T895 |
/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2957254928 |
|
|
Apr 02 01:51:02 PM PDT 24 |
Apr 02 01:51:03 PM PDT 24 |
27611904 ps |
| T896 |
/workspace/coverage/default/5.lc_ctrl_jtag_errors.2038910682 |
|
|
Apr 02 01:48:14 PM PDT 24 |
Apr 02 01:48:52 PM PDT 24 |
4407899072 ps |
| T897 |
/workspace/coverage/default/17.lc_ctrl_jtag_errors.1082400925 |
|
|
Apr 02 01:49:15 PM PDT 24 |
Apr 02 01:50:14 PM PDT 24 |
1983602702 ps |
| T898 |
/workspace/coverage/default/33.lc_ctrl_errors.3018810649 |
|
|
Apr 02 01:50:21 PM PDT 24 |
Apr 02 01:50:39 PM PDT 24 |
753369641 ps |
| T899 |
/workspace/coverage/default/6.lc_ctrl_claim_transition_if.4134380052 |
|
|
Apr 02 01:48:19 PM PDT 24 |
Apr 02 01:48:20 PM PDT 24 |
14083808 ps |
| T78 |
/workspace/coverage/default/13.lc_ctrl_smoke.4012274871 |
|
|
Apr 02 01:48:52 PM PDT 24 |
Apr 02 01:48:55 PM PDT 24 |
46113391 ps |
| T900 |
/workspace/coverage/default/47.lc_ctrl_prog_failure.264216182 |
|
|
Apr 02 01:51:05 PM PDT 24 |
Apr 02 01:51:07 PM PDT 24 |
47416582 ps |
| T901 |
/workspace/coverage/default/23.lc_ctrl_errors.378595851 |
|
|
Apr 02 01:49:40 PM PDT 24 |
Apr 02 01:49:50 PM PDT 24 |
392048041 ps |
| T902 |
/workspace/coverage/default/14.lc_ctrl_jtag_access.1275937346 |
|
|
Apr 02 01:48:59 PM PDT 24 |
Apr 02 01:49:05 PM PDT 24 |
147981578 ps |
| T903 |
/workspace/coverage/default/30.lc_ctrl_sec_mubi.2079287285 |
|
|
Apr 02 01:50:06 PM PDT 24 |
Apr 02 01:50:18 PM PDT 24 |
533188441 ps |
| T904 |
/workspace/coverage/default/34.lc_ctrl_state_failure.4200529786 |
|
|
Apr 02 01:50:23 PM PDT 24 |
Apr 02 01:50:46 PM PDT 24 |
730516412 ps |
| T116 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3252040253 |
|
|
Apr 02 12:33:34 PM PDT 24 |
Apr 02 12:33:36 PM PDT 24 |
107101472 ps |
| T122 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3044783953 |
|
|
Apr 02 12:32:54 PM PDT 24 |
Apr 02 12:32:57 PM PDT 24 |
350532017 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.41733264 |
|
|
Apr 02 12:40:26 PM PDT 24 |
Apr 02 12:40:34 PM PDT 24 |
47808151 ps |
| T117 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3477393782 |
|
|
Apr 02 12:32:55 PM PDT 24 |
Apr 02 12:32:57 PM PDT 24 |
70559933 ps |
| T110 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2214644023 |
|
|
Apr 02 12:32:57 PM PDT 24 |
Apr 02 12:33:01 PM PDT 24 |
238503138 ps |
| T230 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3380839263 |
|
|
Apr 02 12:33:19 PM PDT 24 |
Apr 02 12:33:21 PM PDT 24 |
25755841 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3437871984 |
|
|
Apr 02 12:39:55 PM PDT 24 |
Apr 02 12:39:57 PM PDT 24 |
134612556 ps |
| T178 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3657020684 |
|
|
Apr 02 12:40:04 PM PDT 24 |
Apr 02 12:40:06 PM PDT 24 |
60136768 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.975029130 |
|
|
Apr 02 12:40:22 PM PDT 24 |
Apr 02 12:40:24 PM PDT 24 |
330225383 ps |
| T109 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3570699416 |
|
|
Apr 02 12:40:19 PM PDT 24 |
Apr 02 12:40:22 PM PDT 24 |
224860242 ps |
| T905 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1650466481 |
|
|
Apr 02 12:40:02 PM PDT 24 |
Apr 02 12:40:03 PM PDT 24 |
51556113 ps |
| T212 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4238578646 |
|
|
Apr 02 12:32:53 PM PDT 24 |
Apr 02 12:32:54 PM PDT 24 |
74692497 ps |
| T906 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.171028519 |
|
|
Apr 02 12:40:24 PM PDT 24 |
Apr 02 12:40:26 PM PDT 24 |
28167255 ps |
| T162 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4023719967 |
|
|
Apr 02 12:39:58 PM PDT 24 |
Apr 02 12:40:02 PM PDT 24 |
804817964 ps |
| T907 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1635315202 |
|
|
Apr 02 12:33:20 PM PDT 24 |
Apr 02 12:33:27 PM PDT 24 |
1699091827 ps |
| T138 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.58163481 |
|
|
Apr 02 12:33:13 PM PDT 24 |
Apr 02 12:33:16 PM PDT 24 |
420932886 ps |
| T231 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.176190923 |
|
|
Apr 02 12:40:00 PM PDT 24 |
Apr 02 12:40:02 PM PDT 24 |
25948727 ps |
| T232 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2663384676 |
|
|
Apr 02 12:40:07 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
54025691 ps |
| T111 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3630952356 |
|
|
Apr 02 12:33:19 PM PDT 24 |
Apr 02 12:33:21 PM PDT 24 |
721690588 ps |
| T112 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2833050435 |
|
|
Apr 02 12:40:01 PM PDT 24 |
Apr 02 12:40:04 PM PDT 24 |
75503352 ps |
| T114 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3595677699 |
|
|
Apr 02 12:33:08 PM PDT 24 |
Apr 02 12:33:12 PM PDT 24 |
441817395 ps |
| T115 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1650209625 |
|
|
Apr 02 12:33:28 PM PDT 24 |
Apr 02 12:33:30 PM PDT 24 |
90832870 ps |
| T120 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3730752458 |
|
|
Apr 02 12:40:02 PM PDT 24 |
Apr 02 12:40:04 PM PDT 24 |
377666385 ps |
| T121 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2957280724 |
|
|
Apr 02 12:33:33 PM PDT 24 |
Apr 02 12:33:35 PM PDT 24 |
23630191 ps |
| T233 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.869964927 |
|
|
Apr 02 12:40:11 PM PDT 24 |
Apr 02 12:40:13 PM PDT 24 |
47299506 ps |
| T908 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1377771310 |
|
|
Apr 02 12:40:19 PM PDT 24 |
Apr 02 12:40:21 PM PDT 24 |
122652224 ps |
| T240 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3135931891 |
|
|
Apr 02 12:33:10 PM PDT 24 |
Apr 02 12:33:12 PM PDT 24 |
40573408 ps |
| T159 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3346691964 |
|
|
Apr 02 12:32:49 PM PDT 24 |
Apr 02 12:33:00 PM PDT 24 |
6269223044 ps |
| T129 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2727489461 |
|
|
Apr 02 12:33:00 PM PDT 24 |
Apr 02 12:33:01 PM PDT 24 |
101233639 ps |
| T126 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.730744966 |
|
|
Apr 02 12:32:51 PM PDT 24 |
Apr 02 12:32:56 PM PDT 24 |
1223903148 ps |
| T909 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1388673676 |
|
|
Apr 02 12:39:59 PM PDT 24 |
Apr 02 12:40:01 PM PDT 24 |
55728966 ps |
| T910 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.559918188 |
|
|
Apr 02 12:32:48 PM PDT 24 |
Apr 02 12:32:49 PM PDT 24 |
21458877 ps |
| T234 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3927500220 |
|
|
Apr 02 12:40:22 PM PDT 24 |
Apr 02 12:40:24 PM PDT 24 |
50849356 ps |
| T241 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1615036333 |
|
|
Apr 02 12:40:04 PM PDT 24 |
Apr 02 12:40:06 PM PDT 24 |
132746942 ps |
| T911 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1257959234 |
|
|
Apr 02 12:40:19 PM PDT 24 |
Apr 02 12:40:20 PM PDT 24 |
463836483 ps |
| T135 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3490016014 |
|
|
Apr 02 12:40:23 PM PDT 24 |
Apr 02 12:40:30 PM PDT 24 |
278970909 ps |
| T160 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.850037737 |
|
|
Apr 02 12:40:05 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
330667336 ps |
| T912 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1933478765 |
|
|
Apr 02 12:32:53 PM PDT 24 |
Apr 02 12:32:56 PM PDT 24 |
60999400 ps |
| T161 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1687105872 |
|
|
Apr 02 12:40:14 PM PDT 24 |
Apr 02 12:40:16 PM PDT 24 |
356784681 ps |
| T235 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2706844640 |
|
|
Apr 02 12:40:23 PM PDT 24 |
Apr 02 12:40:24 PM PDT 24 |
44281643 ps |
| T123 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.212931997 |
|
|
Apr 02 12:33:24 PM PDT 24 |
Apr 02 12:33:26 PM PDT 24 |
60585250 ps |
| T130 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1413714345 |
|
|
Apr 02 12:40:23 PM PDT 24 |
Apr 02 12:40:26 PM PDT 24 |
324682180 ps |
| T236 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.494163856 |
|
|
Apr 02 12:40:18 PM PDT 24 |
Apr 02 12:40:19 PM PDT 24 |
182279697 ps |
| T913 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1028142163 |
|
|
Apr 02 12:40:06 PM PDT 24 |
Apr 02 12:40:09 PM PDT 24 |
297874959 ps |
| T914 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3929438669 |
|
|
Apr 02 12:40:19 PM PDT 24 |
Apr 02 12:40:21 PM PDT 24 |
92372391 ps |
| T915 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.195277895 |
|
|
Apr 02 12:33:14 PM PDT 24 |
Apr 02 12:33:21 PM PDT 24 |
635295652 ps |
| T916 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3654910824 |
|
|
Apr 02 12:39:58 PM PDT 24 |
Apr 02 12:40:00 PM PDT 24 |
19732609 ps |
| T917 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.13382726 |
|
|
Apr 02 12:32:42 PM PDT 24 |
Apr 02 12:32:45 PM PDT 24 |
109305226 ps |
| T918 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3430769914 |
|
|
Apr 02 12:40:02 PM PDT 24 |
Apr 02 12:40:05 PM PDT 24 |
41478901 ps |
| T919 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3696895220 |
|
|
Apr 02 12:33:07 PM PDT 24 |
Apr 02 12:33:09 PM PDT 24 |
13577824 ps |
| T213 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.614538688 |
|
|
Apr 02 12:32:59 PM PDT 24 |
Apr 02 12:33:00 PM PDT 24 |
63569265 ps |
| T237 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3700026513 |
|
|
Apr 02 12:33:23 PM PDT 24 |
Apr 02 12:33:26 PM PDT 24 |
45130151 ps |
| T920 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.390743130 |
|
|
Apr 02 12:32:53 PM PDT 24 |
Apr 02 12:32:56 PM PDT 24 |
128830714 ps |
| T921 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4254168661 |
|
|
Apr 02 12:33:29 PM PDT 24 |
Apr 02 12:33:31 PM PDT 24 |
21511292 ps |
| T922 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3978007031 |
|
|
Apr 02 12:33:29 PM PDT 24 |
Apr 02 12:33:31 PM PDT 24 |
19257592 ps |
| T923 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3188084724 |
|
|
Apr 02 12:33:37 PM PDT 24 |
Apr 02 12:33:39 PM PDT 24 |
38394059 ps |
| T924 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2159500548 |
|
|
Apr 02 12:40:04 PM PDT 24 |
Apr 02 12:40:07 PM PDT 24 |
137779397 ps |
| T925 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1005034172 |
|
|
Apr 02 12:33:27 PM PDT 24 |
Apr 02 12:33:30 PM PDT 24 |
240612401 ps |
| T926 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2731942314 |
|
|
Apr 02 12:32:40 PM PDT 24 |
Apr 02 12:32:42 PM PDT 24 |
141367011 ps |
| T927 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3109609432 |
|
|
Apr 02 12:40:25 PM PDT 24 |
Apr 02 12:40:27 PM PDT 24 |
48703150 ps |
| T119 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2900538806 |
|
|
Apr 02 12:33:16 PM PDT 24 |
Apr 02 12:33:19 PM PDT 24 |
143251819 ps |
| T928 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1728015962 |
|
|
Apr 02 12:32:54 PM PDT 24 |
Apr 02 12:32:56 PM PDT 24 |
145929646 ps |
| T140 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1026162015 |
|
|
Apr 02 12:33:39 PM PDT 24 |
Apr 02 12:33:42 PM PDT 24 |
498177384 ps |
| T929 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3220360713 |
|
|
Apr 02 12:39:57 PM PDT 24 |
Apr 02 12:39:59 PM PDT 24 |
36128809 ps |
| T930 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3397837542 |
|
|
Apr 02 12:40:13 PM PDT 24 |
Apr 02 12:40:17 PM PDT 24 |
114414925 ps |
| T931 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3294766198 |
|
|
Apr 02 12:40:19 PM PDT 24 |
Apr 02 12:40:21 PM PDT 24 |
16083482 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2976764213 |
|
|
Apr 02 12:40:18 PM PDT 24 |
Apr 02 12:40:21 PM PDT 24 |
375694749 ps |
| T932 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.543243003 |
|
|
Apr 02 12:40:18 PM PDT 24 |
Apr 02 12:40:24 PM PDT 24 |
556809320 ps |
| T933 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2591819635 |
|
|
Apr 02 12:33:11 PM PDT 24 |
Apr 02 12:33:12 PM PDT 24 |
49019363 ps |
| T214 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3947975063 |
|
|
Apr 02 12:40:05 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
30372337 ps |
| T934 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.594270288 |
|
|
Apr 02 12:33:19 PM PDT 24 |
Apr 02 12:33:23 PM PDT 24 |
601850449 ps |
| T935 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1883533479 |
|
|
Apr 02 12:33:16 PM PDT 24 |
Apr 02 12:33:52 PM PDT 24 |
1614087584 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.272046829 |
|
|
Apr 02 12:32:56 PM PDT 24 |
Apr 02 12:32:58 PM PDT 24 |
45054555 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3242491227 |
|
|
Apr 02 12:32:54 PM PDT 24 |
Apr 02 12:32:57 PM PDT 24 |
66879314 ps |
| T938 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4107164769 |
|
|
Apr 02 12:40:07 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
58680067 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3401281798 |
|
|
Apr 02 12:40:06 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
137396616 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3767052009 |
|
|
Apr 02 12:39:58 PM PDT 24 |
Apr 02 12:40:02 PM PDT 24 |
481231609 ps |
| T941 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1125773422 |
|
|
Apr 02 12:40:13 PM PDT 24 |
Apr 02 12:40:15 PM PDT 24 |
166795920 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1861452928 |
|
|
Apr 02 12:33:23 PM PDT 24 |
Apr 02 12:33:25 PM PDT 24 |
116201344 ps |
| T149 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1483576986 |
|
|
Apr 02 12:33:32 PM PDT 24 |
Apr 02 12:33:35 PM PDT 24 |
61716703 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.95645936 |
|
|
Apr 02 12:33:21 PM PDT 24 |
Apr 02 12:33:22 PM PDT 24 |
60517402 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1998346230 |
|
|
Apr 02 12:33:04 PM PDT 24 |
Apr 02 12:33:17 PM PDT 24 |
782989598 ps |
| T141 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2741857097 |
|
|
Apr 02 12:32:56 PM PDT 24 |
Apr 02 12:32:59 PM PDT 24 |
219810313 ps |
| T945 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3737331025 |
|
|
Apr 02 12:40:25 PM PDT 24 |
Apr 02 12:40:28 PM PDT 24 |
69838803 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2160225189 |
|
|
Apr 02 12:40:23 PM PDT 24 |
Apr 02 12:40:25 PM PDT 24 |
33365081 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.270053682 |
|
|
Apr 02 12:33:17 PM PDT 24 |
Apr 02 12:33:21 PM PDT 24 |
119066225 ps |
| T948 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1546839007 |
|
|
Apr 02 12:40:18 PM PDT 24 |
Apr 02 12:40:19 PM PDT 24 |
32877155 ps |
| T949 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2354435185 |
|
|
Apr 02 12:32:40 PM PDT 24 |
Apr 02 12:32:41 PM PDT 24 |
35474370 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3344760843 |
|
|
Apr 02 12:40:54 PM PDT 24 |
Apr 02 12:40:56 PM PDT 24 |
20209340 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3971181690 |
|
|
Apr 02 12:32:49 PM PDT 24 |
Apr 02 12:32:52 PM PDT 24 |
159368436 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.691155790 |
|
|
Apr 02 12:39:57 PM PDT 24 |
Apr 02 12:40:11 PM PDT 24 |
544158962 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.142796299 |
|
|
Apr 02 12:40:01 PM PDT 24 |
Apr 02 12:40:04 PM PDT 24 |
69818409 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1539418519 |
|
|
Apr 02 12:33:29 PM PDT 24 |
Apr 02 12:33:32 PM PDT 24 |
137136493 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3265089855 |
|
|
Apr 02 12:33:11 PM PDT 24 |
Apr 02 12:33:14 PM PDT 24 |
141700078 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.543612768 |
|
|
Apr 02 12:40:04 PM PDT 24 |
Apr 02 12:40:06 PM PDT 24 |
30562972 ps |
| T146 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.207098926 |
|
|
Apr 02 12:32:45 PM PDT 24 |
Apr 02 12:32:47 PM PDT 24 |
230822944 ps |
| T957 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3410330131 |
|
|
Apr 02 12:40:12 PM PDT 24 |
Apr 02 12:40:14 PM PDT 24 |
36047434 ps |
| T958 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3404401435 |
|
|
Apr 02 12:33:20 PM PDT 24 |
Apr 02 12:33:21 PM PDT 24 |
17113158 ps |
| T157 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.672560057 |
|
|
Apr 02 12:33:24 PM PDT 24 |
Apr 02 12:33:27 PM PDT 24 |
116693759 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.134278259 |
|
|
Apr 02 12:32:42 PM PDT 24 |
Apr 02 12:32:43 PM PDT 24 |
44362837 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4183433643 |
|
|
Apr 02 12:32:55 PM PDT 24 |
Apr 02 12:32:57 PM PDT 24 |
305218719 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2828693271 |
|
|
Apr 02 12:33:14 PM PDT 24 |
Apr 02 12:33:22 PM PDT 24 |
948838912 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.901151405 |
|
|
Apr 02 12:33:28 PM PDT 24 |
Apr 02 12:33:29 PM PDT 24 |
63962873 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.421210524 |
|
|
Apr 02 12:32:43 PM PDT 24 |
Apr 02 12:32:55 PM PDT 24 |
2409720516 ps |
| T964 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2434198561 |
|
|
Apr 02 12:33:40 PM PDT 24 |
Apr 02 12:33:41 PM PDT 24 |
43243997 ps |
| T965 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1134560855 |
|
|
Apr 02 12:32:57 PM PDT 24 |
Apr 02 12:32:59 PM PDT 24 |
57441062 ps |
| T136 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3706544169 |
|
|
Apr 02 12:33:03 PM PDT 24 |
Apr 02 12:33:06 PM PDT 24 |
125326526 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3374906063 |
|
|
Apr 02 12:33:18 PM PDT 24 |
Apr 02 12:33:20 PM PDT 24 |
379255360 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2833517813 |
|
|
Apr 02 12:32:54 PM PDT 24 |
Apr 02 12:32:56 PM PDT 24 |
27379488 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1212974443 |
|
|
Apr 02 12:40:05 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
114115162 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3168864923 |
|
|
Apr 02 12:40:14 PM PDT 24 |
Apr 02 12:40:16 PM PDT 24 |
131756687 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3800426263 |
|
|
Apr 02 12:33:09 PM PDT 24 |
Apr 02 12:33:11 PM PDT 24 |
100731669 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1317546361 |
|
|
Apr 02 12:40:18 PM PDT 24 |
Apr 02 12:40:19 PM PDT 24 |
27601580 ps |
| T154 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.491548695 |
|
|
Apr 02 12:39:59 PM PDT 24 |
Apr 02 12:40:01 PM PDT 24 |
806591737 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4219554505 |
|
|
Apr 02 12:33:06 PM PDT 24 |
Apr 02 12:33:13 PM PDT 24 |
1155770383 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2644899687 |
|
|
Apr 02 12:40:14 PM PDT 24 |
Apr 02 12:40:33 PM PDT 24 |
2828221501 ps |
| T158 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3436065841 |
|
|
Apr 02 12:33:33 PM PDT 24 |
Apr 02 12:33:36 PM PDT 24 |
62354753 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1751867400 |
|
|
Apr 02 12:33:03 PM PDT 24 |
Apr 02 12:33:05 PM PDT 24 |
97509923 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4244266157 |
|
|
Apr 02 12:40:21 PM PDT 24 |
Apr 02 12:40:23 PM PDT 24 |
118756332 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3232708017 |
|
|
Apr 02 12:40:06 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
65544567 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2826535721 |
|
|
Apr 02 12:33:18 PM PDT 24 |
Apr 02 12:33:20 PM PDT 24 |
24397184 ps |
| T978 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.570442282 |
|
|
Apr 02 12:40:21 PM PDT 24 |
Apr 02 12:40:22 PM PDT 24 |
291540212 ps |
| T979 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1374652151 |
|
|
Apr 02 12:40:01 PM PDT 24 |
Apr 02 12:40:02 PM PDT 24 |
59346141 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.130073222 |
|
|
Apr 02 12:33:01 PM PDT 24 |
Apr 02 12:33:03 PM PDT 24 |
308849503 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1750987440 |
|
|
Apr 02 12:40:19 PM PDT 24 |
Apr 02 12:40:20 PM PDT 24 |
14943938 ps |
| T152 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4100769719 |
|
|
Apr 02 12:40:20 PM PDT 24 |
Apr 02 12:40:23 PM PDT 24 |
117976471 ps |
| T124 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.964501264 |
|
|
Apr 02 12:33:27 PM PDT 24 |
Apr 02 12:33:30 PM PDT 24 |
158108710 ps |
| T982 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1874134996 |
|
|
Apr 02 12:40:23 PM PDT 24 |
Apr 02 12:40:26 PM PDT 24 |
20085931 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2361386902 |
|
|
Apr 02 12:32:49 PM PDT 24 |
Apr 02 12:32:51 PM PDT 24 |
62682171 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.109200132 |
|
|
Apr 02 12:40:15 PM PDT 24 |
Apr 02 12:40:18 PM PDT 24 |
48763043 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2677433504 |
|
|
Apr 02 12:32:39 PM PDT 24 |
Apr 02 12:32:41 PM PDT 24 |
112786204 ps |
| T215 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4278086452 |
|
|
Apr 02 12:40:06 PM PDT 24 |
Apr 02 12:40:08 PM PDT 24 |
21635367 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4190056611 |
|
|
Apr 02 12:33:27 PM PDT 24 |
Apr 02 12:33:28 PM PDT 24 |
21774740 ps |
| T216 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3481972028 |
|
|
Apr 02 12:33:28 PM PDT 24 |
Apr 02 12:33:29 PM PDT 24 |
13032838 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1015261112 |
|
|
Apr 02 12:33:14 PM PDT 24 |
Apr 02 12:33:16 PM PDT 24 |
89024149 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2734551237 |
|
|
Apr 02 12:33:25 PM PDT 24 |
Apr 02 12:33:26 PM PDT 24 |
34475281 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.428737818 |
|
|
Apr 02 12:40:06 PM PDT 24 |
Apr 02 12:40:30 PM PDT 24 |
2137276402 ps |
| T990 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3926573787 |
|
|
Apr 02 12:33:28 PM PDT 24 |
Apr 02 12:33:31 PM PDT 24 |
495841761 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2220326743 |
|
|
Apr 02 12:40:09 PM PDT 24 |
Apr 02 12:40:18 PM PDT 24 |
5918605957 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.826836763 |
|
|
Apr 02 12:32:51 PM PDT 24 |
Apr 02 12:32:53 PM PDT 24 |
15687200 ps |
| T217 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3583494131 |
|
|
Apr 02 12:33:24 PM PDT 24 |
Apr 02 12:33:25 PM PDT 24 |
125560134 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1443512890 |
|
|
Apr 02 12:33:25 PM PDT 24 |
Apr 02 12:33:26 PM PDT 24 |
57611332 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3113140541 |
|
|
Apr 02 12:33:34 PM PDT 24 |
Apr 02 12:33:36 PM PDT 24 |
90169672 ps |
| T995 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3057605308 |
|
|
Apr 02 12:40:21 PM PDT 24 |
Apr 02 12:40:25 PM PDT 24 |
450005430 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.658610062 |
|
|
Apr 02 12:40:02 PM PDT 24 |
Apr 02 12:40:23 PM PDT 24 |
3106063506 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2988022060 |
|
|
Apr 02 12:40:06 PM PDT 24 |
Apr 02 12:40:09 PM PDT 24 |
43347659 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.820580843 |
|
|
Apr 02 12:32:56 PM PDT 24 |
Apr 02 12:33:07 PM PDT 24 |
824495671 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2390071370 |
|
|
Apr 02 12:40:06 PM PDT 24 |
Apr 02 12:40:09 PM PDT 24 |
147972116 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3020468648 |
|
|
Apr 02 12:33:03 PM PDT 24 |
Apr 02 12:33:04 PM PDT 24 |
37993973 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2373627396 |
|
|
Apr 02 12:40:05 PM PDT 24 |
Apr 02 12:40:12 PM PDT 24 |
858025088 ps |
| T1002 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1773703624 |
|
|
Apr 02 12:40:24 PM PDT 24 |
Apr 02 12:40:27 PM PDT 24 |
116673059 ps |
| T1003 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2084024034 |
|
|
Apr 02 12:40:05 PM PDT 24 |
Apr 02 12:40:09 PM PDT 24 |
586117176 ps |
| T142 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1606597316 |
|
|
Apr 02 12:33:31 PM PDT 24 |
Apr 02 12:33:33 PM PDT 24 |
44888943 ps |
| T218 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4140975117 |
|
|
Apr 02 12:32:54 PM PDT 24 |
Apr 02 12:32:56 PM PDT 24 |
75614057 ps |
| T1004 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.316170398 |
|
|
Apr 02 12:40:13 PM PDT 24 |
Apr 02 12:40:16 PM PDT 24 |
387092499 ps |
| T1005 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1281383307 |
|
|
Apr 02 12:33:34 PM PDT 24 |
Apr 02 12:33:35 PM PDT 24 |
65424327 ps |
| T219 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.539464578 |
|
|
Apr 02 12:33:07 PM PDT 24 |
Apr 02 12:33:08 PM PDT 24 |
14854662 ps |
| T1006 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1110109044 |
|
|
Apr 02 12:40:28 PM PDT 24 |
Apr 02 12:40:30 PM PDT 24 |
60239972 ps |
| T1007 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2303837278 |
|
|
Apr 02 12:33:22 PM PDT 24 |
Apr 02 12:33:26 PM PDT 24 |
470775994 ps |
| T1008 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1943446925 |
|
|
Apr 02 12:39:59 PM PDT 24 |
Apr 02 12:40:01 PM PDT 24 |
309135929 ps |
| T1009 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2855212956 |
|
|
Apr 02 12:32:45 PM PDT 24 |
Apr 02 12:32:46 PM PDT 24 |
31168350 ps |
| T132 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3674223117 |
|
|
Apr 02 12:40:02 PM PDT 24 |
Apr 02 12:40:05 PM PDT 24 |
90706381 ps |
| T1010 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3783745724 |
|
|
Apr 02 12:40:01 PM PDT 24 |
Apr 02 12:40:03 PM PDT 24 |
45997645 ps |
| T1011 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3880274049 |
|
|
Apr 02 12:40:05 PM PDT 24 |
Apr 02 12:40:07 PM PDT 24 |
20304080 ps |
| T1012 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1758364607 |
|
|
Apr 02 12:33:33 PM PDT 24 |
Apr 02 12:33:34 PM PDT 24 |
42527094 ps |
| T1013 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.753338476 |
|
|
Apr 02 12:32:56 PM PDT 24 |
Apr 02 12:33:01 PM PDT 24 |
403940443 ps |
| T1014 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4255336736 |
|
|
Apr 02 12:40:09 PM PDT 24 |
Apr 02 12:40:10 PM PDT 24 |
28493384 ps |
| T1015 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4001995110 |
|
|
Apr 02 12:32:55 PM PDT 24 |
Apr 02 12:33:01 PM PDT 24 |
1136791601 ps |
| T1016 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3137108692 |
|
|
Apr 02 12:40:00 PM PDT 24 |
Apr 02 12:40:02 PM PDT 24 |
68977329 ps |
| T1017 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1634224491 |
|
|
Apr 02 12:32:53 PM PDT 24 |
Apr 02 12:32:55 PM PDT 24 |
242657294 ps |
| T1018 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1686285335 |
|
|
Apr 02 12:39:58 PM PDT 24 |
Apr 02 12:39:59 PM PDT 24 |
38385207 ps |
| T1019 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2978891367 |
|
|
Apr 02 12:40:23 PM PDT 24 |
Apr 02 12:40:26 PM PDT 24 |
260718119 ps |
| T1020 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2701043900 |
|
|
Apr 02 12:32:51 PM PDT 24 |
Apr 02 12:32:56 PM PDT 24 |
2085677263 ps |
| T1021 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2017681074 |
|
|
Apr 02 12:40:04 PM PDT 24 |
Apr 02 12:40:06 PM PDT 24 |
479730966 ps |
| T1022 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4070863609 |
|
|
Apr 02 12:33:26 PM PDT 24 |
Apr 02 12:33:27 PM PDT 24 |
20888440 ps |
| T1023 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.607953629 |
|
|
Apr 02 12:40:00 PM PDT 24 |
Apr 02 12:40:04 PM PDT 24 |
589608962 ps |
| T1024 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3030997597 |
|
|
Apr 02 12:32:43 PM PDT 24 |
Apr 02 12:32:45 PM PDT 24 |
65804733 ps |
| T1025 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2775420858 |
|
|
Apr 02 12:40:03 PM PDT 24 |
Apr 02 12:40:10 PM PDT 24 |
500368702 ps |
| T1026 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1461009541 |
|
|
Apr 02 12:40:11 PM PDT 24 |
Apr 02 12:40:13 PM PDT 24 |
20708773 ps |
| T1027 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3698888000 |
|
|
Apr 02 12:33:25 PM PDT 24 |
Apr 02 12:33:26 PM PDT 24 |
18148002 ps |