Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105832 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3723 |
1 |
|
|
T42 |
8 |
|
T19 |
82 |
|
T20 |
22 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
107989 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
1566 |
1 |
|
|
T43 |
19 |
|
T76 |
12 |
|
T77 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105616 |
1 |
|
|
T1 |
84 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3939 |
1 |
|
|
T1 |
14 |
|
T12 |
1 |
|
T19 |
57 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105618 |
1 |
|
|
T1 |
92 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3937 |
1 |
|
|
T1 |
6 |
|
T12 |
1 |
|
T19 |
65 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105605 |
1 |
|
|
T1 |
84 |
|
T2 |
8 |
|
T3 |
50 |
auto[1] |
3950 |
1 |
|
|
T1 |
14 |
|
T2 |
3 |
|
T49 |
3 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
99847 |
1 |
|
|
T1 |
98 |
|
T2 |
6 |
|
T3 |
50 |
no_err_inj |
9708 |
1 |
|
|
T2 |
5 |
|
T11 |
18 |
|
T12 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105752 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3803 |
1 |
|
|
T42 |
12 |
|
T19 |
67 |
|
T20 |
23 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
108025 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
1530 |
1 |
|
|
T43 |
14 |
|
T76 |
9 |
|
T77 |
13 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
75035 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[1] |
34520 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105653 |
1 |
|
|
T1 |
89 |
|
T2 |
10 |
|
T3 |
50 |
auto[1] |
3902 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T19 |
65 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105777 |
1 |
|
|
T1 |
83 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3778 |
1 |
|
|
T1 |
15 |
|
T12 |
1 |
|
T19 |
77 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105638 |
1 |
|
|
T1 |
88 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3917 |
1 |
|
|
T1 |
10 |
|
T12 |
2 |
|
T19 |
66 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105793 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3762 |
1 |
|
|
T42 |
15 |
|
T19 |
74 |
|
T20 |
36 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105108 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
4447 |
1 |
|
|
T10 |
18 |
|
T13 |
4 |
|
T17 |
18 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
108100 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
1455 |
1 |
|
|
T43 |
25 |
|
T76 |
17 |
|
T77 |
6 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
108022 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
1533 |
1 |
|
|
T43 |
17 |
|
T76 |
20 |
|
T77 |
16 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
108058 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
1497 |
1 |
|
|
T43 |
17 |
|
T76 |
19 |
|
T77 |
10 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
104320 |
1 |
|
|
T1 |
98 |
|
T3 |
50 |
|
T10 |
18 |
auto[1] |
5235 |
1 |
|
|
T2 |
11 |
|
T12 |
15 |
|
T49 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
102173 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T10 |
18 |
auto[1] |
7382 |
1 |
|
|
T3 |
50 |
|
T50 |
88 |
|
T63 |
93 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105599 |
1 |
|
|
T1 |
90 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3956 |
1 |
|
|
T1 |
8 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105654 |
1 |
|
|
T1 |
85 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3901 |
1 |
|
|
T1 |
13 |
|
T49 |
2 |
|
T19 |
67 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105572 |
1 |
|
|
T1 |
89 |
|
T2 |
9 |
|
T3 |
50 |
auto[1] |
3983 |
1 |
|
|
T1 |
9 |
|
T2 |
2 |
|
T12 |
2 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105859 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3696 |
1 |
|
|
T42 |
14 |
|
T19 |
79 |
|
T20 |
20 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
98246 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
11309 |
1 |
|
|
T46 |
90 |
|
T48 |
91 |
|
T42 |
7 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101867 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
7688 |
1 |
|
|
T62 |
91 |
|
T74 |
55 |
|
T75 |
68 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
109555 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105795 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3760 |
1 |
|
|
T42 |
9 |
|
T19 |
68 |
|
T20 |
29 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105884 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3671 |
1 |
|
|
T42 |
11 |
|
T19 |
64 |
|
T20 |
22 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105793 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
50 |
auto[1] |
3762 |
1 |
|
|
T42 |
12 |
|
T19 |
69 |
|
T20 |
25 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
97238 |
1 |
|
|
T1 |
98 |
|
T3 |
50 |
|
T10 |
18 |
auto[0] |
no_err_inj |
7082 |
1 |
|
|
T11 |
18 |
|
T14 |
14 |
|
T16 |
2 |
auto[1] |
err_inj |
2609 |
1 |
|
|
T2 |
6 |
|
T12 |
8 |
|
T49 |
7 |
auto[1] |
no_err_inj |
2626 |
1 |
|
|
T2 |
5 |
|
T12 |
7 |
|
T49 |
4 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
100713 |
1 |
|
|
T1 |
85 |
|
T3 |
50 |
|
T10 |
18 |
auto[0] |
auto[1] |
3607 |
1 |
|
|
T1 |
13 |
|
T19 |
57 |
|
T20 |
27 |
auto[1] |
auto[0] |
4941 |
1 |
|
|
T2 |
11 |
|
T12 |
15 |
|
T49 |
9 |
auto[1] |
auto[1] |
294 |
1 |
|
|
T49 |
2 |
|
T19 |
10 |
|
T20 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
100831 |
1 |
|
|
T1 |
83 |
|
T3 |
50 |
|
T10 |
18 |
auto[0] |
auto[1] |
3489 |
1 |
|
|
T1 |
15 |
|
T19 |
68 |
|
T20 |
24 |
auto[1] |
auto[0] |
4946 |
1 |
|
|
T2 |
11 |
|
T12 |
14 |
|
T49 |
11 |
auto[1] |
auto[1] |
289 |
1 |
|
|
T12 |
1 |
|
T19 |
9 |
|
T20 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
100621 |
1 |
|
|
T1 |
89 |
|
T3 |
50 |
|
T10 |
18 |
auto[0] |
auto[1] |
3699 |
1 |
|
|
T1 |
9 |
|
T19 |
58 |
|
T20 |
26 |
auto[1] |
auto[0] |
4951 |
1 |
|
|
T2 |
9 |
|
T12 |
13 |
|
T49 |
10 |
auto[1] |
auto[1] |
284 |
1 |
|
|
T2 |
2 |
|
T12 |
2 |
|
T49 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
100686 |
1 |
|
|
T1 |
92 |
|
T3 |
50 |
|
T10 |
18 |
auto[0] |
auto[1] |
3634 |
1 |
|
|
T1 |
6 |
|
T19 |
63 |
|
T20 |
26 |
auto[1] |
auto[0] |
4932 |
1 |
|
|
T2 |
11 |
|
T12 |
14 |
|
T49 |
11 |
auto[1] |
auto[1] |
303 |
1 |
|
|
T12 |
1 |
|
T19 |
2 |
|
T20 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
100634 |
1 |
|
|
T1 |
84 |
|
T3 |
50 |
|
T10 |
18 |
auto[0] |
auto[1] |
3686 |
1 |
|
|
T1 |
14 |
|
T19 |
54 |
|
T20 |
30 |
auto[1] |
auto[0] |
4971 |
1 |
|
|
T2 |
8 |
|
T12 |
15 |
|
T49 |
8 |
auto[1] |
auto[1] |
264 |
1 |
|
|
T2 |
3 |
|
T49 |
3 |
|
T19 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
100651 |
1 |
|
|
T1 |
84 |
|
T3 |
50 |
|
T10 |
18 |
auto[0] |
auto[1] |
3669 |
1 |
|
|
T1 |
14 |
|
T19 |
57 |
|
T20 |
26 |
auto[1] |
auto[0] |
4965 |
1 |
|
|
T2 |
11 |
|
T12 |
14 |
|
T49 |
11 |
auto[1] |
auto[1] |
270 |
1 |
|
|
T12 |
1 |
|
T20 |
3 |
|
T99 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72912 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2123 |
1 |
|
|
T42 |
8 |
|
T19 |
57 |
|
T20 |
7 |
auto[1] |
auto[0] |
32920 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1600 |
1 |
|
|
T19 |
25 |
|
T20 |
15 |
|
T21 |
16 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72879 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2156 |
1 |
|
|
T42 |
12 |
|
T19 |
54 |
|
T20 |
3 |
auto[1] |
auto[0] |
32873 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1647 |
1 |
|
|
T19 |
13 |
|
T20 |
20 |
|
T21 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72554 |
1 |
|
|
T3 |
50 |
|
T11 |
18 |
|
T12 |
15 |
auto[0] |
auto[1] |
2481 |
1 |
|
|
T10 |
18 |
|
T13 |
4 |
|
T17 |
18 |
auto[1] |
auto[0] |
32554 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1966 |
1 |
|
|
T18 |
3 |
|
T19 |
22 |
|
T97 |
8 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72940 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2095 |
1 |
|
|
T42 |
15 |
|
T19 |
52 |
|
T20 |
10 |
auto[1] |
auto[0] |
32853 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1667 |
1 |
|
|
T19 |
22 |
|
T20 |
26 |
|
T21 |
7 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
65345 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
9690 |
1 |
|
|
T46 |
90 |
|
T48 |
91 |
|
T42 |
7 |
auto[1] |
auto[0] |
32901 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1619 |
1 |
|
|
T19 |
17 |
|
T20 |
23 |
|
T21 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72777 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2258 |
1 |
|
|
T49 |
2 |
|
T19 |
30 |
|
T20 |
29 |
auto[1] |
auto[0] |
32877 |
1 |
|
|
T1 |
85 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1643 |
1 |
|
|
T1 |
13 |
|
T19 |
37 |
|
T97 |
10 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72765 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2270 |
1 |
|
|
T12 |
1 |
|
T49 |
1 |
|
T19 |
33 |
auto[1] |
auto[0] |
32834 |
1 |
|
|
T1 |
90 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1686 |
1 |
|
|
T1 |
8 |
|
T19 |
33 |
|
T97 |
15 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72981 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2054 |
1 |
|
|
T12 |
1 |
|
T19 |
34 |
|
T20 |
27 |
auto[1] |
auto[0] |
32796 |
1 |
|
|
T1 |
83 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1724 |
1 |
|
|
T1 |
15 |
|
T19 |
43 |
|
T278 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72817 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2218 |
1 |
|
|
T19 |
32 |
|
T20 |
30 |
|
T99 |
1 |
auto[1] |
auto[0] |
32836 |
1 |
|
|
T1 |
89 |
|
T2 |
10 |
|
T14 |
14 |
auto[1] |
auto[1] |
1684 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T19 |
33 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72814 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2221 |
1 |
|
|
T12 |
1 |
|
T19 |
29 |
|
T20 |
28 |
auto[1] |
auto[0] |
32804 |
1 |
|
|
T1 |
92 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1716 |
1 |
|
|
T1 |
6 |
|
T19 |
36 |
|
T278 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72784 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2251 |
1 |
|
|
T12 |
1 |
|
T19 |
28 |
|
T20 |
29 |
auto[1] |
auto[0] |
32832 |
1 |
|
|
T1 |
84 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1688 |
1 |
|
|
T1 |
14 |
|
T19 |
29 |
|
T97 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72946 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2089 |
1 |
|
|
T42 |
12 |
|
T19 |
51 |
|
T20 |
15 |
auto[1] |
auto[0] |
32847 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1673 |
1 |
|
|
T19 |
18 |
|
T20 |
10 |
|
T21 |
16 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72938 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
2097 |
1 |
|
|
T42 |
11 |
|
T19 |
48 |
|
T20 |
13 |
auto[1] |
auto[0] |
32946 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T14 |
14 |
auto[1] |
auto[1] |
1574 |
1 |
|
|
T19 |
16 |
|
T20 |
9 |
|
T21 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71886 |
1 |
|
|
T3 |
50 |
|
T10 |
18 |
|
T11 |
18 |
auto[0] |
auto[1] |
3149 |
1 |
|
|
T12 |
15 |
|
T49 |
11 |
|
T19 |
45 |
auto[1] |
auto[0] |
32434 |
1 |
|
|
T1 |
98 |
|
T14 |
14 |
|
T18 |
3 |
auto[1] |
auto[1] |
2086 |
1 |
|
|
T2 |
11 |
|
T19 |
25 |
|
T278 |
15 |