Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

201124596

1

T1

290228

T2

38427

T3

13698

auto[1]

2857558

1

T1

3234

T2

196

T3

5717

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

201150788

1

T1

288954

T2

38427

T3

11670

auto[1]

2831366

1

T1

4508

T2

196

T3

7745

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	14649141	1			T1	37208		T2	1217		T3	4361
auto[IdleSt]	43365217	1			T1	13993		T2	6934		T3	4080
auto[ClkMuxSt]	71707	1			T2	5		T3	41		T10	18
auto[CntIncrSt]	71041	1			T2	5		T3	39		T10	18
auto[CntProgSt]	3527205	1			T2	39		T3	385		T10	36
auto[TransCheckSt]	55791	1			T2	5		T3	20		T11	18
auto[TokenHashSt]	78244142	1			T2	266		T3	325		T11	730
auto[FlashRmaSt]	58561	1			T2	15		T3	33		T11	41
auto[TokenCheck0St]	25764	1			T2	5		T3	13		T11	18
auto[TokenCheck1St]	18964	1			T2	5		T3	13		T11	18
auto[TransProgSt]	934168	1			T2	103		T3	21		T11	206
auto[PostTransSt]	25797631	1			T2	11910		T10	1106		T11	1305
auto[ScrapSt]	286891	1			T45	14		T50	3		T19	48
auto[EscalateSt]	13567518	1			T1	53192		T2	7142		T3	10084
auto[InvalidSt]	23304492	1			T1	189054		T2	10972		T12	768

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3921	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	23304492	1			T1	189054		T2	10972		T12	768
EscalateSt	13567518	1			T1	53192		T2	7142		T3	10084
ScrapSt	286891	1			T45	14		T50	3		T19	48
PostTransSt	25797631	1			T2	11910		T10	1106		T11	1305
TransProgSt	934168	1			T2	103		T3	21		T11	206
TokenCheck1St	18964	1			T2	5		T3	13		T11	18
TokenCheck0St	25764	1			T2	5		T3	13		T11	18
FlashRmaSt	58561	1			T2	15		T3	33		T11	41
TokenHashSt	78244142	1			T2	266		T3	325		T11	730
TransCheckSt	55791	1			T2	5		T3	20		T11	18
CntProgSt	3527205	1			T2	39		T3	385		T10	36
CntIncrSt	71041	1			T2	5		T3	39		T10	18
ClkMuxSt	71707	1			T2	5		T3	41		T10	18
IdleSt	43365217	1			T1	13993		T2	6934		T3	4080
ResetSt	14649141	1			T1	37208		T2	1217		T3	4361
arcs[ResetSt=>IdleSt]	109931	1			T1	89		T2	12		T3	44
arcs[IdleSt=>ScrapSt]	581	1			T45	1		T50	1		T19	1
arcs[IdleSt=>ClkMuxSt]	71176	1			T2	5		T3	41		T10	18
arcs[ClkMuxSt=>CntIncrSt]	71041	1			T2	5		T3	39		T10	18
arcs[CntIncrSt=>PostTransSt]	3313	1			T42	10		T19	57		T20	20
arcs[CntIncrSt=>CntProgSt]	67598	1			T2	5		T3	39		T10	18
arcs[CntProgSt=>PostTransSt]	9659	1			T10	18		T13	4		T17	18
arcs[CntProgSt=>TransCheckSt]	55791	1			T2	5		T3	20		T11	18
arcs[TransCheckSt=>PostTransSt]	7663	1			T42	12		T19	69		T20	25
arcs[TransCheckSt=>TokenHashSt]	47909	1			T2	5		T3	20		T11	18
arcs[TokenHashSt=>PostTransSt]	20663	1			T43	7		T46	90		T48	91
arcs[TokenHashSt=>FlashRmaSt]	25948	1			T2	5		T3	13		T11	18
arcs[FlashRmaSt=>TokenCheck0St]	25764	1			T2	5		T3	13		T11	18
arcs[TokenCheck0St=>PostTransSt]	6738	1			T43	13		T42	11		T19	61
arcs[TokenCheck0St=>TokenCheck1St]	18964	1			T2	5		T3	13		T11	18
arcs[TokenCheck1St=>PostTransSt]	1346	1			T43	1		T42	1		T19	5
arcs[TransProgSt=>PostTransSt]	15856	1			T2	5		T11	18		T12	7
arcs[IdleSt=>EscalateSt]	426	1			T3	2		T67	13		T64	7
arcs[ClkMuxSt=>EscalateSt]	135	1			T3	2		T50	2		T63	1
arcs[CntIncrSt=>EscalateSt]	130	1			T63	3		T64	2		T65	1
arcs[CntProgSt=>EscalateSt]	2148	1			T3	19		T50	7		T63	9
arcs[TransCheckSt=>EscalateSt]	219	1			T50	11		T63	5		T67	2
arcs[TokenHashSt=>EscalateSt]	1297	1			T3	7		T50	32		T19	1
arcs[FlashRmaSt=>EscalateSt]	184	1			T50	2		T63	2		T66	3
arcs[TokenCheck0St=>EscalateSt]	62	1			T66	2		T67	1		T64	2
arcs[TokenCheck1St=>EscalateSt]	270	1			T3	4		T50	5		T19	1
arcs[TransProgSt=>EscalateSt]	1492	1			T3	9		T50	11		T63	12
arcs[PostTransSt=>EscalateSt]	10148	1			T10	18		T13	4		T17	18
arcs[InvalidSt=>EscalateSt]	28922	1			T1	79		T2	4		T12	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14648799	1			T1	37208		T2	1217		T3	4358
auto[0]	auto[IdleSt]	43364947	1			T1	13993		T2	6934		T3	4080
auto[0]	auto[ClkMuxSt]	71611	1			T2	5		T3	40		T10	18
auto[0]	auto[CntIncrSt]	70949	1			T2	5		T3	39		T10	18
auto[0]	auto[CntProgSt]	3525759	1			T2	39		T3	374		T10	36
auto[0]	auto[TransCheckSt]	55627	1			T2	5		T3	20		T11	18
auto[0]	auto[TokenHashSt]	78243292	1			T2	266		T3	319		T11	730
auto[0]	auto[FlashRmaSt]	58441	1			T2	15		T3	33		T11	41
auto[0]	auto[TokenCheck0St]	25726	1			T2	5		T3	13		T11	18
auto[0]	auto[TokenCheck1St]	18764	1			T2	5		T3	11		T11	18
auto[0]	auto[TransProgSt]	933143	1			T2	103		T3	15		T11	206
auto[0]	auto[PostTransSt]	25792454	1			T2	11910		T10	1097		T11	1305
auto[0]	auto[ScrapSt]	286802	1			T45	14		T50	2		T19	48
auto[0]	auto[EscalateSt]	10734303	1			T1	49991		T2	6948		T3	4396
auto[0]	auto[InvalidSt]	23290058	1			T1	189021		T2	10970		T12	764
auto[1]	auto[ResetSt]	342	1			T3	3		T50	6		T63	4
auto[1]	auto[IdleSt]	270	1			T67	12		T64	3		T65	2
auto[1]	auto[ClkMuxSt]	96	1			T3	1		T50	2		T63	1
auto[1]	auto[CntIncrSt]	92	1			T63	2		T64	1		T65	1
auto[1]	auto[CntProgSt]	1446	1			T3	11		T50	6		T63	6
auto[1]	auto[TransCheckSt]	164	1			T50	9		T63	4		T67	2
auto[1]	auto[TokenHashSt]	850	1			T3	6		T50	20		T63	29
auto[1]	auto[FlashRmaSt]	120	1			T50	1		T63	2		T66	3
auto[1]	auto[TokenCheck0St]	38	1			T66	1		T67	1		T65	1
auto[1]	auto[TokenCheck1St]	200	1			T3	2		T50	3		T19	1
auto[1]	auto[TransProgSt]	1025	1			T3	6		T50	7		T63	9
auto[1]	auto[PostTransSt]	5177	1			T10	9		T13	3		T17	10
auto[1]	auto[ScrapSt]	89	1			T50	1		T63	2		T66	2
auto[1]	auto[EscalateSt]	2833215	1			T1	3201		T2	194		T3	5688
auto[1]	auto[InvalidSt]	14434	1			T1	33		T2	2		T12	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	14648804	1			T1	37208		T2	1217		T3	4355
auto[0]	auto[IdleSt]	43364927	1			T1	13993		T2	6934		T3	4078
auto[0]	auto[ClkMuxSt]	71617	1			T2	5		T3	39		T10	18
auto[0]	auto[CntIncrSt]	70950	1			T2	5		T3	39		T10	18
auto[0]	auto[CntProgSt]	3525803	1			T2	39		T3	372		T10	36
auto[0]	auto[TransCheckSt]	55657	1			T2	5		T3	20		T11	18
auto[0]	auto[TokenHashSt]	78243280	1			T2	266		T3	319		T11	730
auto[0]	auto[FlashRmaSt]	58442	1			T2	15		T3	33		T11	41
auto[0]	auto[TokenCheck0St]	25721	1			T2	5		T3	13		T11	18
auto[0]	auto[TokenCheck1St]	18809	1			T2	5		T3	10		T11	18
auto[0]	auto[TransProgSt]	933199	1			T2	103		T3	15		T11	206
auto[0]	auto[PostTransSt]	25792513	1			T2	11910		T10	1097		T11	1305
auto[0]	auto[ScrapSt]	286801	1			T45	14		T50	2		T19	48
auto[0]	auto[EscalateSt]	10760340	1			T1	48730		T2	6948		T3	2377
auto[0]	auto[InvalidSt]	23290004	1			T1	189008		T2	10970		T12	768
auto[1]	auto[ResetSt]	337	1			T3	6		T50	5		T63	3
auto[1]	auto[IdleSt]	290	1			T3	2		T67	8		T64	6
auto[1]	auto[ClkMuxSt]	90	1			T3	2		T50	1		T63	1
auto[1]	auto[CntIncrSt]	91	1			T63	3		T64	2		T277	1
auto[1]	auto[CntProgSt]	1402	1			T3	13		T50	6		T63	7
auto[1]	auto[TransCheckSt]	134	1			T50	7		T63	2		T67	1
auto[1]	auto[TokenHashSt]	862	1			T3	6		T50	19		T19	1
auto[1]	auto[FlashRmaSt]	119	1			T50	2		T63	1		T66	2
auto[1]	auto[TokenCheck0St]	43	1			T66	1		T64	2		T65	1
auto[1]	auto[TokenCheck1St]	155	1			T3	3		T50	3		T63	4
auto[1]	auto[TransProgSt]	969	1			T3	6		T50	5		T63	6
auto[1]	auto[PostTransSt]	5118	1			T10	9		T13	1		T17	8
auto[1]	auto[ScrapSt]	90	1			T50	1		T63	3		T66	2
auto[1]	auto[EscalateSt]	2807178	1			T1	4462		T2	194		T3	7707
auto[1]	auto[InvalidSt]	14488	1			T1	46		T2	2		T43	6