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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 97.79 95.53 93.30 100.00 98.34 99.00 96.43


Total test records in report: 2005
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T1779 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.948275842 Apr 04 03:02:56 PM PDT 24 Apr 04 03:02:58 PM PDT 24 53394299 ps
T1780 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.23195304 Apr 04 03:02:59 PM PDT 24 Apr 04 03:03:00 PM PDT 24 234496527 ps
T1781 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3814663488 Apr 04 01:24:37 PM PDT 24 Apr 04 01:24:38 PM PDT 24 48280919 ps
T249 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2364227521 Apr 04 01:24:21 PM PDT 24 Apr 04 01:24:22 PM PDT 24 30428199 ps
T1782 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2375624202 Apr 04 03:03:05 PM PDT 24 Apr 04 03:03:07 PM PDT 24 100315148 ps
T1783 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4144477432 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:36 PM PDT 24 40769684 ps
T1784 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3135033217 Apr 04 01:24:15 PM PDT 24 Apr 04 01:24:20 PM PDT 24 301274123 ps
T159 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.755344612 Apr 04 03:03:50 PM PDT 24 Apr 04 03:03:54 PM PDT 24 206207118 ps
T1785 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2683167037 Apr 04 03:02:58 PM PDT 24 Apr 04 03:02:59 PM PDT 24 73259184 ps
T1786 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2216094048 Apr 04 01:24:26 PM PDT 24 Apr 04 01:24:29 PM PDT 24 94092235 ps
T256 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3169667734 Apr 04 03:03:51 PM PDT 24 Apr 04 03:03:52 PM PDT 24 16079310 ps
T1787 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2465601167 Apr 04 01:25:18 PM PDT 24 Apr 04 01:25:20 PM PDT 24 44454481 ps
T1788 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1721281837 Apr 04 03:03:36 PM PDT 24 Apr 04 03:03:37 PM PDT 24 12151150 ps
T1789 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1842720312 Apr 04 03:03:38 PM PDT 24 Apr 04 03:03:39 PM PDT 24 32145042 ps
T1790 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.598652420 Apr 04 01:25:06 PM PDT 24 Apr 04 01:25:08 PM PDT 24 1437880414 ps
T1791 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.582640373 Apr 04 03:03:38 PM PDT 24 Apr 04 03:03:41 PM PDT 24 558541351 ps
T1792 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3176509783 Apr 04 01:25:06 PM PDT 24 Apr 04 01:25:09 PM PDT 24 250622179 ps
T1793 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.371803190 Apr 04 03:03:01 PM PDT 24 Apr 04 03:03:05 PM PDT 24 89891220 ps
T1794 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1684002399 Apr 04 01:24:57 PM PDT 24 Apr 04 01:24:58 PM PDT 24 11497901 ps
T1795 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3517092705 Apr 04 03:03:36 PM PDT 24 Apr 04 03:03:40 PM PDT 24 1357713240 ps
T1796 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1557248265 Apr 04 01:24:37 PM PDT 24 Apr 04 01:24:41 PM PDT 24 107198615 ps
T181 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.585929371 Apr 04 03:03:49 PM PDT 24 Apr 04 03:03:52 PM PDT 24 747295496 ps
T1797 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2947277941 Apr 04 03:03:02 PM PDT 24 Apr 04 03:03:04 PM PDT 24 180406156 ps
T1798 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2363082128 Apr 04 03:03:12 PM PDT 24 Apr 04 03:03:14 PM PDT 24 80861208 ps
T1799 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4220228598 Apr 04 01:25:21 PM PDT 24 Apr 04 01:25:23 PM PDT 24 160143147 ps
T1800 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2885939232 Apr 04 03:03:33 PM PDT 24 Apr 04 03:03:35 PM PDT 24 353157074 ps
T1801 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3205136745 Apr 04 03:03:51 PM PDT 24 Apr 04 03:03:52 PM PDT 24 28731264 ps
T1802 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3492214422 Apr 04 01:24:53 PM PDT 24 Apr 04 01:24:55 PM PDT 24 53090727 ps
T1803 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1346158181 Apr 04 01:24:36 PM PDT 24 Apr 04 01:24:39 PM PDT 24 27018932 ps
T1804 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2404069355 Apr 04 01:25:29 PM PDT 24 Apr 04 01:25:30 PM PDT 24 33039661 ps
T163 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2971446680 Apr 04 03:03:37 PM PDT 24 Apr 04 03:03:41 PM PDT 24 163644490 ps
T1805 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1623531776 Apr 04 01:25:19 PM PDT 24 Apr 04 01:25:21 PM PDT 24 103247249 ps
T1806 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1988032565 Apr 04 01:25:06 PM PDT 24 Apr 04 01:25:10 PM PDT 24 818205654 ps
T1807 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3820445840 Apr 04 01:25:30 PM PDT 24 Apr 04 01:25:31 PM PDT 24 64712057 ps
T1808 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1654783999 Apr 04 03:03:33 PM PDT 24 Apr 04 03:03:34 PM PDT 24 24878215 ps
T1809 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.123456904 Apr 04 01:25:05 PM PDT 24 Apr 04 01:25:07 PM PDT 24 29512753 ps
T253 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2417096152 Apr 04 01:24:35 PM PDT 24 Apr 04 01:24:36 PM PDT 24 46804051 ps
T252 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.422416471 Apr 04 01:25:29 PM PDT 24 Apr 04 01:25:30 PM PDT 24 65222342 ps
T1810 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1463380422 Apr 04 03:03:01 PM PDT 24 Apr 04 03:03:03 PM PDT 24 222949620 ps
T250 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.467882967 Apr 04 01:25:20 PM PDT 24 Apr 04 01:25:21 PM PDT 24 88362997 ps
T1811 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2615419716 Apr 04 03:03:46 PM PDT 24 Apr 04 03:03:47 PM PDT 24 31610519 ps
T1812 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1142987395 Apr 04 01:25:32 PM PDT 24 Apr 04 01:25:34 PM PDT 24 31042434 ps
T186 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3103613890 Apr 04 01:25:30 PM PDT 24 Apr 04 01:25:32 PM PDT 24 106208127 ps
T1813 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3114445065 Apr 04 03:03:01 PM PDT 24 Apr 04 03:03:05 PM PDT 24 2159508672 ps
T1814 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4031113143 Apr 04 03:02:55 PM PDT 24 Apr 04 03:02:56 PM PDT 24 15156006 ps
T1815 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1314423913 Apr 04 03:02:57 PM PDT 24 Apr 04 03:03:01 PM PDT 24 91065076 ps
T1816 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3615437641 Apr 04 01:24:27 PM PDT 24 Apr 04 01:24:29 PM PDT 24 38216430 ps
T149 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1960602145 Apr 04 01:24:28 PM PDT 24 Apr 04 01:24:30 PM PDT 24 329708419 ps
T1817 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4192430082 Apr 04 03:03:01 PM PDT 24 Apr 04 03:03:05 PM PDT 24 922784480 ps
T1818 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2727218670 Apr 04 03:03:52 PM PDT 24 Apr 04 03:03:54 PM PDT 24 210621193 ps
T1819 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3020142819 Apr 04 03:03:06 PM PDT 24 Apr 04 03:03:08 PM PDT 24 129323450 ps
T184 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.400774038 Apr 04 01:25:33 PM PDT 24 Apr 04 01:25:34 PM PDT 24 64077343 ps
T1820 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1965508634 Apr 04 01:24:16 PM PDT 24 Apr 04 01:24:18 PM PDT 24 1469798215 ps
T1821 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2064310053 Apr 04 01:25:21 PM PDT 24 Apr 04 01:25:25 PM PDT 24 117849253 ps
T1822 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4232571091 Apr 04 01:25:22 PM PDT 24 Apr 04 01:25:24 PM PDT 24 135280595 ps
T1823 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.133481856 Apr 04 01:25:18 PM PDT 24 Apr 04 01:25:22 PM PDT 24 379756669 ps
T168 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2279003257 Apr 04 03:03:36 PM PDT 24 Apr 04 03:03:39 PM PDT 24 338535468 ps
T176 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3492813270 Apr 04 01:24:18 PM PDT 24 Apr 04 01:24:21 PM PDT 24 445501541 ps
T1824 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1677407478 Apr 04 01:25:31 PM PDT 24 Apr 04 01:25:33 PM PDT 24 30005415 ps
T1825 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2063185100 Apr 04 03:03:38 PM PDT 24 Apr 04 03:03:39 PM PDT 24 24104641 ps
T1826 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1698461064 Apr 04 01:24:54 PM PDT 24 Apr 04 01:25:16 PM PDT 24 2081922015 ps
T1827 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.714926968 Apr 04 03:03:22 PM PDT 24 Apr 04 03:03:26 PM PDT 24 1144483085 ps
T1828 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3675600591 Apr 04 03:03:02 PM PDT 24 Apr 04 03:03:04 PM PDT 24 39510078 ps
T1829 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.142798475 Apr 04 03:03:02 PM PDT 24 Apr 04 03:03:03 PM PDT 24 47078179 ps
T1830 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.637162470 Apr 04 01:25:19 PM PDT 24 Apr 04 01:25:20 PM PDT 24 42600017 ps
T1831 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1876351982 Apr 04 01:25:26 PM PDT 24 Apr 04 01:25:28 PM PDT 24 25193663 ps
T180 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2465177258 Apr 04 03:03:22 PM PDT 24 Apr 04 03:03:25 PM PDT 24 82044986 ps
T1832 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2861230493 Apr 04 03:03:38 PM PDT 24 Apr 04 03:03:42 PM PDT 24 507040709 ps
T1833 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2907865379 Apr 04 01:24:17 PM PDT 24 Apr 04 01:24:20 PM PDT 24 237603944 ps
T1834 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.291470936 Apr 04 01:24:46 PM PDT 24 Apr 04 01:25:01 PM PDT 24 5485378595 ps
T1835 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2227406140 Apr 04 03:03:04 PM PDT 24 Apr 04 03:03:08 PM PDT 24 100185730 ps
T1836 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.452704194 Apr 04 03:03:49 PM PDT 24 Apr 04 03:03:50 PM PDT 24 86059509 ps
T1837 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1819791066 Apr 04 01:25:06 PM PDT 24 Apr 04 01:25:08 PM PDT 24 242780486 ps
T1838 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3880743005 Apr 04 01:25:32 PM PDT 24 Apr 04 01:25:33 PM PDT 24 15642121 ps
T1839 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2019936708 Apr 04 03:03:03 PM PDT 24 Apr 04 03:03:07 PM PDT 24 54258803 ps
T1840 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3976866199 Apr 04 03:03:21 PM PDT 24 Apr 04 03:03:25 PM PDT 24 44248147 ps
T167 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.876996278 Apr 04 03:03:09 PM PDT 24 Apr 04 03:03:13 PM PDT 24 80472395 ps
T1841 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1863004244 Apr 04 01:24:27 PM PDT 24 Apr 04 01:24:32 PM PDT 24 763897317 ps
T1842 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1167018336 Apr 04 03:03:05 PM PDT 24 Apr 04 03:03:07 PM PDT 24 154625151 ps
T1843 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4286448644 Apr 04 01:24:57 PM PDT 24 Apr 04 01:25:04 PM PDT 24 702100033 ps
T1844 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.717588561 Apr 04 01:25:07 PM PDT 24 Apr 04 01:25:09 PM PDT 24 145284648 ps
T1845 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1532825121 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:37 PM PDT 24 46992610 ps
T1846 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2088041447 Apr 04 01:25:08 PM PDT 24 Apr 04 01:25:55 PM PDT 24 2137593231 ps
T1847 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2675434872 Apr 04 03:03:51 PM PDT 24 Apr 04 03:03:52 PM PDT 24 17118019 ps
T1848 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.117244674 Apr 04 03:02:54 PM PDT 24 Apr 04 03:02:55 PM PDT 24 185648829 ps
T1849 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.799670327 Apr 04 03:03:53 PM PDT 24 Apr 04 03:03:55 PM PDT 24 27328733 ps
T1850 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3961186188 Apr 04 03:03:19 PM PDT 24 Apr 04 03:03:21 PM PDT 24 39248466 ps
T1851 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4203310724 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:36 PM PDT 24 20379697 ps
T1852 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3360555122 Apr 04 03:03:38 PM PDT 24 Apr 04 03:03:40 PM PDT 24 101092174 ps
T1853 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.183163904 Apr 04 03:02:51 PM PDT 24 Apr 04 03:03:09 PM PDT 24 1290899609 ps
T160 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3494356872 Apr 04 03:02:55 PM PDT 24 Apr 04 03:02:57 PM PDT 24 164560019 ps
T1854 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1525724723 Apr 04 01:25:06 PM PDT 24 Apr 04 01:25:09 PM PDT 24 99903735 ps
T1855 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1656919479 Apr 04 01:25:07 PM PDT 24 Apr 04 01:25:08 PM PDT 24 51364767 ps
T1856 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3294787104 Apr 04 01:24:55 PM PDT 24 Apr 04 01:24:57 PM PDT 24 207322994 ps
T1857 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2375121715 Apr 04 03:02:49 PM PDT 24 Apr 04 03:03:11 PM PDT 24 3943784971 ps
T1858 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.94826662 Apr 04 01:25:08 PM PDT 24 Apr 04 01:25:10 PM PDT 24 64258036 ps
T1859 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2322208766 Apr 04 01:25:18 PM PDT 24 Apr 04 01:25:20 PM PDT 24 125746288 ps
T1860 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.130324211 Apr 04 01:25:07 PM PDT 24 Apr 04 01:25:10 PM PDT 24 345488173 ps
T1861 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.255328119 Apr 04 01:25:22 PM PDT 24 Apr 04 01:25:23 PM PDT 24 53689376 ps
T1862 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3843752319 Apr 04 01:24:27 PM PDT 24 Apr 04 01:24:29 PM PDT 24 112652855 ps
T1863 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3825233276 Apr 04 03:02:52 PM PDT 24 Apr 04 03:02:56 PM PDT 24 144030048 ps
T1864 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3132595487 Apr 04 01:24:24 PM PDT 24 Apr 04 01:24:27 PM PDT 24 95150062 ps
T164 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2653942472 Apr 04 01:25:27 PM PDT 24 Apr 04 01:25:32 PM PDT 24 247529110 ps
T1865 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4256879494 Apr 04 01:25:30 PM PDT 24 Apr 04 01:25:31 PM PDT 24 154384968 ps
T1866 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.584796647 Apr 04 01:24:38 PM PDT 24 Apr 04 01:24:39 PM PDT 24 14600569 ps
T1867 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3611651390 Apr 04 01:24:25 PM PDT 24 Apr 04 01:24:29 PM PDT 24 525727102 ps
T1868 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1124046666 Apr 04 01:25:28 PM PDT 24 Apr 04 01:25:30 PM PDT 24 110002418 ps
T1869 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.855722897 Apr 04 01:24:27 PM PDT 24 Apr 04 01:24:29 PM PDT 24 394473148 ps
T1870 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3010989828 Apr 04 03:03:14 PM PDT 24 Apr 04 03:03:18 PM PDT 24 636093673 ps
T1871 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2335361423 Apr 04 01:24:45 PM PDT 24 Apr 04 01:24:48 PM PDT 24 81306195 ps
T1872 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2647839050 Apr 04 03:03:14 PM PDT 24 Apr 04 03:03:33 PM PDT 24 20610031918 ps
T1873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.332269276 Apr 04 01:24:54 PM PDT 24 Apr 04 01:24:56 PM PDT 24 84061737 ps
T1874 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2528042038 Apr 04 03:03:51 PM PDT 24 Apr 04 03:03:52 PM PDT 24 32314997 ps
T1875 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3437181982 Apr 04 01:24:27 PM PDT 24 Apr 04 01:24:28 PM PDT 24 29323849 ps
T1876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3790210306 Apr 04 03:03:05 PM PDT 24 Apr 04 03:03:11 PM PDT 24 439381083 ps
T251 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2739714676 Apr 04 03:03:00 PM PDT 24 Apr 04 03:03:03 PM PDT 24 17626298 ps
T1877 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1809938600 Apr 04 01:24:21 PM PDT 24 Apr 04 01:24:23 PM PDT 24 17316107 ps
T1878 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.90179159 Apr 04 01:25:28 PM PDT 24 Apr 04 01:25:30 PM PDT 24 286964375 ps
T1879 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.71475271 Apr 04 01:24:18 PM PDT 24 Apr 04 01:24:25 PM PDT 24 568890659 ps
T1880 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3572883283 Apr 04 01:25:08 PM PDT 24 Apr 04 01:25:10 PM PDT 24 55280951 ps
T1881 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1947378814 Apr 04 03:03:51 PM PDT 24 Apr 04 03:03:52 PM PDT 24 24843617 ps
T1882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.194489585 Apr 04 01:24:30 PM PDT 24 Apr 04 01:24:32 PM PDT 24 61327909 ps
T1883 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3680250342 Apr 04 01:24:35 PM PDT 24 Apr 04 01:24:36 PM PDT 24 34082846 ps
T1884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.203957761 Apr 04 03:03:22 PM PDT 24 Apr 04 03:03:25 PM PDT 24 33274137 ps
T177 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1934911728 Apr 04 03:02:52 PM PDT 24 Apr 04 03:02:56 PM PDT 24 133075516 ps
T153 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1433400185 Apr 04 03:03:52 PM PDT 24 Apr 04 03:03:55 PM PDT 24 1358310545 ps
T1885 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.947532670 Apr 04 01:24:55 PM PDT 24 Apr 04 01:24:57 PM PDT 24 35952558 ps
T1886 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1375585036 Apr 04 01:25:20 PM PDT 24 Apr 04 01:25:21 PM PDT 24 34131981 ps
T1887 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3338643818 Apr 04 01:24:27 PM PDT 24 Apr 04 01:24:30 PM PDT 24 418960465 ps
T1888 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4106228066 Apr 04 01:25:27 PM PDT 24 Apr 04 01:25:30 PM PDT 24 83015579 ps
T1889 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2429133196 Apr 04 01:25:21 PM PDT 24 Apr 04 01:25:23 PM PDT 24 20405479 ps
T1890 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3132578733 Apr 04 03:03:50 PM PDT 24 Apr 04 03:03:51 PM PDT 24 63544303 ps
T1891 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.142495835 Apr 04 01:24:16 PM PDT 24 Apr 04 01:24:17 PM PDT 24 15407935 ps
T1892 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2670239560 Apr 04 03:03:00 PM PDT 24 Apr 04 03:03:03 PM PDT 24 85639538 ps
T1893 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2368534434 Apr 04 03:03:39 PM PDT 24 Apr 04 03:03:40 PM PDT 24 180788690 ps
T1894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2588915093 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:44 PM PDT 24 1139078231 ps
T1895 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3528324471 Apr 04 01:25:21 PM PDT 24 Apr 04 01:25:22 PM PDT 24 102172523 ps
T1896 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3155095374 Apr 04 01:25:30 PM PDT 24 Apr 04 01:25:31 PM PDT 24 72111041 ps
T178 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3312113116 Apr 04 03:03:56 PM PDT 24 Apr 04 03:03:59 PM PDT 24 393439419 ps
T1897 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1662077540 Apr 04 01:24:23 PM PDT 24 Apr 04 01:24:24 PM PDT 24 65772875 ps
T1898 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3475791530 Apr 04 03:03:52 PM PDT 24 Apr 04 03:03:53 PM PDT 24 87458027 ps
T183 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2433952210 Apr 04 01:25:19 PM PDT 24 Apr 04 01:25:21 PM PDT 24 69872714 ps
T1899 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2359851346 Apr 04 03:03:14 PM PDT 24 Apr 04 03:03:18 PM PDT 24 40739423 ps
T1900 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.63984217 Apr 04 03:03:53 PM PDT 24 Apr 04 03:03:54 PM PDT 24 85824271 ps
T1901 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3872201057 Apr 04 01:24:44 PM PDT 24 Apr 04 01:24:48 PM PDT 24 277261480 ps
T1902 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3519629910 Apr 04 01:24:43 PM PDT 24 Apr 04 01:24:45 PM PDT 24 26017648 ps
T1903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1574924577 Apr 04 03:03:22 PM PDT 24 Apr 04 03:03:44 PM PDT 24 3474973938 ps
T1904 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2917918703 Apr 04 03:02:56 PM PDT 24 Apr 04 03:02:58 PM PDT 24 471191158 ps
T1905 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2688445377 Apr 04 01:24:55 PM PDT 24 Apr 04 01:24:58 PM PDT 24 34389178 ps
T1906 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3534468309 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:36 PM PDT 24 14798907 ps
T1907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3062142915 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:41 PM PDT 24 430121277 ps
T1908 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3860699610 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:37 PM PDT 24 86147534 ps
T1909 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2149951542 Apr 04 03:03:36 PM PDT 24 Apr 04 03:03:37 PM PDT 24 20955203 ps
T1910 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.454416210 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:37 PM PDT 24 283751458 ps
T1911 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1942629839 Apr 04 01:25:18 PM PDT 24 Apr 04 01:25:50 PM PDT 24 2258814182 ps
T1912 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.734309760 Apr 04 03:03:52 PM PDT 24 Apr 04 03:03:56 PM PDT 24 103134861 ps
T1913 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4064107955 Apr 04 01:24:27 PM PDT 24 Apr 04 01:24:29 PM PDT 24 21081232 ps
T1914 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3180050571 Apr 04 03:03:56 PM PDT 24 Apr 04 03:03:57 PM PDT 24 18076650 ps
T1915 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.200668283 Apr 04 03:03:47 PM PDT 24 Apr 04 03:03:48 PM PDT 24 13945165 ps
T1916 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2029821268 Apr 04 01:24:15 PM PDT 24 Apr 04 01:24:16 PM PDT 24 33001228 ps
T1917 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2448317065 Apr 04 01:24:37 PM PDT 24 Apr 04 01:24:41 PM PDT 24 173662439 ps
T1918 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.931052228 Apr 04 01:24:30 PM PDT 24 Apr 04 01:24:33 PM PDT 24 102450672 ps
T1919 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.518593337 Apr 04 03:03:48 PM PDT 24 Apr 04 03:03:50 PM PDT 24 978153142 ps
T1920 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3748287280 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:37 PM PDT 24 195820522 ps
T171 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2492846863 Apr 04 01:25:19 PM PDT 24 Apr 04 01:25:21 PM PDT 24 91123865 ps
T1921 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1586015255 Apr 04 03:03:35 PM PDT 24 Apr 04 03:03:37 PM PDT 24 163081991 ps
T1922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.825562909 Apr 04 03:03:17 PM PDT 24 Apr 04 03:03:21 PM PDT 24 1530753108 ps
T1923 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3946882505 Apr 04 01:25:18 PM PDT 24 Apr 04 01:25:21 PM PDT 24 117844610 ps
T1924 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.215597486 Apr 04 03:03:55 PM PDT 24 Apr 04 03:03:56 PM PDT 24 95931841 ps
T1925 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3151007962 Apr 04 01:25:06 PM PDT 24 Apr 04 01:25:08 PM PDT 24 45630200 ps
T1926 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2413051489 Apr 04 01:25:05 PM PDT 24 Apr 04 01:25:07 PM PDT 24 587602027 ps
T1927 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3019663688 Apr 04 01:25:20 PM PDT 24 Apr 04 01:25:23 PM PDT 24 525448743 ps
T1928 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.211375877 Apr 04 01:25:19 PM PDT 24 Apr 04 01:25:20 PM PDT 24 16197023 ps
T1929 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.899894827 Apr 04 01:24:29 PM PDT 24 Apr 04 01:24:31 PM PDT 24 56109582 ps
T1930 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.253466404 Apr 04 03:03:47 PM PDT 24 Apr 04 03:03:50 PM PDT 24 268265701 ps
T1931 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.434257569 Apr 04 01:24:37 PM PDT 24 Apr 04 01:24:39 PM PDT 24 40189403 ps
T1932 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3349102027 Apr 04 03:03:02 PM PDT 24 Apr 04 03:03:03 PM PDT 24 71619252 ps
T1933 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.593324667 Apr 04 01:25:27 PM PDT 24 Apr 04 01:25:29 PM PDT 24 105677692 ps
T1934 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1031105117 Apr 04 01:25:33 PM PDT 24 Apr 04 01:25:37 PM PDT 24 223263373 ps
T1935 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1104964201 Apr 04 03:03:36 PM PDT 24 Apr 04 03:03:37 PM PDT 24 29037569 ps
T1936 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3690563813 Apr 04 01:25:26 PM PDT 24 Apr 04 01:25:29 PM PDT 24 152272809 ps
T1937 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2083278172 Apr 04 03:03:33 PM PDT 24 Apr 04 03:03:49 PM PDT 24 1870217130 ps
T1938 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2250460922 Apr 04 03:02:58 PM PDT 24 Apr 04 03:03:17 PM PDT 24 812086510 ps
T1939 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1046873765 Apr 04 01:24:37 PM PDT 24 Apr 04 01:24:40 PM PDT 24 53591363 ps
T1940 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4265198904 Apr 04 03:03:51 PM PDT 24 Apr 04 03:03:53 PM PDT 24 17091079 ps
T175 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2763309729 Apr 04 03:03:46 PM PDT 24 Apr 04 03:03:49 PM PDT 24 46035652 ps
T156 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3763533991 Apr 04 01:25:20 PM PDT 24 Apr 04 01:25:22 PM PDT 24 174085295 ps
T1941 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.468623965 Apr 04 03:03:08 PM PDT 24 Apr 04 03:03:13 PM PDT 24 532851962 ps
T1942 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2662472940 Apr 04 03:02:58 PM PDT 24 Apr 04 03:03:00 PM PDT 24 21992285 ps
T1943 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3105768939 Apr 04 03:03:03 PM PDT 24 Apr 04 03:03:05 PM PDT 24 315072384 ps
T1944 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4030208197 Apr 04 01:24:15 PM PDT 24 Apr 04 01:24:18 PM PDT 24 85410512 ps
T1945 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.26869564 Apr 04 01:24:26 PM PDT 24 Apr 04 01:24:27 PM PDT 24 41924293 ps
T1946 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.926616011 Apr 04 03:03:37 PM PDT 24 Apr 04 03:03:39 PM PDT 24 91994394 ps
T1947 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2312512538 Apr 04 01:25:26 PM PDT 24 Apr 04 01:25:27 PM PDT 24 52990304 ps
T1948 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3599784720 Apr 04 01:25:29 PM PDT 24 Apr 04 01:25:32 PM PDT 24 63179622 ps
T1949 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1793527575 Apr 04 03:03:53 PM PDT 24 Apr 04 03:03:54 PM PDT 24 36404158 ps
T1950 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.633357757 Apr 04 01:24:43 PM PDT 24 Apr 04 01:24:53 PM PDT 24 615183080 ps
T1951 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.804379015 Apr 04 01:25:06 PM PDT 24 Apr 04 01:25:07 PM PDT 24 56786671 ps
T1952 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.416421798 Apr 04 01:25:22 PM PDT 24 Apr 04 01:25:23 PM PDT 24 23037890 ps
T1953 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3265085338 Apr 04 01:25:08 PM PDT 24 Apr 04 01:25:12 PM PDT 24 845840824 ps
T1954 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.351186070 Apr 04 03:03:34 PM PDT 24 Apr 04 03:03:36 PM PDT 24 25448084 ps
T1955 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2137801627 Apr 04 03:03:49 PM PDT 24 Apr 04 03:03:51 PM PDT 24 131325447 ps
T1956 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2284413822 Apr 04 03:03:34 PM PDT 24 Apr 04 03:03:38 PM PDT 24 230496291 ps
T1957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1189160480 Apr 04 01:25:16 PM PDT 24 Apr 04 01:25:18 PM PDT 24 250980626 ps
T1958 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.164720347 Apr 04 03:03:47 PM PDT 24 Apr 04 03:03:50 PM PDT 24 133402036 ps
T1959 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3336760142 Apr 04 03:02:56 PM PDT 24 Apr 04 03:02:58 PM PDT 24 22302754 ps
T1960 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.331930661 Apr 04 01:25:22 PM PDT 24 Apr 04 01:25:23 PM PDT 24 19428451 ps
T1961 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.709474978 Apr 04 01:24:18 PM PDT 24 Apr 04 01:24:20 PM PDT 24 63950921 ps
T1962 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2664505390 Apr 04 03:03:22 PM PDT 24 Apr 04 03:03:24 PM PDT 24 29995577 ps
T1963 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.21396961 Apr 04 01:24:26 PM PDT 24 Apr 04 01:25:19 PM PDT 24 2547385529 ps
T1964 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2869572474 Apr 04 01:24:35 PM PDT 24 Apr 04 01:24:36 PM PDT 24 16450874 ps
T1965 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2576094936 Apr 04 03:03:46 PM PDT 24 Apr 04 03:03:47 PM PDT 24 35385461 ps
T1966 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3814855069 Apr 04 01:24:29 PM PDT 24 Apr 04 01:24:30 PM PDT 24 77169698 ps
T1967 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3426483939 Apr 04 01:25:07 PM PDT 24 Apr 04 01:25:16 PM PDT 24 2600759169 ps
T1968 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3073241224 Apr 04 03:03:06 PM PDT 24 Apr 04 03:03:07 PM PDT 24 57576794 ps
T1969 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1466262313 Apr 04 03:03:36 PM PDT 24 Apr 04 03:03:38 PM PDT 24 174790839 ps
T1970 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2008590230 Apr 04 01:24:56 PM PDT 24 Apr 04 01:25:00 PM PDT 24 448364472 ps
T1971 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.603535395 Apr 04 03:03:06 PM PDT 24 Apr 04 03:03:08 PM PDT 24 109212499 ps
T1972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3405887102 Apr 04 03:03:05 PM PDT 24 Apr 04 03:03:07 PM PDT 24 715280708 ps
T1973 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1761973539 Apr 04 01:25:09 PM PDT 24 Apr 04 01:25:10 PM PDT 24 40670099 ps
T1974 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4133865996 Apr 04 03:02:58 PM PDT 24 Apr 04 03:03:01 PM PDT 24 778523311 ps
T1975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1632127961 Apr 04 01:24:38 PM PDT 24 Apr 04 01:24:39 PM PDT 24 23905027 ps
T1976 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2758850101 Apr 04 01:24:26 PM PDT 24 Apr 04 01:24:29 PM PDT 24 501304767 ps
T1977 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1397532858 Apr 04 03:02:56 PM PDT 24 Apr 04 03:02:59 PM PDT 24 1400172156 ps
T1978 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1342180739 Apr 04 01:24:55 PM PDT 24 Apr 04 01:24:57 PM PDT 24 71836134 ps
T1979 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.22820557 Apr 04 03:03:32 PM PDT 24 Apr 04 03:03:34 PM PDT 24 42010388 ps
T1980 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.8644019 Apr 04 03:03:22 PM PDT 24 Apr 04 03:03:25 PM PDT 24 126907579 ps
T1981 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.74713248 Apr 04 01:24:55 PM PDT 24 Apr 04 01:24:58 PM PDT 24 327304931 ps
T1982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1073085071 Apr 04 03:03:32 PM PDT 24 Apr 04 03:03:40 PM PDT 24 16780543045 ps
T1983 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2283111347 Apr 04 03:02:52 PM PDT 24 Apr 04 03:02:55 PM PDT 24 200010812 ps
T1984 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1421807855 Apr 04 03:02:55 PM PDT 24 Apr 04 03:02:56 PM PDT 24 80397436 ps
T1985 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2785037647 Apr 04 01:25:07 PM PDT 24 Apr 04 01:25:10 PM PDT 24 55333565 ps
T1986 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.557044573 Apr 04 03:03:20 PM PDT 24 Apr 04 03:03:30 PM PDT 24 822046979 ps
T1987 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2542340183 Apr 04 01:24:37 PM PDT 24 Apr 04 01:24:39 PM PDT 24 116956985 ps
T1988 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3028646464 Apr 04 03:02:57 PM PDT 24 Apr 04 03:02:58 PM PDT 24 28526211 ps
T1989 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2665470511 Apr 04 01:24:37 PM PDT 24 Apr 04 01:24:40 PM PDT 24 83711195 ps
T150 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3585651724 Apr 04 03:03:53 PM PDT 24 Apr 04 03:03:57 PM PDT 24 70885027 ps
T161 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1578679154 Apr 04 01:24:55 PM PDT 24 Apr 04 01:24:58 PM PDT 24 65374029 ps
T1990 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2083601254 Apr 04 03:03:55 PM PDT 24 Apr 04 03:03:58 PM PDT 24 516345029 ps
T1991 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.200548987 Apr 04 01:25:07 PM PDT 24 Apr 04 01:25:09 PM PDT 24 645818621 ps
T1992 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.720995415 Apr 04 01:25:16 PM PDT 24 Apr 04 01:25:17 PM PDT 24 22893344 ps
T1993 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2981540078 Apr 04 01:25:19 PM PDT 24 Apr 04 01:25:21 PM PDT 24 79827135 ps
T1994 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.555696665 Apr 04 03:03:49 PM PDT 24 Apr 04 03:03:50 PM PDT 24 239734915 ps
T1995 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1426321012 Apr 04 03:02:56 PM PDT 24 Apr 04 03:02:57 PM PDT 24 40997108 ps
T1996 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3820833858 Apr 04 03:03:06 PM PDT 24 Apr 04 03:03:07 PM PDT 24 19541286 ps
T1997 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1874322601 Apr 04 01:24:17 PM PDT 24 Apr 04 01:24:18 PM PDT 24 22642983 ps
T1998 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1084524862 Apr 04 01:25:18 PM PDT 24 Apr 04 01:25:20 PM PDT 24 21363335 ps
T1999 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1988707519 Apr 04 03:03:38 PM PDT 24 Apr 04 03:03:41 PM PDT 24 185868025 ps
T2000 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3619877610 Apr 04 03:03:34 PM PDT 24 Apr 04 03:03:36 PM PDT 24 16613488 ps
T2001 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2933356923 Apr 04 01:25:28 PM PDT 24 Apr 04 01:25:30 PM PDT 24 88336008 ps
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