Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181025154

1

T1

142629

T2

190468

T3

24248

auto[1]

2597824

1

T1

99

T2

9496

T3

792

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181011944

1

T1

142233

T2

193836

T3

24248

auto[1]

2611034

1

T1

495

T2

6128

T3

792

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	13251574	1			T1	6688		T2	23801		T3	7821
auto[IdleSt]	41970034	1			T1	67883		T2	39576		T3	2615
auto[ClkMuxSt]	67636	1			T1	73		T2	43		T3	82
auto[CntIncrSt]	67055	1			T1	73		T2	43		T3	82
auto[CntProgSt]	3207705	1			T1	1357		T2	570		T3	384
auto[TransCheckSt]	52322	1			T1	56		T2	21		T3	51
auto[TokenHashSt]	66539784	1			T1	4269		T2	69022		T3	512
auto[FlashRmaSt]	53812	1			T1	50		T2	72		T3	37
auto[TokenCheck0St]	23600	1			T1	18		T2	21		T3	22
auto[TokenCheck1St]	17295	1			T1	9		T2	21		T3	14
auto[TransProgSt]	753699	1			T1	210		T2	242		T3	97
auto[PostTransSt]	24968960	1			T1	59722		T2	12989		T3	11321
auto[ScrapSt]	416951	1			T13	3		T14	9014		T43	3
auto[EscalateSt]	12140429	1			T1	2320		T2	28335		T3	2002
auto[InvalidSt]	20088691	1			T2	25186		T9	1556		T14	97012

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3431	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	20088691	1			T2	25186		T9	1556		T14	97012
EscalateSt	12140429	1			T1	2320		T2	28335		T3	2002
ScrapSt	416951	1			T13	3		T14	9014		T43	3
PostTransSt	24968960	1			T1	59722		T2	12989		T3	11321
TransProgSt	753699	1			T1	210		T2	242		T3	97
TokenCheck1St	17295	1			T1	9		T2	21		T3	14
TokenCheck0St	23600	1			T1	18		T2	21		T3	22
FlashRmaSt	53812	1			T1	50		T2	72		T3	37
TokenHashSt	66539784	1			T1	4269		T2	69022		T3	512
TransCheckSt	52322	1			T1	56		T2	21		T3	51
CntProgSt	3207705	1			T1	1357		T2	570		T3	384
CntIncrSt	67055	1			T1	73		T2	43		T3	82
ClkMuxSt	67636	1			T1	73		T2	43		T3	82
IdleSt	41970034	1			T1	67883		T2	39576		T3	2615
ResetSt	13251574	1			T1	6688		T2	23801		T3	7821
arcs[ResetSt=>IdleSt]	100525	1			T1	74		T2	205		T3	83
arcs[IdleSt=>ScrapSt]	508	1			T13	1		T14	5		T43	1
arcs[IdleSt=>ClkMuxSt]	67187	1			T1	73		T2	43		T3	82
arcs[ClkMuxSt=>CntIncrSt]	67055	1			T1	73		T2	43		T3	82
arcs[CntIncrSt=>PostTransSt]	3449	1			T1	11		T3	15		T4	12
arcs[CntIncrSt=>CntProgSt]	63473	1			T1	62		T2	43		T3	67
arcs[CntProgSt=>PostTransSt]	8874	1			T1	6		T2	22		T3	16
arcs[CntProgSt=>TransCheckSt]	52322	1			T1	56		T2	21		T3	51
arcs[TransCheckSt=>PostTransSt]	7311	1			T1	10		T3	4		T4	12
arcs[TransCheckSt=>TokenHashSt]	44800	1			T1	46		T2	21		T3	47
arcs[TokenHashSt=>PostTransSt]	19683	1			T1	28		T3	25		T9	8
arcs[TokenHashSt=>FlashRmaSt]	23807	1			T1	18		T2	21		T3	22
arcs[FlashRmaSt=>TokenCheck0St]	23600	1			T1	18		T2	21		T3	22
arcs[TokenCheck0St=>PostTransSt]	6253	1			T1	9		T3	8		T9	8
arcs[TokenCheck0St=>TokenCheck1St]	17295	1			T1	9		T2	21		T3	14
arcs[TokenCheck1St=>PostTransSt]	1292	1			T1	1		T14	2		T15	2
arcs[TransProgSt=>PostTransSt]	14219	1			T1	8		T2	21		T3	14
arcs[IdleSt=>EscalateSt]	400	1			T61	5		T62	5		T63	9
arcs[ClkMuxSt=>EscalateSt]	132	1			T13	3		T43	2		T29	1
arcs[CntIncrSt=>EscalateSt]	133	1			T43	2		T29	2		T61	1
arcs[CntProgSt=>EscalateSt]	2277	1			T13	9		T43	7		T29	21
arcs[TransCheckSt=>EscalateSt]	211	1			T13	9		T43	6		T29	2
arcs[TokenHashSt=>EscalateSt]	1310	1			T13	23		T43	22		T29	6
arcs[FlashRmaSt=>EscalateSt]	207	1			T13	3		T43	3		T29	2
arcs[TokenCheck0St=>EscalateSt]	52	1			T29	1		T67	1		T68	1
arcs[TokenCheck1St=>EscalateSt]	264	1			T43	2		T29	2		T61	1
arcs[TransProgSt=>EscalateSt]	1520	1			T13	10		T43	6		T29	13
arcs[PostTransSt=>EscalateSt]	9367	1			T1	6		T2	22		T3	16
arcs[InvalidSt=>EscalateSt]	24884	1			T2	136		T9	20		T14	87

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13251218	1			T1	6688		T2	23801		T3	7821
auto[0]	auto[IdleSt]	41969771	1			T1	67883		T2	39576		T3	2615
auto[0]	auto[ClkMuxSt]	67547	1			T1	73		T2	43		T3	82
auto[0]	auto[CntIncrSt]	66962	1			T1	73		T2	43		T3	82
auto[0]	auto[CntProgSt]	3206228	1			T1	1357		T2	570		T3	384
auto[0]	auto[TransCheckSt]	52177	1			T1	56		T2	21		T3	51
auto[0]	auto[TokenHashSt]	66538923	1			T1	4269		T2	69022		T3	512
auto[0]	auto[FlashRmaSt]	53678	1			T1	50		T2	72		T3	37
auto[0]	auto[TokenCheck0St]	23565	1			T1	18		T2	21		T3	22
auto[0]	auto[TokenCheck1St]	17124	1			T1	9		T2	21		T3	14
auto[0]	auto[TransProgSt]	752702	1			T1	210		T2	242		T3	97
auto[0]	auto[PostTransSt]	24964240	1			T1	59721		T2	12980		T3	11313
auto[0]	auto[ScrapSt]	416865	1			T13	3		T14	9014		T43	2
auto[0]	auto[EscalateSt]	9564493	1			T1	2222		T2	18935		T3	1218
auto[0]	auto[InvalidSt]	20076230	1			T2	25099		T9	1546		T14	96974
auto[1]	auto[ResetSt]	356	1			T13	3		T43	1		T29	4
auto[1]	auto[IdleSt]	263	1			T61	4		T62	2		T63	3
auto[1]	auto[ClkMuxSt]	89	1			T13	2		T62	1		T284	2
auto[1]	auto[CntIncrSt]	93	1			T43	2		T29	1		T61	1
auto[1]	auto[CntProgSt]	1477	1			T13	5		T43	4		T29	17
auto[1]	auto[TransCheckSt]	145	1			T13	8		T43	5		T29	1
auto[1]	auto[TokenHashSt]	861	1			T13	18		T43	14		T29	5
auto[1]	auto[FlashRmaSt]	134	1			T13	2		T43	2		T29	2
auto[1]	auto[TokenCheck0St]	35	1			T67	1		T68	1		T285	1
auto[1]	auto[TokenCheck1St]	171	1			T43	2		T29	2		T61	1
auto[1]	auto[TransProgSt]	997	1			T13	6		T43	4		T29	8
auto[1]	auto[PostTransSt]	4720	1			T1	1		T2	9		T3	8
auto[1]	auto[ScrapSt]	86	1			T43	1		T29	3		T62	2
auto[1]	auto[EscalateSt]	2575936	1			T1	98		T2	9400		T3	784
auto[1]	auto[InvalidSt]	12461	1			T2	87		T9	10		T14	38

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13251237	1			T1	6688		T2	23801		T3	7821
auto[0]	auto[IdleSt]	41969761	1			T1	67883		T2	39576		T3	2615
auto[0]	auto[ClkMuxSt]	67553	1			T1	73		T2	43		T3	82
auto[0]	auto[CntIncrSt]	66970	1			T1	73		T2	43		T3	82
auto[0]	auto[CntProgSt]	3206183	1			T1	1357		T2	570		T3	384
auto[0]	auto[TransCheckSt]	52173	1			T1	56		T2	21		T3	51
auto[0]	auto[TokenHashSt]	66538922	1			T1	4269		T2	69022		T3	512
auto[0]	auto[FlashRmaSt]	53677	1			T1	50		T2	72		T3	37
auto[0]	auto[TokenCheck0St]	23567	1			T1	18		T2	21		T3	22
auto[0]	auto[TokenCheck1St]	17123	1			T1	9		T2	21		T3	14
auto[0]	auto[TransProgSt]	752662	1			T1	210		T2	242		T3	97
auto[0]	auto[PostTransSt]	24964158	1			T1	59717		T2	12976		T3	11313
auto[0]	auto[ScrapSt]	416870	1			T13	2		T14	9014		T43	3
auto[0]	auto[EscalateSt]	9551389	1			T1	1830		T2	22269		T3	1218
auto[0]	auto[InvalidSt]	20076268	1			T2	25137		T9	1546		T14	96963
auto[1]	auto[ResetSt]	337	1			T13	4		T43	3		T29	2
auto[1]	auto[IdleSt]	273	1			T61	2		T62	3		T63	8
auto[1]	auto[ClkMuxSt]	83	1			T13	1		T43	2		T29	1
auto[1]	auto[CntIncrSt]	85	1			T43	1		T29	2		T61	1
auto[1]	auto[CntProgSt]	1522	1			T13	6		T43	5		T29	14
auto[1]	auto[TransCheckSt]	149	1			T13	8		T43	4		T29	2
auto[1]	auto[TokenHashSt]	862	1			T13	10		T43	16		T29	1
auto[1]	auto[FlashRmaSt]	135	1			T13	3		T43	2		T29	1
auto[1]	auto[TokenCheck0St]	33	1			T29	1		T67	1		T286	2
auto[1]	auto[TokenCheck1St]	172	1			T43	1		T29	2		T61	1
auto[1]	auto[TransProgSt]	1037	1			T13	7		T43	5		T29	10
auto[1]	auto[PostTransSt]	4802	1			T1	5		T2	13		T3	8
auto[1]	auto[ScrapSt]	81	1			T13	1		T29	2		T62	3
auto[1]	auto[EscalateSt]	2589040	1			T1	490		T2	6066		T3	784
auto[1]	auto[InvalidSt]	12423	1			T2	49		T9	10		T14	49