Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225374299

1

T1

13398

T2

11609

T3

23442

auto[1]

3046132

1

T1

5668

T4

6981

T13

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225358242

1

T1

12530

T2

11609

T3

23442

auto[1]

3062189

1

T1

6536

T4

8753

T13

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	16220491	1			T1	6219		T2	436		T3	6791
auto[IdleSt]	43617108	1			T1	1707		T2	6912		T3	2230
auto[ClkMuxSt]	73942	1			T1	57		T2	5		T3	73
auto[CntIncrSt]	73346	1			T1	57		T2	5		T3	73
auto[CntProgSt]	3346561	1			T1	107		T2	1494		T3	146
auto[TransCheckSt]	57438	1			T1	46		T2	5		T3	73
auto[TokenHashSt]	94856917	1			T1	864		T2	54		T3	2480
auto[FlashRmaSt]	60577	1			T1	17		T2	5		T3	104
auto[TokenCheck0St]	27105	1			T1	17		T2	5		T3	35
auto[TokenCheck1St]	20326	1			T1	17		T2	5		T3	16
auto[TransProgSt]	954498	1			T1	30		T2	1160		T4	53
auto[PostTransSt]	26277298	1			T1	18		T2	1523		T3	11421
auto[ScrapSt]	355003	1			T4	42		T12	223		T37	3
auto[EscalateSt]	15233278	1			T1	9910		T4	57706		T13	1733
auto[InvalidSt]	27241791	1			T4	125763		T21	246		T37	7051

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	4752	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	27241791	1			T4	125763		T21	246		T37	7051
EscalateSt	15233278	1			T1	9910		T4	57706		T13	1733
ScrapSt	355003	1			T4	42		T12	223		T37	3
PostTransSt	26277298	1			T1	18		T2	1523		T3	11421
TransProgSt	954498	1			T1	30		T2	1160		T4	53
TokenCheck1St	20326	1			T1	17		T2	5		T3	16
TokenCheck0St	27105	1			T1	17		T2	5		T3	35
FlashRmaSt	60577	1			T1	17		T2	5		T3	104
TokenHashSt	94856917	1			T1	864		T2	54		T3	2480
TransCheckSt	57438	1			T1	46		T2	5		T3	73
CntProgSt	3346561	1			T1	107		T2	1494		T3	146
CntIncrSt	73346	1			T1	57		T2	5		T3	73
ClkMuxSt	73942	1			T1	57		T2	5		T3	73
IdleSt	43617108	1			T1	1707		T2	6912		T3	2230
ResetSt	16220491	1			T1	6219		T2	436		T3	6791
arcs[ResetSt=>IdleSt]	116651	1			T1	58		T2	5		T3	74
arcs[IdleSt=>ScrapSt]	594	1			T4	2		T12	1		T37	2
arcs[IdleSt=>ClkMuxSt]	73473	1			T1	57		T2	5		T3	73
arcs[ClkMuxSt=>CntIncrSt]	73346	1			T1	57		T2	5		T3	73
arcs[CntIncrSt=>PostTransSt]	3678	1			T4	4		T13	9		T36	13
arcs[CntIncrSt=>CntProgSt]	69541	1			T1	56		T2	5		T3	73
arcs[CntProgSt=>PostTransSt]	10156	1			T4	17		T13	12		T36	14
arcs[CntProgSt=>TransCheckSt]	57438	1			T1	46		T2	5		T3	73
arcs[TransCheckSt=>PostTransSt]	7639	1			T3	30		T9	37		T10	41
arcs[TransCheckSt=>TokenHashSt]	49491	1			T1	42		T2	5		T3	43
arcs[TokenHashSt=>PostTransSt]	20693	1			T3	8		T9	10		T10	10
arcs[TokenHashSt=>FlashRmaSt]	27283	1			T1	17		T2	5		T3	35
arcs[FlashRmaSt=>TokenCheck0St]	27105	1			T1	17		T2	5		T3	35
arcs[TokenCheck0St=>PostTransSt]	6722	1			T3	19		T9	17		T10	26
arcs[TokenCheck0St=>TokenCheck1St]	20326	1			T1	17		T2	5		T3	16
arcs[TokenCheck1St=>PostTransSt]	1336	1			T3	16		T9	9		T10	16
arcs[TransProgSt=>PostTransSt]	17226	1			T1	11		T2	5		T4	27
arcs[IdleSt=>EscalateSt]	347	1			T49	7		T50	6		T51	9
arcs[ClkMuxSt=>EscalateSt]	127	1			T49	3		T50	1		T51	1
arcs[CntIncrSt=>EscalateSt]	127	1			T1	1		T49	2		T52	1
arcs[CntProgSt=>EscalateSt]	1947	1			T1	10		T49	10		T50	6
arcs[TransCheckSt=>EscalateSt]	308	1			T1	4		T49	5		T50	5
arcs[TokenHashSt=>EscalateSt]	1514	1			T1	25		T49	19		T50	11
arcs[FlashRmaSt=>EscalateSt]	178	1			T51	2		T52	2		T53	4
arcs[TokenCheck0St=>EscalateSt]	57	1			T52	1		T58	1		T59	1
arcs[TokenCheck1St=>EscalateSt]	280	1			T49	3		T50	3		T51	6
arcs[TransProgSt=>EscalateSt]	1484	1			T1	6		T49	9		T50	12
arcs[PostTransSt=>EscalateSt]	10735	1			T1	11		T4	18		T13	12
arcs[InvalidSt=>EscalateSt]	32752	1			T4	142		T21	3		T16	46

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	16220111	1			T1	6218		T2	436		T3	6791
auto[0]	auto[IdleSt]	43616883	1			T1	1707		T2	6912		T3	2230
auto[0]	auto[ClkMuxSt]	73854	1			T1	57		T2	5		T3	73
auto[0]	auto[CntIncrSt]	73249	1			T1	56		T2	5		T3	73
auto[0]	auto[CntProgSt]	3345242	1			T1	102		T2	1494		T3	146
auto[0]	auto[TransCheckSt]	57252	1			T1	43		T2	5		T3	73
auto[0]	auto[TokenHashSt]	94855925	1			T1	847		T2	54		T3	2480
auto[0]	auto[FlashRmaSt]	60458	1			T1	17		T2	5		T3	104
auto[0]	auto[TokenCheck0St]	27072	1			T1	17		T2	5		T3	35
auto[0]	auto[TokenCheck1St]	20137	1			T1	17		T2	5		T3	16
auto[0]	auto[TransProgSt]	953488	1			T1	30		T2	1160		T4	53
auto[0]	auto[PostTransSt]	26271864	1			T1	10		T2	1523		T3	11421
auto[0]	auto[ScrapSt]	354929	1			T4	42		T12	223		T37	3
auto[0]	auto[EscalateSt]	12213494	1			T1	4277		T4	50796		T13	1145
auto[0]	auto[InvalidSt]	27225589	1			T4	125701		T21	245		T37	7051
auto[1]	auto[ResetSt]	380	1			T1	1		T49	2		T50	8
auto[1]	auto[IdleSt]	225	1			T49	3		T50	6		T51	7
auto[1]	auto[ClkMuxSt]	88	1			T49	2		T50	1		T53	1
auto[1]	auto[CntIncrSt]	97	1			T1	1		T49	2		T239	2
auto[1]	auto[CntProgSt]	1319	1			T1	5		T49	8		T50	5
auto[1]	auto[TransCheckSt]	186	1			T1	3		T49	3		T50	4
auto[1]	auto[TokenHashSt]	992	1			T1	17		T49	14		T50	10
auto[1]	auto[FlashRmaSt]	119	1			T51	2		T52	2		T53	3
auto[1]	auto[TokenCheck0St]	33	1			T58	1		T240	1		T241	1
auto[1]	auto[TokenCheck1St]	189	1			T49	3		T50	3		T51	2
auto[1]	auto[TransProgSt]	1010	1			T49	5		T50	9		T51	18
auto[1]	auto[PostTransSt]	5434	1			T1	8		T4	9		T13	6
auto[1]	auto[ScrapSt]	74	1			T50	1		T242	2		T243	1
auto[1]	auto[EscalateSt]	3019784	1			T1	5633		T4	6910		T13	588
auto[1]	auto[InvalidSt]	16202	1			T4	62		T21	1		T16	18

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	16220133	1			T1	6217		T2	436		T3	6791
auto[0]	auto[IdleSt]	43616860	1			T1	1707		T2	6912		T3	2230
auto[0]	auto[ClkMuxSt]	73865	1			T1	57		T2	5		T3	73
auto[0]	auto[CntIncrSt]	73269	1			T1	56		T2	5		T3	73
auto[0]	auto[CntProgSt]	3345272	1			T1	100		T2	1494		T3	146
auto[0]	auto[TransCheckSt]	57229	1			T1	45		T2	5		T3	73
auto[0]	auto[TokenHashSt]	94855937	1			T1	849		T2	54		T3	2480
auto[0]	auto[FlashRmaSt]	60464	1			T1	17		T2	5		T3	104
auto[0]	auto[TokenCheck0St]	27063	1			T1	17		T2	5		T3	35
auto[0]	auto[TokenCheck1St]	20157	1			T1	17		T2	5		T3	16
auto[0]	auto[TransProgSt]	953537	1			T1	24		T2	1160		T4	53
auto[0]	auto[PostTransSt]	26271809	1			T1	11		T2	1523		T3	11421
auto[0]	auto[ScrapSt]	354940	1			T4	42		T12	223		T37	3
auto[0]	auto[EscalateSt]	12197714	1			T1	3413		T4	49042		T13	1145
auto[0]	auto[InvalidSt]	27225241	1			T4	125683		T21	244		T37	7051
auto[1]	auto[ResetSt]	358	1			T1	2		T49	2		T50	5
auto[1]	auto[IdleSt]	248	1			T49	6		T50	2		T51	7
auto[1]	auto[ClkMuxSt]	77	1			T49	2		T51	1		T244	1
auto[1]	auto[CntIncrSt]	77	1			T1	1		T49	2		T52	1
auto[1]	auto[CntProgSt]	1289	1			T1	7		T49	4		T50	4
auto[1]	auto[TransCheckSt]	209	1			T1	1		T49	3		T50	4
auto[1]	auto[TokenHashSt]	980	1			T1	15		T49	12		T50	4
auto[1]	auto[FlashRmaSt]	113	1			T51	2		T52	1		T53	2
auto[1]	auto[TokenCheck0St]	42	1			T52	1		T59	1		T240	1
auto[1]	auto[TokenCheck1St]	169	1			T49	3		T50	1		T51	6
auto[1]	auto[TransProgSt]	961	1			T1	6		T49	7		T50	7
auto[1]	auto[PostTransSt]	5489	1			T1	7		T4	9		T13	6
auto[1]	auto[ScrapSt]	63	1			T52	1		T54	1		T244	1
auto[1]	auto[EscalateSt]	3035564	1			T1	6497		T4	8664		T13	588
auto[1]	auto[InvalidSt]	16550	1			T4	80		T21	2		T16	28