| T143 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1730291346 |
|
|
Apr 16 02:28:14 PM PDT 24 |
Apr 16 02:28:17 PM PDT 24 |
159890770 ps |
| T1781 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.446409249 |
|
|
Apr 16 12:21:50 PM PDT 24 |
Apr 16 12:21:54 PM PDT 24 |
185209822 ps |
| T1782 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2724012808 |
|
|
Apr 16 12:24:17 PM PDT 24 |
Apr 16 12:24:21 PM PDT 24 |
168216031 ps |
| T1783 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.955209815 |
|
|
Apr 16 02:28:29 PM PDT 24 |
Apr 16 02:28:31 PM PDT 24 |
14620221 ps |
| T1784 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3673290334 |
|
|
Apr 16 12:24:37 PM PDT 24 |
Apr 16 12:24:41 PM PDT 24 |
71899709 ps |
| T123 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3566016009 |
|
|
Apr 16 12:24:34 PM PDT 24 |
Apr 16 12:24:39 PM PDT 24 |
157773073 ps |
| T209 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3049114697 |
|
|
Apr 16 12:24:22 PM PDT 24 |
Apr 16 12:24:27 PM PDT 24 |
180413711 ps |
| T210 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2958843633 |
|
|
Apr 16 12:24:25 PM PDT 24 |
Apr 16 12:24:29 PM PDT 24 |
15341804 ps |
| T1785 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2801954205 |
|
|
Apr 16 12:24:22 PM PDT 24 |
Apr 16 12:24:28 PM PDT 24 |
277698251 ps |
| T1786 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3002384117 |
|
|
Apr 16 12:24:24 PM PDT 24 |
Apr 16 12:24:29 PM PDT 24 |
90333323 ps |
| T1787 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1222826631 |
|
|
Apr 16 02:28:12 PM PDT 24 |
Apr 16 02:28:15 PM PDT 24 |
137834637 ps |
| T1788 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.130989759 |
|
|
Apr 16 02:28:52 PM PDT 24 |
Apr 16 02:28:54 PM PDT 24 |
58253025 ps |
| T1789 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2868869244 |
|
|
Apr 16 12:24:32 PM PDT 24 |
Apr 16 12:24:36 PM PDT 24 |
25672858 ps |
| T1790 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2471977165 |
|
|
Apr 16 12:24:37 PM PDT 24 |
Apr 16 12:24:42 PM PDT 24 |
264919939 ps |
| T1791 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3537880819 |
|
|
Apr 16 02:28:01 PM PDT 24 |
Apr 16 02:28:06 PM PDT 24 |
395716947 ps |
| T1792 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2775662333 |
|
|
Apr 16 02:28:55 PM PDT 24 |
Apr 16 02:28:59 PM PDT 24 |
142894673 ps |
| T125 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.635783445 |
|
|
Apr 16 02:28:24 PM PDT 24 |
Apr 16 02:28:28 PM PDT 24 |
222828640 ps |
| T1793 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.587716756 |
|
|
Apr 16 12:24:26 PM PDT 24 |
Apr 16 12:24:32 PM PDT 24 |
52120097 ps |
| T1794 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2171330924 |
|
|
Apr 16 02:28:35 PM PDT 24 |
Apr 16 02:28:37 PM PDT 24 |
21753221 ps |
| T1795 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.636753880 |
|
|
Apr 16 02:28:49 PM PDT 24 |
Apr 16 02:28:53 PM PDT 24 |
199889336 ps |
| T142 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.652507002 |
|
|
Apr 16 12:24:39 PM PDT 24 |
Apr 16 12:24:44 PM PDT 24 |
233948595 ps |
| T1796 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1119510858 |
|
|
Apr 16 12:24:27 PM PDT 24 |
Apr 16 12:24:32 PM PDT 24 |
583921114 ps |
| T1797 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1288947789 |
|
|
Apr 16 12:24:33 PM PDT 24 |
Apr 16 12:24:39 PM PDT 24 |
140037773 ps |
| T1798 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3750301253 |
|
|
Apr 16 12:24:19 PM PDT 24 |
Apr 16 12:24:24 PM PDT 24 |
107012805 ps |
| T1799 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.416599796 |
|
|
Apr 16 02:28:54 PM PDT 24 |
Apr 16 02:28:56 PM PDT 24 |
16783336 ps |
| T1800 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2690415400 |
|
|
Apr 16 02:28:13 PM PDT 24 |
Apr 16 02:28:24 PM PDT 24 |
788229115 ps |
| T1801 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3797365929 |
|
|
Apr 16 02:28:24 PM PDT 24 |
Apr 16 02:28:26 PM PDT 24 |
27690425 ps |
| T1802 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2747981936 |
|
|
Apr 16 02:28:41 PM PDT 24 |
Apr 16 02:28:43 PM PDT 24 |
58832291 ps |
| T1803 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1480520988 |
|
|
Apr 16 02:28:24 PM PDT 24 |
Apr 16 02:28:26 PM PDT 24 |
211536589 ps |
| T1804 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3949761900 |
|
|
Apr 16 12:24:13 PM PDT 24 |
Apr 16 12:24:16 PM PDT 24 |
250624997 ps |
| T133 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2801520963 |
|
|
Apr 16 02:28:59 PM PDT 24 |
Apr 16 02:29:02 PM PDT 24 |
55900015 ps |
| T1805 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2533291081 |
|
|
Apr 16 12:24:34 PM PDT 24 |
Apr 16 12:24:38 PM PDT 24 |
34484142 ps |
| T1806 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.964659472 |
|
|
Apr 16 02:29:15 PM PDT 24 |
Apr 16 02:29:17 PM PDT 24 |
233727779 ps |
| T140 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3604873670 |
|
|
Apr 16 02:28:54 PM PDT 24 |
Apr 16 02:28:58 PM PDT 24 |
57573584 ps |
| T1807 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3020083281 |
|
|
Apr 16 12:24:19 PM PDT 24 |
Apr 16 12:24:24 PM PDT 24 |
46472544 ps |
| T1808 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1840251160 |
|
|
Apr 16 12:24:31 PM PDT 24 |
Apr 16 12:24:35 PM PDT 24 |
59483477 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.364078394 |
|
|
Apr 16 12:24:28 PM PDT 24 |
Apr 16 12:24:34 PM PDT 24 |
180233880 ps |
| T1809 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3898927701 |
|
|
Apr 16 12:18:53 PM PDT 24 |
Apr 16 12:18:55 PM PDT 24 |
17214101 ps |
| T1810 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3832414085 |
|
|
Apr 16 12:17:55 PM PDT 24 |
Apr 16 12:17:57 PM PDT 24 |
46016271 ps |
| T122 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.377212505 |
|
|
Apr 16 12:21:13 PM PDT 24 |
Apr 16 12:21:18 PM PDT 24 |
73067502 ps |
| T1811 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2085379213 |
|
|
Apr 16 12:24:25 PM PDT 24 |
Apr 16 12:24:30 PM PDT 24 |
45339410 ps |
| T1812 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3284736626 |
|
|
Apr 16 02:28:30 PM PDT 24 |
Apr 16 02:28:31 PM PDT 24 |
22693330 ps |
| T130 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1594381352 |
|
|
Apr 16 02:28:49 PM PDT 24 |
Apr 16 02:28:56 PM PDT 24 |
331605593 ps |
| T1813 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4048376888 |
|
|
Apr 16 02:28:34 PM PDT 24 |
Apr 16 02:28:37 PM PDT 24 |
63342491 ps |
| T1814 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4165326213 |
|
|
Apr 16 02:27:59 PM PDT 24 |
Apr 16 02:28:01 PM PDT 24 |
60180017 ps |
| T1815 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1324743593 |
|
|
Apr 16 02:28:39 PM PDT 24 |
Apr 16 02:28:41 PM PDT 24 |
16360609 ps |
| T1816 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.346934487 |
|
|
Apr 16 02:28:41 PM PDT 24 |
Apr 16 02:28:43 PM PDT 24 |
21061459 ps |
| T1817 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3387811042 |
|
|
Apr 16 12:26:09 PM PDT 24 |
Apr 16 12:26:34 PM PDT 24 |
6460932303 ps |
| T1818 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3965122011 |
|
|
Apr 16 12:20:51 PM PDT 24 |
Apr 16 12:20:55 PM PDT 24 |
94503964 ps |
| T1819 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3695775929 |
|
|
Apr 16 02:27:52 PM PDT 24 |
Apr 16 02:27:54 PM PDT 24 |
70864143 ps |
| T1820 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4049957923 |
|
|
Apr 16 02:29:10 PM PDT 24 |
Apr 16 02:29:14 PM PDT 24 |
365809659 ps |
| T1821 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1758594201 |
|
|
Apr 16 12:24:30 PM PDT 24 |
Apr 16 12:24:35 PM PDT 24 |
230495359 ps |
| T1822 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1115281742 |
|
|
Apr 16 12:22:56 PM PDT 24 |
Apr 16 12:23:00 PM PDT 24 |
23591330 ps |
| T149 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.164504914 |
|
|
Apr 16 12:24:26 PM PDT 24 |
Apr 16 12:24:32 PM PDT 24 |
242840141 ps |
| T1823 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.354445748 |
|
|
Apr 16 12:24:18 PM PDT 24 |
Apr 16 12:24:28 PM PDT 24 |
26799829 ps |
| T1824 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3367158035 |
|
|
Apr 16 02:28:36 PM PDT 24 |
Apr 16 02:28:39 PM PDT 24 |
200935687 ps |
| T1825 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3778193607 |
|
|
Apr 16 12:24:21 PM PDT 24 |
Apr 16 12:24:29 PM PDT 24 |
92196527 ps |
| T1826 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.163068331 |
|
|
Apr 16 02:28:38 PM PDT 24 |
Apr 16 02:28:46 PM PDT 24 |
3895811972 ps |
| T1827 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2091651400 |
|
|
Apr 16 02:28:41 PM PDT 24 |
Apr 16 02:28:45 PM PDT 24 |
1101742983 ps |
| T1828 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.256288164 |
|
|
Apr 16 02:28:49 PM PDT 24 |
Apr 16 02:28:54 PM PDT 24 |
605899429 ps |
| T1829 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.391215949 |
|
|
Apr 16 12:24:16 PM PDT 24 |
Apr 16 12:24:20 PM PDT 24 |
193849334 ps |
| T1830 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1809705141 |
|
|
Apr 16 12:24:17 PM PDT 24 |
Apr 16 12:24:26 PM PDT 24 |
292790047 ps |
| T1831 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2686159234 |
|
|
Apr 16 12:21:13 PM PDT 24 |
Apr 16 12:21:16 PM PDT 24 |
22368047 ps |
| T1832 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1918419898 |
|
|
Apr 16 12:24:18 PM PDT 24 |
Apr 16 12:24:23 PM PDT 24 |
17996167 ps |
| T1833 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3313937288 |
|
|
Apr 16 02:28:03 PM PDT 24 |
Apr 16 02:28:06 PM PDT 24 |
231049279 ps |
| T1834 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2392648480 |
|
|
Apr 16 12:26:08 PM PDT 24 |
Apr 16 12:26:17 PM PDT 24 |
450590354 ps |
| T1835 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.785311215 |
|
|
Apr 16 12:24:29 PM PDT 24 |
Apr 16 12:24:34 PM PDT 24 |
136553369 ps |
| T134 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3744944860 |
|
|
Apr 16 12:21:41 PM PDT 24 |
Apr 16 12:21:46 PM PDT 24 |
119678961 ps |
| T1836 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3080357814 |
|
|
Apr 16 02:28:50 PM PDT 24 |
Apr 16 02:28:59 PM PDT 24 |
674239776 ps |
| T211 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.165367331 |
|
|
Apr 16 12:24:30 PM PDT 24 |
Apr 16 12:24:34 PM PDT 24 |
40893379 ps |
| T1837 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.476995755 |
|
|
Apr 16 02:29:03 PM PDT 24 |
Apr 16 02:29:04 PM PDT 24 |
30391981 ps |
| T1838 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1073390787 |
|
|
Apr 16 12:24:18 PM PDT 24 |
Apr 16 12:24:22 PM PDT 24 |
21325474 ps |
| T1839 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4193853843 |
|
|
Apr 16 12:24:18 PM PDT 24 |
Apr 16 12:24:23 PM PDT 24 |
46084866 ps |
| T1840 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.586228326 |
|
|
Apr 16 12:24:36 PM PDT 24 |
Apr 16 12:24:46 PM PDT 24 |
497617563 ps |
| T1841 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.769414277 |
|
|
Apr 16 12:24:38 PM PDT 24 |
Apr 16 12:24:42 PM PDT 24 |
20006725 ps |
| T1842 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.202991653 |
|
|
Apr 16 02:27:54 PM PDT 24 |
Apr 16 02:27:58 PM PDT 24 |
405640480 ps |
| T1843 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.205034363 |
|
|
Apr 16 12:24:24 PM PDT 24 |
Apr 16 12:24:30 PM PDT 24 |
98715348 ps |
| T147 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.268340682 |
|
|
Apr 16 02:28:47 PM PDT 24 |
Apr 16 02:28:50 PM PDT 24 |
98505424 ps |
| T212 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3493772267 |
|
|
Apr 16 02:28:36 PM PDT 24 |
Apr 16 02:28:38 PM PDT 24 |
36890861 ps |
| T1844 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2277094956 |
|
|
Apr 16 12:24:41 PM PDT 24 |
Apr 16 12:24:44 PM PDT 24 |
21378363 ps |
| T213 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1243898563 |
|
|
Apr 16 02:28:13 PM PDT 24 |
Apr 16 02:28:15 PM PDT 24 |
44283781 ps |
| T214 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.949896831 |
|
|
Apr 16 02:28:54 PM PDT 24 |
Apr 16 02:28:56 PM PDT 24 |
59942489 ps |
| T1845 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3649122399 |
|
|
Apr 16 02:28:25 PM PDT 24 |
Apr 16 02:28:27 PM PDT 24 |
197043376 ps |
| T1846 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.597581799 |
|
|
Apr 16 02:28:39 PM PDT 24 |
Apr 16 02:28:40 PM PDT 24 |
14751830 ps |
| T1847 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3228750288 |
|
|
Apr 16 12:24:27 PM PDT 24 |
Apr 16 12:24:31 PM PDT 24 |
16725419 ps |
| T1848 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2132735412 |
|
|
Apr 16 02:28:35 PM PDT 24 |
Apr 16 02:28:38 PM PDT 24 |
232858955 ps |
| T1849 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3181425218 |
|
|
Apr 16 12:24:34 PM PDT 24 |
Apr 16 12:24:38 PM PDT 24 |
23873366 ps |
| T1850 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3223705518 |
|
|
Apr 16 02:27:54 PM PDT 24 |
Apr 16 02:28:00 PM PDT 24 |
150562024 ps |
| T1851 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2754253251 |
|
|
Apr 16 02:28:37 PM PDT 24 |
Apr 16 02:28:38 PM PDT 24 |
40181450 ps |
| T1852 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4007847382 |
|
|
Apr 16 02:28:59 PM PDT 24 |
Apr 16 02:29:01 PM PDT 24 |
69759114 ps |
| T1853 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.166038994 |
|
|
Apr 16 12:24:36 PM PDT 24 |
Apr 16 12:24:40 PM PDT 24 |
171471949 ps |
| T1854 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3041007261 |
|
|
Apr 16 02:28:40 PM PDT 24 |
Apr 16 02:28:42 PM PDT 24 |
46915757 ps |
| T1855 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3270104870 |
|
|
Apr 16 02:29:03 PM PDT 24 |
Apr 16 02:29:04 PM PDT 24 |
25335599 ps |
| T1856 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3300787109 |
|
|
Apr 16 12:21:51 PM PDT 24 |
Apr 16 12:21:57 PM PDT 24 |
91963092 ps |
| T1857 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.755127886 |
|
|
Apr 16 12:24:13 PM PDT 24 |
Apr 16 12:24:18 PM PDT 24 |
153636097 ps |
| T1858 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3221003749 |
|
|
Apr 16 12:24:28 PM PDT 24 |
Apr 16 12:24:33 PM PDT 24 |
91241017 ps |
| T1859 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.976511599 |
|
|
Apr 16 02:29:02 PM PDT 24 |
Apr 16 02:29:04 PM PDT 24 |
26086705 ps |
| T1860 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1266067520 |
|
|
Apr 16 02:28:30 PM PDT 24 |
Apr 16 02:28:32 PM PDT 24 |
35403695 ps |
| T1861 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1290480766 |
|
|
Apr 16 02:28:40 PM PDT 24 |
Apr 16 02:28:43 PM PDT 24 |
61231101 ps |
| T1862 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2788507641 |
|
|
Apr 16 02:29:04 PM PDT 24 |
Apr 16 02:29:05 PM PDT 24 |
22339856 ps |
| T1863 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.169299515 |
|
|
Apr 16 12:24:25 PM PDT 24 |
Apr 16 12:24:31 PM PDT 24 |
103972683 ps |
| T1864 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1995446728 |
|
|
Apr 16 12:24:31 PM PDT 24 |
Apr 16 12:24:36 PM PDT 24 |
97485487 ps |
| T1865 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1159157592 |
|
|
Apr 16 12:21:05 PM PDT 24 |
Apr 16 12:21:09 PM PDT 24 |
54734509 ps |
| T1866 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3306520089 |
|
|
Apr 16 12:24:37 PM PDT 24 |
Apr 16 12:24:40 PM PDT 24 |
94664174 ps |
| T1867 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3144852406 |
|
|
Apr 16 02:27:59 PM PDT 24 |
Apr 16 02:28:02 PM PDT 24 |
243382343 ps |
| T118 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1916492200 |
|
|
Apr 16 12:24:23 PM PDT 24 |
Apr 16 12:24:30 PM PDT 24 |
510484746 ps |
| T1868 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4169210064 |
|
|
Apr 16 02:28:37 PM PDT 24 |
Apr 16 02:28:41 PM PDT 24 |
85977627 ps |
| T1869 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3467497477 |
|
|
Apr 16 02:29:08 PM PDT 24 |
Apr 16 02:29:09 PM PDT 24 |
12978654 ps |
| T1870 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2800442966 |
|
|
Apr 16 02:28:37 PM PDT 24 |
Apr 16 02:28:39 PM PDT 24 |
37285351 ps |
| T1871 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2064836296 |
|
|
Apr 16 02:29:14 PM PDT 24 |
Apr 16 02:29:18 PM PDT 24 |
41409407 ps |
| T1872 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2005585894 |
|
|
Apr 16 02:28:59 PM PDT 24 |
Apr 16 02:29:01 PM PDT 24 |
12533116 ps |
| T1873 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.936601549 |
|
|
Apr 16 12:24:23 PM PDT 24 |
Apr 16 12:24:28 PM PDT 24 |
62222727 ps |
| T1874 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2002772272 |
|
|
Apr 16 02:28:47 PM PDT 24 |
Apr 16 02:28:49 PM PDT 24 |
61681254 ps |
| T1875 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.994649358 |
|
|
Apr 16 12:24:24 PM PDT 24 |
Apr 16 12:24:28 PM PDT 24 |
12863167 ps |
| T1876 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2930495636 |
|
|
Apr 16 02:28:50 PM PDT 24 |
Apr 16 02:29:03 PM PDT 24 |
618591432 ps |
| T148 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3015256552 |
|
|
Apr 16 12:24:36 PM PDT 24 |
Apr 16 12:24:43 PM PDT 24 |
230520433 ps |
| T1877 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.708279907 |
|
|
Apr 16 02:28:46 PM PDT 24 |
Apr 16 02:28:48 PM PDT 24 |
108334886 ps |
| T1878 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2520488042 |
|
|
Apr 16 12:24:34 PM PDT 24 |
Apr 16 12:24:39 PM PDT 24 |
326241425 ps |
| T1879 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1119216622 |
|
|
Apr 16 12:24:26 PM PDT 24 |
Apr 16 12:24:31 PM PDT 24 |
17187239 ps |
| T1880 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2407124575 |
|
|
Apr 16 12:24:33 PM PDT 24 |
Apr 16 12:24:38 PM PDT 24 |
23418241 ps |
| T1881 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3041231051 |
|
|
Apr 16 02:28:45 PM PDT 24 |
Apr 16 02:28:48 PM PDT 24 |
878113380 ps |
| T1882 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2543686344 |
|
|
Apr 16 12:21:14 PM PDT 24 |
Apr 16 12:21:20 PM PDT 24 |
186454004 ps |
| T1883 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1284085837 |
|
|
Apr 16 12:24:14 PM PDT 24 |
Apr 16 12:24:19 PM PDT 24 |
774802745 ps |
| T1884 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2930577274 |
|
|
Apr 16 02:27:59 PM PDT 24 |
Apr 16 02:28:36 PM PDT 24 |
1750759334 ps |
| T1885 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.954817593 |
|
|
Apr 16 02:28:12 PM PDT 24 |
Apr 16 02:28:23 PM PDT 24 |
4732052533 ps |
| T1886 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3425817097 |
|
|
Apr 16 02:28:35 PM PDT 24 |
Apr 16 02:28:37 PM PDT 24 |
112272515 ps |
| T1887 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3910265198 |
|
|
Apr 16 12:24:23 PM PDT 24 |
Apr 16 12:24:40 PM PDT 24 |
3676527853 ps |
| T1888 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4100072575 |
|
|
Apr 16 12:24:25 PM PDT 24 |
Apr 16 12:24:31 PM PDT 24 |
133612171 ps |
| T1889 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.962414211 |
|
|
Apr 16 02:28:23 PM PDT 24 |
Apr 16 02:28:24 PM PDT 24 |
22038842 ps |
| T1890 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.82512895 |
|
|
Apr 16 12:24:35 PM PDT 24 |
Apr 16 12:24:40 PM PDT 24 |
729425014 ps |
| T1891 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2768229349 |
|
|
Apr 16 12:24:28 PM PDT 24 |
Apr 16 12:24:33 PM PDT 24 |
55599068 ps |
| T1892 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2038778952 |
|
|
Apr 16 02:28:40 PM PDT 24 |
Apr 16 02:28:42 PM PDT 24 |
453915800 ps |
| T1893 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.152241775 |
|
|
Apr 16 12:24:18 PM PDT 24 |
Apr 16 12:24:24 PM PDT 24 |
211687069 ps |
| T1894 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.324134330 |
|
|
Apr 16 02:28:40 PM PDT 24 |
Apr 16 02:28:42 PM PDT 24 |
26450698 ps |
| T1895 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3381251556 |
|
|
Apr 16 12:24:19 PM PDT 24 |
Apr 16 12:24:23 PM PDT 24 |
49833134 ps |
| T215 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1375100136 |
|
|
Apr 16 02:29:10 PM PDT 24 |
Apr 16 02:29:12 PM PDT 24 |
12278077 ps |
| T1896 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1124866300 |
|
|
Apr 16 02:28:55 PM PDT 24 |
Apr 16 02:29:00 PM PDT 24 |
439287280 ps |
| T1897 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3304752947 |
|
|
Apr 16 02:29:17 PM PDT 24 |
Apr 16 02:29:18 PM PDT 24 |
11972244 ps |
| T1898 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3659843608 |
|
|
Apr 16 02:28:36 PM PDT 24 |
Apr 16 02:28:40 PM PDT 24 |
1606737333 ps |
| T1899 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.860372091 |
|
|
Apr 16 02:27:58 PM PDT 24 |
Apr 16 02:27:59 PM PDT 24 |
11544863 ps |
| T1900 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1047927568 |
|
|
Apr 16 12:24:20 PM PDT 24 |
Apr 16 12:24:25 PM PDT 24 |
29179562 ps |
| T1901 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2804989102 |
|
|
Apr 16 02:28:22 PM PDT 24 |
Apr 16 02:28:29 PM PDT 24 |
1115657288 ps |
| T1902 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1393178722 |
|
|
Apr 16 12:24:20 PM PDT 24 |
Apr 16 12:24:33 PM PDT 24 |
1623336752 ps |
| T1903 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2162074080 |
|
|
Apr 16 02:28:12 PM PDT 24 |
Apr 16 02:28:14 PM PDT 24 |
36662074 ps |
| T1904 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1655675778 |
|
|
Apr 16 12:24:25 PM PDT 24 |
Apr 16 12:24:32 PM PDT 24 |
558605561 ps |
| T1905 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3846952206 |
|
|
Apr 16 02:28:37 PM PDT 24 |
Apr 16 02:28:48 PM PDT 24 |
749747458 ps |
| T126 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1705644899 |
|
|
Apr 16 12:24:34 PM PDT 24 |
Apr 16 12:24:41 PM PDT 24 |
2059627074 ps |
| T1906 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3871892434 |
|
|
Apr 16 02:28:41 PM PDT 24 |
Apr 16 02:28:45 PM PDT 24 |
261259227 ps |
| T1907 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3327448759 |
|
|
Apr 16 12:21:45 PM PDT 24 |
Apr 16 12:21:49 PM PDT 24 |
15947453 ps |
| T1908 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1733951436 |
|
|
Apr 16 12:24:07 PM PDT 24 |
Apr 16 12:24:11 PM PDT 24 |
44767613 ps |
| T1909 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1430441077 |
|
|
Apr 16 12:26:07 PM PDT 24 |
Apr 16 12:26:11 PM PDT 24 |
25675879 ps |
| T1910 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1789913973 |
|
|
Apr 16 02:28:17 PM PDT 24 |
Apr 16 02:28:22 PM PDT 24 |
130237653 ps |
| T1911 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.867079813 |
|
|
Apr 16 12:24:24 PM PDT 24 |
Apr 16 12:24:42 PM PDT 24 |
2824219850 ps |
| T1912 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3286983614 |
|
|
Apr 16 12:24:18 PM PDT 24 |
Apr 16 12:24:23 PM PDT 24 |
304115065 ps |
| T1913 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2825682118 |
|
|
Apr 16 02:28:25 PM PDT 24 |
Apr 16 02:28:29 PM PDT 24 |
401626051 ps |
| T1914 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2206385805 |
|
|
Apr 16 02:28:59 PM PDT 24 |
Apr 16 02:29:02 PM PDT 24 |
849960971 ps |
| T135 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4154199204 |
|
|
Apr 16 02:27:58 PM PDT 24 |
Apr 16 02:28:02 PM PDT 24 |
573966377 ps |
| T1915 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3827527444 |
|
|
Apr 16 12:24:19 PM PDT 24 |
Apr 16 12:24:23 PM PDT 24 |
44472973 ps |
| T1916 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3265445009 |
|
|
Apr 16 02:28:40 PM PDT 24 |
Apr 16 02:28:58 PM PDT 24 |
2149977732 ps |
| T1917 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2766900367 |
|
|
Apr 16 12:24:22 PM PDT 24 |
Apr 16 12:24:27 PM PDT 24 |
29031470 ps |
| T1918 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3046657399 |
|
|
Apr 16 12:21:13 PM PDT 24 |
Apr 16 12:21:16 PM PDT 24 |
60769429 ps |
| T1919 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3415135604 |
|
|
Apr 16 12:24:21 PM PDT 24 |
Apr 16 12:24:25 PM PDT 24 |
15447073 ps |
| T1920 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3402705618 |
|
|
Apr 16 02:29:01 PM PDT 24 |
Apr 16 02:29:05 PM PDT 24 |
45611459 ps |
| T1921 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4099336880 |
|
|
Apr 16 02:28:30 PM PDT 24 |
Apr 16 02:28:38 PM PDT 24 |
1920223361 ps |
| T1922 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.735826967 |
|
|
Apr 16 02:28:50 PM PDT 24 |
Apr 16 02:28:53 PM PDT 24 |
492394304 ps |
| T1923 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2022159484 |
|
|
Apr 16 12:24:25 PM PDT 24 |
Apr 16 12:24:29 PM PDT 24 |
129673088 ps |
| T1924 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3178447261 |
|
|
Apr 16 02:28:59 PM PDT 24 |
Apr 16 02:29:01 PM PDT 24 |
312589601 ps |
| T1925 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2836222589 |
|
|
Apr 16 02:28:39 PM PDT 24 |
Apr 16 02:28:44 PM PDT 24 |
501914942 ps |
| T1926 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2976179643 |
|
|
Apr 16 12:24:31 PM PDT 24 |
Apr 16 12:24:38 PM PDT 24 |
307414525 ps |
| T1927 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2314866654 |
|
|
Apr 16 12:17:59 PM PDT 24 |
Apr 16 12:18:15 PM PDT 24 |
940176326 ps |
| T136 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.577651856 |
|
|
Apr 16 02:29:07 PM PDT 24 |
Apr 16 02:29:10 PM PDT 24 |
158251901 ps |
| T1928 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3258965775 |
|
|
Apr 16 12:24:29 PM PDT 24 |
Apr 16 12:24:35 PM PDT 24 |
326833053 ps |
| T1929 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2674215310 |
|
|
Apr 16 02:29:18 PM PDT 24 |
Apr 16 02:29:21 PM PDT 24 |
92640494 ps |
| T1930 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.284088748 |
|
|
Apr 16 12:26:04 PM PDT 24 |
Apr 16 12:26:08 PM PDT 24 |
135334919 ps |
| T1931 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1000584819 |
|
|
Apr 16 02:27:54 PM PDT 24 |
Apr 16 02:27:56 PM PDT 24 |
54670858 ps |
| T127 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.212064548 |
|
|
Apr 16 12:24:30 PM PDT 24 |
Apr 16 12:24:36 PM PDT 24 |
305454655 ps |
| T1932 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1092349703 |
|
|
Apr 16 12:24:36 PM PDT 24 |
Apr 16 12:24:44 PM PDT 24 |
158818763 ps |
| T1933 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.475175117 |
|
|
Apr 16 02:28:57 PM PDT 24 |
Apr 16 02:28:59 PM PDT 24 |
23970593 ps |
| T1934 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2008568997 |
|
|
Apr 16 12:21:01 PM PDT 24 |
Apr 16 12:21:09 PM PDT 24 |
253930592 ps |
| T1935 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2906666367 |
|
|
Apr 16 12:24:34 PM PDT 24 |
Apr 16 12:24:38 PM PDT 24 |
127716321 ps |
| T1936 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3146376192 |
|
|
Apr 16 02:28:28 PM PDT 24 |
Apr 16 02:28:30 PM PDT 24 |
14624452 ps |
| T1937 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3792561662 |
|
|
Apr 16 12:24:55 PM PDT 24 |
Apr 16 12:24:59 PM PDT 24 |
117205637 ps |
| T145 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3916030324 |
|
|
Apr 16 02:29:04 PM PDT 24 |
Apr 16 02:29:07 PM PDT 24 |
143559859 ps |
| T1938 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4161431799 |
|
|
Apr 16 12:24:27 PM PDT 24 |
Apr 16 12:24:33 PM PDT 24 |
230369661 ps |
| T1939 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2597836392 |
|
|
Apr 16 12:21:07 PM PDT 24 |
Apr 16 12:21:11 PM PDT 24 |
117165252 ps |
| T1940 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2383401302 |
|
|
Apr 16 02:28:41 PM PDT 24 |
Apr 16 02:28:44 PM PDT 24 |
238290553 ps |
| T1941 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3912387455 |
|
|
Apr 16 12:24:36 PM PDT 24 |
Apr 16 12:24:40 PM PDT 24 |
45879034 ps |
| T1942 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3336258892 |
|
|
Apr 16 02:28:29 PM PDT 24 |
Apr 16 02:28:30 PM PDT 24 |
22006727 ps |
| T1943 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4230977895 |
|
|
Apr 16 12:24:19 PM PDT 24 |
Apr 16 12:24:24 PM PDT 24 |
239930336 ps |
| T1944 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1639916594 |
|
|
Apr 16 12:24:17 PM PDT 24 |
Apr 16 12:24:34 PM PDT 24 |
1472863523 ps |
| T1945 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1446665439 |
|
|
Apr 16 12:22:42 PM PDT 24 |
Apr 16 12:22:49 PM PDT 24 |
308759238 ps |
| T1946 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3577321577 |
|
|
Apr 16 12:24:21 PM PDT 24 |
Apr 16 12:24:26 PM PDT 24 |
85048979 ps |
| T1947 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4128396405 |
|
|
Apr 16 02:29:05 PM PDT 24 |
Apr 16 02:29:07 PM PDT 24 |
47518635 ps |
| T137 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1094256855 |
|
|
Apr 16 12:24:27 PM PDT 24 |
Apr 16 12:24:34 PM PDT 24 |
73479850 ps |
| T131 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3525725559 |
|
|
Apr 16 02:29:11 PM PDT 24 |
Apr 16 02:29:14 PM PDT 24 |
439721717 ps |
| T1948 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2666048796 |
|
|
Apr 16 02:28:17 PM PDT 24 |
Apr 16 02:28:19 PM PDT 24 |
17272472 ps |
| T1949 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2911154505 |
|
|
Apr 16 02:28:03 PM PDT 24 |
Apr 16 02:28:05 PM PDT 24 |
66233570 ps |
| T1950 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.77028876 |
|
|
Apr 16 12:24:22 PM PDT 24 |
Apr 16 12:24:35 PM PDT 24 |
2021475582 ps |
| T1951 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3986724160 |
|
|
Apr 16 12:26:04 PM PDT 24 |
Apr 16 12:26:08 PM PDT 24 |
370099364 ps |
| T1952 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3599818459 |
|
|
Apr 16 12:24:32 PM PDT 24 |
Apr 16 12:24:44 PM PDT 24 |
677436205 ps |
| T128 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.118302157 |
|
|
Apr 16 12:24:37 PM PDT 24 |
Apr 16 12:24:42 PM PDT 24 |
1782485451 ps |
| T1953 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1356974942 |
|
|
Apr 16 02:28:38 PM PDT 24 |
Apr 16 02:28:40 PM PDT 24 |
14467966 ps |
| T1954 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1377015286 |
|
|
Apr 16 02:28:17 PM PDT 24 |
Apr 16 02:28:20 PM PDT 24 |
115810270 ps |
| T1955 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2978912065 |
|
|
Apr 16 02:29:01 PM PDT 24 |
Apr 16 02:29:04 PM PDT 24 |
30583659 ps |
| T1956 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3143044980 |
|
|
Apr 16 12:22:04 PM PDT 24 |
Apr 16 12:22:10 PM PDT 24 |
1491973892 ps |
| T146 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2962380874 |
|
|
Apr 16 02:28:39 PM PDT 24 |
Apr 16 02:28:43 PM PDT 24 |
243200892 ps |
| T1957 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4074041289 |
|
|
Apr 16 12:24:37 PM PDT 24 |
Apr 16 12:24:43 PM PDT 24 |
684536395 ps |
| T1958 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1973173623 |
|
|
Apr 16 12:24:20 PM PDT 24 |
Apr 16 12:24:25 PM PDT 24 |
68074149 ps |
| T1959 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2191107826 |
|
|
Apr 16 12:24:23 PM PDT 24 |
Apr 16 12:24:28 PM PDT 24 |
90216752 ps |
| T1960 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.695072859 |
|
|
Apr 16 02:29:13 PM PDT 24 |
Apr 16 02:29:15 PM PDT 24 |
128022491 ps |
| T1961 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.673067590 |
|
|
Apr 16 12:17:54 PM PDT 24 |
Apr 16 12:17:57 PM PDT 24 |
56003481 ps |
| T1962 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3669561206 |
|
|
Apr 16 12:24:19 PM PDT 24 |
Apr 16 12:24:27 PM PDT 24 |
360307062 ps |
| T1963 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2994861967 |
|
|
Apr 16 12:24:22 PM PDT 24 |
Apr 16 12:24:28 PM PDT 24 |
59446590 ps |
| T1964 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.187630784 |
|
|
Apr 16 12:24:25 PM PDT 24 |
Apr 16 12:24:29 PM PDT 24 |
46950464 ps |
| T1965 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.922908139 |
|
|
Apr 16 02:29:10 PM PDT 24 |
Apr 16 02:29:12 PM PDT 24 |
32459022 ps |
| T1966 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.532103987 |
|
|
Apr 16 02:28:00 PM PDT 24 |
Apr 16 02:28:02 PM PDT 24 |
23322497 ps |
| T1967 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1987597659 |
|
|
Apr 16 12:24:29 PM PDT 24 |
Apr 16 12:24:34 PM PDT 24 |
16839318 ps |
| T1968 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1058384999 |
|
|
Apr 16 12:26:12 PM PDT 24 |
Apr 16 12:26:18 PM PDT 24 |
117576686 ps |
| T1969 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3398024975 |
|
|
Apr 16 02:27:52 PM PDT 24 |
Apr 16 02:27:55 PM PDT 24 |
268394145 ps |
| T1970 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3387375368 |
|
|
Apr 16 12:21:31 PM PDT 24 |
Apr 16 12:21:33 PM PDT 24 |
29044207 ps |
| T1971 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1107249819 |
|
|
Apr 16 12:24:31 PM PDT 24 |
Apr 16 12:24:43 PM PDT 24 |
825949178 ps |
| T1972 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2407807696 |
|
|
Apr 16 12:24:16 PM PDT 24 |
Apr 16 12:24:24 PM PDT 24 |
1422514055 ps |
| T1973 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4088321854 |
|
|
Apr 16 02:28:30 PM PDT 24 |
Apr 16 02:28:37 PM PDT 24 |
478740919 ps |
| T1974 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3609404583 |
|
|
Apr 16 02:27:53 PM PDT 24 |
Apr 16 02:27:57 PM PDT 24 |
291047277 ps |
| T1975 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3040146759 |
|
|
Apr 16 02:28:36 PM PDT 24 |
Apr 16 02:28:39 PM PDT 24 |
170081798 ps |
| T1976 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4249791774 |
|
|
Apr 16 02:28:46 PM PDT 24 |
Apr 16 02:28:47 PM PDT 24 |
201760239 ps |
| T1977 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2889520385 |
|
|
Apr 16 02:28:54 PM PDT 24 |
Apr 16 02:28:57 PM PDT 24 |
343980763 ps |
| T1978 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4007917681 |
|
|
Apr 16 02:29:03 PM PDT 24 |
Apr 16 02:29:05 PM PDT 24 |
20384077 ps |
| T1979 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3523859266 |
|
|
Apr 16 02:28:35 PM PDT 24 |
Apr 16 02:28:36 PM PDT 24 |
15908022 ps |
| T1980 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3532847428 |
|
|
Apr 16 12:24:29 PM PDT 24 |
Apr 16 12:24:36 PM PDT 24 |
365664968 ps |
| T1981 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2706442315 |
|
|
Apr 16 02:29:00 PM PDT 24 |
Apr 16 02:29:03 PM PDT 24 |
80077410 ps |
| T1982 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.424882486 |
|
|
Apr 16 02:28:04 PM PDT 24 |
Apr 16 02:28:06 PM PDT 24 |
350444492 ps |
| T1983 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3020808391 |
|
|
Apr 16 02:29:05 PM PDT 24 |
Apr 16 02:29:06 PM PDT 24 |
40675156 ps |
| T1984 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.356132873 |
|
|
Apr 16 02:28:55 PM PDT 24 |
Apr 16 02:28:58 PM PDT 24 |
203706771 ps |
| T1985 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2788240500 |
|
|
Apr 16 12:24:19 PM PDT 24 |
Apr 16 12:24:36 PM PDT 24 |
621039676 ps |
| T1986 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.307538307 |
|
|
Apr 16 02:28:12 PM PDT 24 |
Apr 16 02:28:18 PM PDT 24 |
115102367 ps |
| T1987 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1090188339 |
|
|
Apr 16 02:28:48 PM PDT 24 |
Apr 16 02:28:50 PM PDT 24 |
25037459 ps |
| T1988 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.947387057 |
|
|
Apr 16 02:28:35 PM PDT 24 |
Apr 16 02:28:37 PM PDT 24 |
400038138 ps |
| T1989 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2414363805 |
|
|
Apr 16 12:24:23 PM PDT 24 |
Apr 16 12:24:27 PM PDT 24 |
20328296 ps |
| T1990 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.259235375 |
|
|
Apr 16 12:24:21 PM PDT 24 |
Apr 16 12:24:27 PM PDT 24 |
337441517 ps |
| T1991 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1641708784 |
|
|
Apr 16 02:28:49 PM PDT 24 |
Apr 16 02:28:50 PM PDT 24 |
46313555 ps |
| T1992 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1293502068 |
|
|
Apr 16 12:24:26 PM PDT 24 |
Apr 16 12:24:31 PM PDT 24 |
38723832 ps |
| T1993 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.598202179 |
|
|
Apr 16 02:27:58 PM PDT 24 |
Apr 16 02:28:00 PM PDT 24 |
51546862 ps |
| T1994 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2807094927 |
|
|
Apr 16 02:29:04 PM PDT 24 |
Apr 16 02:29:06 PM PDT 24 |
54438005 ps |
| T1995 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3420631579 |
|
|
Apr 16 12:24:14 PM PDT 24 |
Apr 16 12:24:20 PM PDT 24 |
83443497 ps |
| T1996 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1422903025 |
|
|
Apr 16 12:24:30 PM PDT 24 |
Apr 16 12:24:55 PM PDT 24 |
984584487 ps |
| T1997 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1567134751 |
|
|
Apr 16 12:24:07 PM PDT 24 |
Apr 16 12:24:12 PM PDT 24 |
78120460 ps |
| T1998 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1663045197 |
|
|
Apr 16 02:28:29 PM PDT 24 |
Apr 16 02:28:32 PM PDT 24 |
232040987 ps |
| T1999 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4141778836 |
|
|
Apr 16 02:28:59 PM PDT 24 |
Apr 16 02:29:04 PM PDT 24 |
1403516134 ps |
| T2000 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2298741287 |
|
|
Apr 16 02:28:59 PM PDT 24 |
Apr 16 02:29:01 PM PDT 24 |
77087603 ps |