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NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
gen_alert_tx[2].u_prim_alert_sender 100.00 100.00
lc_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_dmi_jtag 94.66 94.66
i_dmi_cdc 95.43 95.43
i_cdc_req 97.86 97.86
sync_rptr 95.83 95.83
u_prim_cdc_rand_delay 75.00 75.00
u_sync_1 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_sync_2 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
sync_wptr 95.83 95.83
u_prim_cdc_rand_delay 75.00 75.00
u_sync_1 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_sync_2 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
i_cdc_resp 95.20 95.20
sync_rptr 95.83 95.83
u_prim_cdc_rand_delay 75.00 75.00
u_sync_1 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_sync_2 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
sync_wptr 95.83 95.83
u_prim_cdc_rand_delay 75.00 75.00
u_sync_1 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_sync_2 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_combined_rstn_sync 81.82 81.82
u_prim_cdc_rand_delay 33.33 33.33
u_sync_1 75.00 75.00
gen_generic.u_impl_generic 75.00 75.00
u_sync_2 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_rst_mux 75.00 75.00
gen_generic.u_impl_generic 75.00 75.00
i_dmi_jtag_tap 80.65 80.65
i_tck_inv 71.43 71.43
gen_generic.u_impl_generic 72.73 72.73
gen_scan.i_dft_tck_mux 75.00 75.00
gen_generic.u_impl_generic 75.00 75.00
u_lc_ctrl_fsm 86.66 98.29 68.97 73.91 95.35 96.77
subtree...
u_lc_ctrl_kmac_if 97.01 97.37 100.00 100.00 87.69 100.00
u_prim_sync_reqack_data_in 93.48 96.43 84.00 100.00
u_prim_sync_reqack 92.58 95.92 81.82 100.00
ack_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
req_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_sync_reqack_data_out 92.61 96.00 81.82 100.00
u_prim_sync_reqack 92.58 95.92 81.82 100.00
ack_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
req_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_state_flop 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_clock_mux2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_esc_receiver0 9.00 9.00
u_prim_count 2.15 2.15
u_prim_esc_receiver1 9.00 9.00
u_prim_count 2.15 2.15
u_prim_flop_2sync_init 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_lc_sync 100.00 100.00 100.00 100.00
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_prim_mubi4_dec 0.00 0.00
gen_bits[0].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_bits[1].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_bits[2].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_bits[3].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_rst_n_mux2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg 97.32 99.09 100.00 100.00 100.00 87.50
u_alert_test_fatal_bus_integ_error 100.00 100.00
u_alert_test_fatal_prog_error 100.00 100.00
u_alert_test_fatal_state_error 100.00 100.00
u_chk 100.00 100.00 100.00
u_chk 100.00 100.00
u_tlul_data_integ_dec 100.00 100.00
u_data_chk 100.00 100.00
u_claim_transition_if 100.00 100.00
u_device_id_0 100.00 100.00
u_device_id_1 100.00 100.00
u_device_id_2 100.00 100.00
u_device_id_3 100.00 100.00
u_device_id_4 100.00 100.00
u_device_id_5 100.00 100.00
u_device_id_6 100.00 100.00
u_device_id_7 100.00 100.00
u_hw_rev_chip_gen 33.33 33.33
u_hw_rev_chip_rev 33.33 33.33
u_lc_id_state 66.67 66.67
u_lc_state 100.00 100.00
u_lc_transition_cnt 100.00 100.00
u_manuf_state_0 100.00 100.00
u_manuf_state_1 100.00 100.00
u_manuf_state_2 100.00 100.00
u_manuf_state_3 100.00 100.00
u_manuf_state_4 100.00 100.00
u_manuf_state_5 100.00 100.00
u_manuf_state_6 100.00 100.00
u_manuf_state_7 100.00 100.00
u_otp_vendor_test_ctrl 100.00 100.00
u_otp_vendor_test_status 100.00 100.00
u_prim_reg_we_check 90.48 100.00 100.00 71.43
u_prim_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_prim_onehot_check 85.71 100.00 71.43
u_reg_if 100.00 100.00 100.00 100.00 100.00
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
u_data_gen 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00
u_status_bus_integ_error 100.00 100.00
u_status_flash_rma_error 100.00 100.00
u_status_otp_error 100.00 100.00
u_status_otp_partition_error 100.00 100.00
u_status_ready 100.00 100.00
u_status_state_error 100.00 100.00
u_status_token_error 100.00 100.00
u_status_transition_count_error 100.00 100.00
u_status_transition_error 100.00 100.00
u_status_transition_successful 100.00 100.00
u_transition_cmd 100.00 100.00
u_transition_ctrl 100.00 100.00
u_transition_regwen 100.00 100.00
u_transition_target 100.00 100.00
u_transition_token_0 100.00 100.00
u_transition_token_1 100.00 100.00
u_transition_token_2 100.00 100.00
u_transition_token_3 100.00 100.00
u_reg_tap 93.60 97.46 92.86 100.00 90.16 87.50
u_alert_test_fatal_bus_integ_error 100.00 100.00
u_alert_test_fatal_prog_error 100.00 100.00
u_alert_test_fatal_state_error 100.00 100.00
u_chk 100.00 100.00 100.00
u_chk 100.00 100.00
u_tlul_data_integ_dec 100.00 100.00
u_data_chk 100.00 100.00
u_claim_transition_if 100.00 100.00
u_device_id_0 100.00 100.00
u_device_id_1 100.00 100.00
u_device_id_2 100.00 100.00
u_device_id_3 100.00 100.00
u_device_id_4 100.00 100.00
u_device_id_5 100.00 100.00
u_device_id_6 100.00 100.00
u_device_id_7 100.00 100.00
u_hw_rev_chip_gen 33.33 33.33
u_hw_rev_chip_rev 33.33 33.33
u_lc_id_state 66.67 66.67
u_lc_state 100.00 100.00
u_lc_transition_cnt 100.00 100.00
u_manuf_state_0 100.00 100.00
u_manuf_state_1 100.00 100.00
u_manuf_state_2 100.00 100.00
u_manuf_state_3 100.00 100.00
u_manuf_state_4 100.00 100.00
u_manuf_state_5 100.00 100.00
u_manuf_state_6 100.00 100.00
u_manuf_state_7 100.00 100.00
u_otp_vendor_test_ctrl 100.00 100.00
u_otp_vendor_test_status 100.00 100.00
u_prim_reg_we_check 90.48 100.00 100.00 71.43
u_prim_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_prim_onehot_check 85.71 100.00 71.43
u_reg_if 89.90 86.89 100.00 72.73 100.00
u_err 64.74 69.23 25.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
u_data_gen 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00
u_status_bus_integ_error 100.00 100.00
u_status_flash_rma_error 100.00 100.00
u_status_otp_error 100.00 100.00
u_status_otp_partition_error 100.00 100.00
u_status_ready 100.00 100.00
u_status_state_error 100.00 100.00
u_status_token_error 100.00 100.00
u_status_transition_count_error 100.00 100.00
u_status_transition_error 100.00 100.00
u_status_transition_successful 100.00 100.00
u_transition_cmd 100.00 100.00
u_transition_ctrl 100.00 100.00
u_transition_regwen 100.00 100.00
u_transition_target 100.00 100.00
u_transition_token_0 100.00 100.00
u_transition_token_1 100.00 100.00
u_transition_token_2 100.00 100.00
u_transition_token_3 100.00 100.00
u_tap_tlul_host 94.59 98.36 86.67 93.33 100.00
u_cmd_intg_gen 100.00 100.00 100.00
gen_data_intg.u_data_gen 100.00 100.00
u_cmd_gen 100.00 100.00
u_rsp_chk 100.00 100.00 100.00
u_chk 100.00 100.00
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