Module Definition
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Module : tlul_rsp_intg_chk
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 40.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tap_tlul_host.u_rsp_chk 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.77 100.00 100.00 15.09 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.78 95.45 91.67 100.00 100.00 u_tap_tlul_host


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 15.09 15.09

Line Coverage for Module : tlul_rsp_intg_chk
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2311100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 1 1
47 1 1
50 1 1


Cond Coverage for Module : tlul_rsp_intg_chk
TotalCoveredPercent
Conditions5240.00
Logical5240.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Not Covered

Assert Coverage for Module : tlul_rsp_intg_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 812 812 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 812 812 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2311100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 1 1
47 1 1
50 1 1


Cond Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT2,T3,T4
11Excluded VC_COV_UNR

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Unreachable
10Excluded VC_COV_UNR

Assert Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 812 812 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 812 812 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%