Module Definition
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Module : lc_ctrl_fsm_cov_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if 96.97 100.00 90.91 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.77 98.87 93.02 100.00 98.63 93.33 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : lc_ctrl_fsm_cov_if
Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN7111100.00
ALWAYS7799100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv' or '../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
71 1 1
77 1 1
78 1 1
79 1 1
81 1 1
82 1 1
85 1 1
86 1 1
MISSING_ELSE
89 1 1
90 1 1
MISSING_ELSE


Cond Coverage for Module : lc_ctrl_fsm_cov_if
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       71
 EXPRESSION (trans_invalid_error_o & ((~trans_invalid_error)))
             ----------1----------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT11,T50,T51

 LINE       77
 EXPRESSION (rst_ni == 1'b0)
            --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       85
 EXPRESSION (((~token_mux_idx_error_prev)) & token_mux_idx_error)
             --------------1--------------   ---------2---------
-1--2-StatusTests
01CoveredT11,T50,T51
10CoveredT1,T2,T3
11CoveredT11,T50,T51

 LINE       89
 EXPRESSION (((~token_invalid_error_o_prev)) & token_invalid_error_o)
             ---------------1---------------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

Branch Coverage for Module : lc_ctrl_fsm_cov_if
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 77 2 2 100.00
IF 85 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv' or '../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 77 if ((rst_ni == 1'b0))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 85 if (((~token_mux_idx_error_prev) & token_mux_idx_error))

Branches:
-1-StatusTests
1 Covered T11,T50,T51
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if (((~token_invalid_error_o_prev) & token_invalid_error_o))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%