Module Definition
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Module Instance : tb.dut.u_reg.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_tap.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
err_o[1:0] Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT

Toggle Coverage for Instance : tb.dut.u_reg.u_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
err_o[1:0] Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT

Toggle Coverage for Instance : tb.dut.u_reg_tap.u_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 142 142 100.00
Total Bits 0->1 71 71 100.00
Total Bits 1->0 71 71 100.00

Ports 2 2 100.00
Port Bits 142 142 100.00
Port Bits 0->1 71 71 100.00
Port Bits 1->0 71 71 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[38:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
data_o[31:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
syndrome_o[6:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

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