Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : lc_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 100.00 98.97 100.00 84.85

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 96.76 100.00 100.00 98.97 100.00 84.85



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 100.00 98.97 100.00 84.85


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.49 97.89 81.58 94.45 76.92 94.61 97.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
gen_alert_tx[2].u_prim_alert_sender 100.00 100.00
lc_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_dmi_jtag 94.66 94.66
u_lc_ctrl_fsm 86.66 98.29 68.97 73.91 95.35 96.77
u_lc_ctrl_kmac_if 97.01 97.37 100.00 100.00 87.69 100.00
u_prim_clock_mux2 100.00 100.00 100.00
u_prim_esc_receiver0 9.00 9.00
u_prim_esc_receiver1 9.00 9.00
u_prim_flop_2sync_init 100.00 100.00 100.00
u_prim_lc_sync 100.00 100.00 100.00 100.00
u_prim_mubi4_dec 0.00 0.00
u_prim_rst_n_mux2 100.00 100.00 100.00
u_reg 97.32 99.09 100.00 100.00 100.00 87.50
u_reg_tap 93.60 97.46 92.86 100.00 90.16 87.50
u_tap_tlul_host 94.59 98.36 86.67 93.33 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : lc_ctrl
Line No.TotalCoveredPercent
TOTAL117117100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN26111100.00
ALWAYS3053535100.00
ALWAYS3503636100.00
ALWAYS4273131100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN48211100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN51011100.00
ALWAYS59655100.00
CONT_ASSIGN60511100.00
CONT_ASSIGN60611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
208 1 1
261 1 1
305 1 1
306 1 1
307 1 1
308 1 1
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
320 1 1
321 1 1
322 1 1
325 1 1
328 1 1
329 1 1
330 1 1
331 1 1
332 1 1
333 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
343 1 1
344 1 1
345 1 1
MISSING_ELSE
350 1 1
351 1 1
352 1 1
353 1 1
354 1 1
355 1 1
356 1 1
361 1 1
363 1 1
365 1 1
367 1 1
MISSING_ELSE
372 1 1
374 1 1
375 1 1
378 1 1
379 1 1
MISSING_ELSE
382 1 1
383 1 1
384 1 1
MISSING_ELSE
388 1 1
389 1 1
390 1 1
MISSING_ELSE
395 1 1
396 1 1
MISSING_ELSE
398 1 1
399 1 1
402 1 1
403 1 1
MISSING_ELSE
406 1 1
407 1 1
408 1 1
MISSING_ELSE
412 1 1
413 1 1
414 1 1
MISSING_ELSE
419 1 1
420 1 1
MISSING_ELSE
MISSING_ELSE
MISSING_ELSE
427 1 1
428 1 1
429 1 1
430 1 1
431 1 1
432 1 1
433 1 1
434 1 1
435 1 1
436 1 1
437 1 1
438 1 1
439 1 1
440 1 1
441 1 1
442 1 1
445 1 1
446 1 1
447 1 1
448 1 1
449 1 1
450 1 1
451 1 1
452 1 1
453 1 1
457 1 1
458 1 1
459 1 1
460 1 1
461 1 1
462 1 1
466 1 1
482 1 1
484 1 1
495 1 1
501 1 1
510 1 1
596 1 1
597 1 1
598 1 1
600 1 1
601 1 1
605 1 1
606 1 1


Cond Coverage for Module : lc_ctrl
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       482
 EXPRESSION ((lc_raw_test_rma_buf[0] == On) ? otp_vendor_test_ctrl_q : '0)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       484
 EXPRESSION ((lc_raw_test_rma_buf[1] == On) ? lc_otp_vendor_test_i.status : '0)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Toggle Coverage for Module : lc_ctrl
TotalCoveredPercent
Totals 103 99 96.12
Total Bits 7368 7292 98.97
Total Bits 0->1 3684 3646 98.97
Total Bits 1->0 3684 3646 98.97

Ports 103 99 96.12
Port Bits 7368 7292 98.97
Port Bits 0->1 3684 3646 98.97
Port Bits 1->0 3684 3646 98.97

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
rst_ni Yes Yes T45,T57,T58 Yes T22,T41,T42 INPUT
clk_kmac_i Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
rst_kmac_ni Yes Yes T45,T57,T58 Yes T22,T41,T42 INPUT
tl_i.d_ready Yes Yes T22,T42,T44 Yes T22,T41,T42 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T45,T57,T58 Yes T45,T57,T58 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 INPUT
tl_i.a_mask[3:0] Yes Yes T22,T42,T44 Yes T22,T42,T44 INPUT
tl_i.a_address[31:0] Yes Yes T22,T42,T44 Yes T22,T42,T44 INPUT
tl_i.a_source[7:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 INPUT
tl_i.a_size[1:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 INPUT
tl_i.a_valid Yes Yes T22,T42,T43 Yes T22,T42,T43 INPUT
tl_o.a_ready Yes Yes T22,T42,T43 Yes T22,T42,T43 OUTPUT
tl_o.d_error Yes Yes T45,T57,T58 Yes T45,T57,T58 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T22,*T42,*T43 Yes T22,T42,T43 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T22,T42,T44 Yes T22,T42,T43 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 OUTPUT
tl_o.d_size[1:0] Yes Yes T22,T42,T43 Yes T22,T42,T43 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T22,*T42,*T44 Yes T22,T42,T44 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T22,T42,T43 Yes T22,T42,T43 OUTPUT
jtag_i.tdi Yes Yes T41,T46,T49 Yes T41,T46,T49 INPUT
jtag_i.trst_n Yes Yes T45,T57,T58 Yes T22,T41,T42 INPUT
jtag_i.tms Yes Yes T41,T46,T49 Yes T41,T46,T49 INPUT
jtag_i.tck Yes Yes T41,T46,T49 Yes T41,T46,T49 INPUT
jtag_o.tdo_oe Yes Yes T41,T46,T49 Yes T41,T46,T49 OUTPUT
jtag_o.tdo Yes Yes T41,T46,T49 Yes T41,T46,T49 OUTPUT
scan_rst_ni Yes Yes T4,T5,T6 Yes T6,T19,T20 INPUT
scanmode_i[3:0] No No No INPUT
alert_rx_i[0].ack_n Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
alert_rx_i[0].ack_p Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
alert_rx_i[1].ack_p Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
alert_rx_i[2].ack_p Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T22,T41,T42 Yes T22,T41,T42 OUTPUT
alert_tx_o[0].alert_p Yes Yes T22,T41,T42 Yes T22,T41,T42 OUTPUT
alert_tx_o[1].alert_n Yes Yes T22,T41,T42 Yes T22,T41,T42 OUTPUT
alert_tx_o[1].alert_p Yes Yes T22,T41,T42 Yes T22,T41,T42 OUTPUT
alert_tx_o[2].alert_n Yes Yes T22,T41,T42 Yes T22,T41,T42 OUTPUT
alert_tx_o[2].alert_p Yes Yes T22,T41,T42 Yes T22,T41,T42 OUTPUT
esc_scrap_state0_tx_i.resp_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_scrap_state0_tx_i.resp_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_scrap_state0_rx_o.esc_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_scrap_state0_rx_o.esc_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_scrap_state1_tx_i.resp_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_scrap_state1_tx_i.resp_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_scrap_state1_rx_o.esc_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_scrap_state1_rx_o.esc_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_lc_i.lc_init Yes Yes T22,T41,T42 Yes T22,T41,T42 INPUT
pwr_lc_o.lc_idle Yes Yes T45,T57,T58 Yes T22,T41,T42 OUTPUT
pwr_lc_o.lc_done Yes Yes T45,T57,T58 Yes T22,T41,T42 OUTPUT
lc_otp_vendor_test_o.ctrl[31:0] Yes Yes T2,T13,T14 Yes T2,T13,T14 OUTPUT
lc_otp_vendor_test_i.status[31:0] Yes Yes T45,T57,T59 Yes T41,T42,T43 INPUT
lc_otp_program_o.count[383:0] Yes Yes T60,T8,T38 Yes T8,T38,T11 OUTPUT
lc_otp_program_o.state[319:0] Yes Yes T45,T61,T59 Yes T45,T59,T62 OUTPUT
lc_otp_program_o.req Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
lc_otp_program_i.ack Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
lc_otp_program_i.err Yes Yes T10,T25,T53 Yes T10,T25,T63 INPUT
kmac_data_i.error Yes Yes T8,T9,T10 Yes T8,T9,T10 INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T2,T3,T7 Yes T3,T7,T13 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
kmac_data_i.done Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
kmac_data_i.ready Yes Yes T22,T41,T44 Yes T22,T41,T42 INPUT
kmac_data_o.last Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
kmac_data_o.strb[7:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
kmac_data_o.data[63:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
kmac_data_o.valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
otp_lc_data_i.rma_token[127:0] Yes Yes T45,T57,T59 Yes T45,T57,T59 INPUT
otp_lc_data_i.rma_token_valid[3:0] Yes Yes T7,T28,T29 Yes T7,T28,T29 INPUT
otp_lc_data_i.test_exit_token[127:0] Yes Yes T45,T57,T59 Yes T45,T57,T59 INPUT
otp_lc_data_i.test_unlock_token[127:0] Yes Yes T45,T57,T58 Yes T45,T57,T59 INPUT
otp_lc_data_i.test_tokens_valid[3:0] Yes Yes T7,T28,T29 Yes T7,T28,T29 INPUT
otp_lc_data_i.secrets_valid[3:0] Yes Yes T7,T28,T29 Yes T7,T28,T29 INPUT
otp_lc_data_i.count[383:0] Yes Yes T8,T38,T64 Yes T8,T38,T64 INPUT
otp_lc_data_i.state[319:0] Yes Yes T45,T59,T62 Yes T45,T59,T62 INPUT
otp_lc_data_i.error Yes Yes T8,T9,T10 Yes T8,T9,T10 INPUT
otp_lc_data_i.valid Yes Yes T1,T2,T10 Yes T1,T2,T10 INPUT
lc_dft_en_o[3:0] Yes Yes T45,T57,T65 Yes T42,T44,T45 OUTPUT
lc_nvm_debug_en_o[3:0] Yes Yes T45,T57,T65 Yes T42,T44,T45 OUTPUT
lc_hw_debug_en_o[3:0] Yes Yes T45,T57,T66 Yes T42,T44,T45 OUTPUT
lc_cpu_en_o[3:0] Yes Yes T45,T57,T59 Yes T42,T44,T45 OUTPUT
lc_creator_seed_sw_rw_en_o[3:0] Yes Yes T45,T57,T59 Yes T45,T48,T57 OUTPUT
lc_owner_seed_sw_rw_en_o[3:0] Yes Yes T45,T57,T59 Yes T45,T48,T57 OUTPUT
lc_iso_part_sw_rd_en_o[3:0] Yes Yes T45,T57,T59 Yes T45,T48,T57 OUTPUT
lc_iso_part_sw_wr_en_o[3:0] Yes Yes T45,T57,T59 Yes T42,T44,T45 OUTPUT
lc_seed_hw_rd_en_o[3:0] Yes Yes T45,T57,T62 Yes T45,T57,T67 OUTPUT
lc_keymgr_en_o[3:0] Yes Yes T45,T57,T59 Yes T45,T48,T57 OUTPUT
lc_escalate_en_o[3:0] Yes Yes T45,T58,T67 Yes T45,T58,T67 OUTPUT
lc_check_byp_en_o[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
lc_clk_byp_req_o[0] No No Yes T4,T5,T6 OUTPUT
lc_clk_byp_req_o[1] No Yes *T4,*T5,*T6 No OUTPUT
lc_clk_byp_req_o[2] No No Yes T4,T5,T6 OUTPUT
lc_clk_byp_req_o[3] No Yes T4,T5,T6 No OUTPUT
lc_clk_byp_ack_i[3:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
lc_flash_rma_seed_o[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
lc_flash_rma_req_o[3:0] Yes Yes T7,T13,T14 Yes T7,T13,T14 OUTPUT
lc_flash_rma_ack_i[3:0] Yes Yes T7,T13,T14 Yes T7,T13,T14 INPUT
lc_keymgr_div_o[127:0] Yes Yes T57,T59,T68 Yes T48,T57,T59 OUTPUT
otp_device_id_i[255:0] Yes Yes T45,T57,T58 Yes T41,T43,T44 INPUT
otp_manuf_state_i[255:0] Yes Yes T45,T58,T59 Yes T42,T44,T45 INPUT
hw_rev_o.chip_rev[15:0] No No No OUTPUT
hw_rev_o.chip_gen[15:0] No No No OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : lc_ctrl
Line No.TotalCoveredPercent
Branches 28 28 100.00
TERNARY 482 2 2 100.00
TERNARY 484 2 2 100.00
IF 330 3 3 100.00
IF 361 3 3 100.00
IF 372 14 14 100.00
IF 427 2 2 100.00
IF 596 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 482 ((lc_raw_test_rma_buf[0] == On)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((lc_raw_test_rma_buf[1] == On)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 330 if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q)) -2-: 338 if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 361 if ((prim_mubi_pkg::mubi8_test_false_loose(sw_claim_transition_if_q) && tap_reg2hw.claim_transition_if.qe)) -2-: 365 if ((prim_mubi_pkg::mubi8_test_false_loose(tap_claim_transition_if_q) && reg2hw.claim_transition_if.qe))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 372 if (lc_idle_d) -2-: 374 if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q)) -3-: 378 if (tap_reg2hw.transition_ctrl.qe) -4-: 388 if (tap_reg2hw.transition_target.qe) -5-: 395 if (tap_reg2hw.otp_vendor_test_ctrl.qe) -6-: 398 if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q)) -7-: 402 if (reg2hw.transition_ctrl.qe) -8-: 412 if (reg2hw.transition_target.qe) -9-: 419 if (reg2hw.otp_vendor_test_ctrl.qe)

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
1 1 1 - - - - - - Covered T4,T5,T6
1 1 0 - - - - - - Covered T4,T5,T6
1 1 - 1 - - - - - Covered T4,T5,T6
1 1 - 0 - - - - - Covered T4,T5,T6
1 1 - - 1 - - - - Covered T4,T5,T6
1 1 - - 0 - - - - Covered T4,T5,T6
1 0 - - - 1 1 - - Covered T4,T6,T21
1 0 - - - 1 0 - - Covered T1,T2,T3
1 0 - - - 1 - 1 - Covered T2,T3,T7
1 0 - - - 1 - 0 - Covered T1,T2,T3
1 0 - - - 1 - - 1 Covered T2,T3,T7
1 0 - - - 1 - - 0 Covered T1,T2,T3
1 0 - - - 0 - - - Covered T1,T2,T3
0 - - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 427 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 596 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : lc_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 33 33 100.00 28 84.85
Cover properties 0 0 0
Cover sequences 0 0 0
Total 33 33 100.00 28 84.85




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnown_A 55408495 52519178 0 0
DecLcCountWidthCheck_A 685 685 0 0
DecLcIdStateWidthCheck_A 685 685 0 0
DecLcStateWidthCheck_A 685 685 0 0
FpvSecCmCtrlKmacIfFsmCheck_A 53839338 0 0 0
FpvSecCmCtrlLcCntCheck_A 50439898 0 0 0
FpvSecCmCtrlLcFsmCheck_A 53658571 0 0 0
FpvSecCmCtrlLcStateCheck_A 51354897 0 0 0
FpvSecCmRegWeOnehotCheck_A 55408495 70 0 0
FpvSecCmTapRegWeOnehotCheck_A 55408495 0 0 0
HwRevFieldWidth_A 685 685 0 0
LcCheckBypassEnKnown_A 55408495 52519178 0 0
LcClkBypReqKnown_A 55408495 52519178 0 0
LcCpuEnKnown_A 55408495 52519178 0 0
LcCreatorSwRwEn_A 55408495 52519178 0 0
LcDftEnKnown_A 55408495 52519178 0 0
LcEscalateEnKnown_A 55408495 52519178 0 0
LcFlashRmaReqKnown_A 55408495 52519178 0 0
LcFlashRmaSeedKnown_A 55408495 52519178 0 0
LcHwDebugEnKnown_A 55408495 52519178 0 0
LcIsoSwRwEn_A 55408495 52519178 0 0
LcIsoSwWrEn_A 55408495 52519178 0 0
LcKeymgrDiv_A 55408495 52519178 0 0
LcKeymgrEnKnown_A 55408495 52519178 0 0
LcNvmDebugEnKnown_A 55408495 52519178 0 0
LcOtpProgramKnown_A 55408495 52519178 0 0
LcOtpTokenKnown_A 55408495 52519178 0 0
LcOwnerSwRwEn_A 55408495 52519178 0 0
LcSeedHwRdEn_A 55408495 52519178 0 0
NumTokenWordsCheck_A 685 685 0 0
OtpTestCtrlWidth_A 685 685 0 0
PwrLcKnown_A 55408495 52519178 0 0
TlOKnown 55408495 52519178 0 0


AlertTxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

DecLcCountWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 685 685 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T24 1 1 0 0

DecLcIdStateWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 685 685 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T24 1 1 0 0

DecLcStateWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 685 685 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T24 1 1 0 0

FpvSecCmCtrlKmacIfFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53839338 0 0 0

FpvSecCmCtrlLcCntCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50439898 0 0 0

FpvSecCmCtrlLcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53658571 0 0 0

FpvSecCmCtrlLcStateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 51354897 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 70 0 0
T23 9606 10 0 0
T35 11886 10 0 0
T40 10086 10 0 0
T50 19589 20 0 0
T69 34658 20 0 0

FpvSecCmTapRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 0 0 0

HwRevFieldWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 685 685 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T24 1 1 0 0

LcCheckBypassEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcClkBypReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcCpuEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcCreatorSwRwEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcDftEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcEscalateEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcFlashRmaReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcFlashRmaSeedKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcHwDebugEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcIsoSwRwEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcIsoSwWrEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcKeymgrDiv_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcKeymgrEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcNvmDebugEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcOtpProgramKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcOtpTokenKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcOwnerSwRwEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

LcSeedHwRdEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

NumTokenWordsCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 685 685 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T24 1 1 0 0

OtpTestCtrlWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 685 685 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T24 1 1 0 0

PwrLcKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

TlOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 55408495 52519178 0 0
T1 22916 17935 0 0
T2 7239 6302 0 0
T3 7338 6191 0 0
T4 4171 4077 0 0
T5 47915 47857 0 0
T7 37060 30238 0 0
T13 48569 40829 0 0
T14 28240 23531 0 0
T15 40982 33803 0 0
T24 2110 1813 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%