Module Definition
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Module : lc_ctrl_state_transition
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.07 97.01 66.67 91.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition 89.97 98.48 75.00 96.43



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.97 98.48 75.00 96.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.97 98.48 75.00 96.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.77 98.87 93.02 100.00 98.63 93.33 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : lc_ctrl_state_transition
Line No.TotalCoveredPercent
TOTAL676597.01
ALWAYS52676597.01
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
53 1 1
54 1 1
55 1 1
63 1 1
66 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
73 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1
91 1 1
92 1 1
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
99 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
108 1 1
109 1 1
118 1 1
119 1 1
120 1 1
121 1 1
MISSING_ELSE
MISSING_ELSE
125 1 1
133 1 1
140 1 1
147 1 1
148 0 1
149 1 1
150 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
172 1 1
175 0 1
180 1 1
201 1 1
MISSING_ELSE


Cond Coverage for Module : lc_ctrl_state_transition
TotalCoveredPercent
Conditions271866.67
Logical271866.67
Non-Logical00
Event00

 LINE       63
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && (fsm_state_i == IdleSt))
             -----------1----------    ----------2----------    -----3-----    -----------4-----------
-1--2--3--4-StatusTests
-011CoveredT1,T2,T3
-101CoveredT37,T5,T6
-110Not Covered
-111CoveredT37,T38,T39

 LINE       63
 SUB-EXPRESSION (fsm_state_i == IdleSt)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || 
      2  (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))
-1--2-StatusTests
00CoveredT37,T38,T39
01Not Covered
10Not Covered

 LINE       66
 SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
                -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT37,T38,T39
1CoveredT39,T40,T41

 LINE       66
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------
-1-StatusTests
0CoveredT37,T38,T39
1CoveredT39,T40,T41

 LINE       118
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       133
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i[0] <= DecLcStScrap) && 
      2  (trans_target_i[0] <= DecLcStScrap) && 
      3  (dec_lc_state_i[1] <= DecLcStScrap) && 
      4  (trans_target_i[1] <= DecLcStScrap))
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T2,T3

 LINE       140
 EXPRESSION 
 Number  Term
      1  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || 
      2  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Module : lc_ctrl_state_transition
Line No.TotalCoveredPercent
Branches 59 54 91.53
IF 63 3 3 100.00
IF 73 29 28 96.55
IF 125 27 23 85.19

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if ((((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i) && (fsm_state_i == IdleSt))) -2-: 66 if (((dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})))

Branches:
-1--2-StatusTests
1 1 Covered T39,T40,T41
1 0 Covered T37,T38,T39
0 - Covered T1,T2,T3


LineNo. Expression -1-: 73 if ((fsm_state_i inside {CntIncrSt, CntProgSt, TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt})) -2-: 84 case (lc_cnt_i) -3-: 118 if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}))

Branches:
-1--2--3-StatusTests
1 LcCnt0 - Covered T2,T4,T11
1 LcCnt1 - Covered T2,T4,T11
1 LcCnt2 - Covered T1,T2,T3
1 LcCnt3 - Covered T2,T3,T4
1 LcCnt4 - Covered T2,T3,T4
1 LcCnt5 - Covered T2,T3,T9
1 LcCnt6 - Covered T1,T2,T3
1 LcCnt7 - Covered T2,T3,T9
1 LcCnt8 - Covered T2,T3,T4
1 LcCnt9 - Covered T2,T3,T4
1 LcCnt10 - Covered T2,T3,T9
1 LcCnt11 - Covered T2,T3,T9
1 LcCnt12 - Covered T1,T2,T3
1 LcCnt13 - Covered T2,T3,T4
1 LcCnt14 - Covered T1,T2,T3
1 LcCnt15 - Covered T2,T3,T4
1 LcCnt16 - Covered T2,T3,T9
1 LcCnt17 - Covered T2,T3,T9
1 LcCnt18 - Covered T2,T3,T4
1 LcCnt19 - Covered T2,T3,T9
1 LcCnt20 - Covered T1,T2,T3
1 LcCnt21 - Covered T2,T3,T4
1 LcCnt22 - Covered T2,T3,T4
1 LcCnt23 - Covered T2,T3,T4
1 LcCnt24 - Covered T2,T3,T9
1 default - Not Covered
1 - 1 Covered T1,T2,T3
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((fsm_state_i inside {TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt})) -2-: 133 if (((((dec_lc_state_i[0] <= DecLcStScrap) && (trans_target_i[0] <= DecLcStScrap)) && (dec_lc_state_i[1] <= DecLcStScrap)) && (trans_target_i[1] <= DecLcStScrap))) -3-: 140 if (((lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))) -4-: 147 case (trans_target_i) -5-: 180 case (dec_lc_state_i)

Branches:
-1--2--3--4--5-StatusTests
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} - Not Covered
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} - Covered T9,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} - Covered T2,T4,T37
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} - Covered T9,T11,T42
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} - Covered T2,T12,T15
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} - Covered T2,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} - Covered T3,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} - Covered T4,T11,T12
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} - Covered T2,T3,T9
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} - Covered T3,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} - Covered T1,T2,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} - Covered T1,T2,T3
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} - Covered T1,T2,T3
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} - Covered T1,T2,T3
1 1 1 default - Not Covered
1 1 0 - - Covered T2,T3,T4
1 0 - - - Not Covered
1 - - - CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} Covered T1,T2,T3
1 - - - default Not Covered
0 - - - - Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition
Line No.TotalCoveredPercent
TOTAL666598.48
ALWAYS52666598.48
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
53 1 1
54 1 1
55 1 1
63 1 1
66 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
73 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1
91 1 1
92 1 1
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
99 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
108 1 1
109 1 1
Exclude Annotation: VC_COV_UNR
118 1 1
119 1 1
120 1 1
121 1 1
MISSING_ELSE
MISSING_ELSE
125 1 1
133 1 1
140 1 1
147 1 1
148 excluded
Exclude Annotation: VC_COV_UNR
149 1 1
150 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
172 1 1
175 0 1
180 1 1
201 1 1
Exclude Annotation: VC_COV_UNR
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       63
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && (fsm_state_i == IdleSt))
             -----------1----------    ----------2----------    -----3-----    -----------4-----------
-1--2--3--4-StatusTests
-011CoveredT1,T2,T3
-101CoveredT37,T5,T6
-110Not Covered
-111CoveredT37,T38,T39

 LINE       63
 SUB-EXPRESSION (fsm_state_i == IdleSt)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || 
      2  (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))
-1--2-StatusTestsExclude Annotation
00CoveredT37,T38,T39
01Not Covered
10Excluded VC_COV_UNR

 LINE       66
 SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
                -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT37,T38,T39
1CoveredT39,T40,T41

 LINE       66
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------
-1-StatusTests
0CoveredT37,T38,T39
1CoveredT39,T40,T41

 LINE       118
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       133
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i[0] <= DecLcStScrap) && 
      2  (trans_target_i[0] <= DecLcStScrap) && 
      3  (dec_lc_state_i[1] <= DecLcStScrap) && 
      4  (trans_target_i[1] <= DecLcStScrap))
-1--2--3--4-StatusTestsExclude Annotation
0111Excluded VC_COV_UNR
1011Not Covered
1101Excluded VC_COV_UNR
1110Not Covered
1111CoveredT1,T2,T3

 LINE       140
 EXPRESSION 
 Number  Term
      1  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || 
      2  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition
Line No.TotalCoveredPercent
Branches 56 54 96.43
IF 63 3 3 100.00
IF 73 28 28 100.00
IF 125 25 23 92.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if ((((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i) && (fsm_state_i == IdleSt))) -2-: 66 if (((dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})))

Branches:
-1--2-StatusTests
1 1 Covered T39,T40,T41
1 0 Covered T37,T38,T39
0 - Covered T1,T2,T3


LineNo. Expression -1-: 73 if ((fsm_state_i inside {CntIncrSt, CntProgSt, TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt})) -2-: 84 case (lc_cnt_i) -3-: 118 if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}))

Branches:
-1--2--3-StatusTestsExclude Annotation
1 LcCnt0 - Covered T2,T4,T11
1 LcCnt1 - Covered T2,T4,T11
1 LcCnt2 - Covered T1,T2,T3
1 LcCnt3 - Covered T2,T3,T4
1 LcCnt4 - Covered T2,T3,T4
1 LcCnt5 - Covered T2,T3,T9
1 LcCnt6 - Covered T1,T2,T3
1 LcCnt7 - Covered T2,T3,T9
1 LcCnt8 - Covered T2,T3,T4
1 LcCnt9 - Covered T2,T3,T4
1 LcCnt10 - Covered T2,T3,T9
1 LcCnt11 - Covered T2,T3,T9
1 LcCnt12 - Covered T1,T2,T3
1 LcCnt13 - Covered T2,T3,T4
1 LcCnt14 - Covered T1,T2,T3
1 LcCnt15 - Covered T2,T3,T4
1 LcCnt16 - Covered T2,T3,T9
1 LcCnt17 - Covered T2,T3,T9
1 LcCnt18 - Covered T2,T3,T4
1 LcCnt19 - Covered T2,T3,T9
1 LcCnt20 - Covered T1,T2,T3
1 LcCnt21 - Covered T2,T3,T4
1 LcCnt22 - Covered T2,T3,T4
1 LcCnt23 - Covered T2,T3,T4
1 LcCnt24 - Covered T2,T3,T9
1 default - Excluded VC_COV_UNR
1 - 1 Covered T1,T2,T3
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((fsm_state_i inside {TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt})) -2-: 133 if (((((dec_lc_state_i[0] <= DecLcStScrap) && (trans_target_i[0] <= DecLcStScrap)) && (dec_lc_state_i[1] <= DecLcStScrap)) && (trans_target_i[1] <= DecLcStScrap))) -3-: 140 if (((lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))) -4-: 147 case (trans_target_i) -5-: 180 case (dec_lc_state_i)

Branches:
-1--2--3--4--5-StatusTestsExclude Annotation
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} - Excluded VC_COV_UNR
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} - Covered T9,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} - Covered T2,T4,T37
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} - Covered T9,T11,T42
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} - Covered T2,T12,T15
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} - Covered T2,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} - Covered T3,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} - Covered T4,T11,T12
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} - Covered T2,T3,T9
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} - Covered T3,T4,T11
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} - Covered T1,T2,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} - Covered T1,T2,T3
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} - Covered T1,T2,T3
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} - Covered T2,T3,T4
1 1 1 {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} - Covered T1,T2,T3
1 1 1 default - Not Covered
1 1 0 - - Covered T2,T3,T4
1 0 - - - Not Covered
1 - - - CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} Covered T1,T2,T3
1 - - - default Excluded VC_COV_UNR
0 - - - - Covered T1,T2,T3

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