Module Definition
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Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Toggle Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
clk1_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
sel_i No No No INPUT
clk_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT


Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 58398783 58397159 0 0
selKnown1 81283939 81282315 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 58398783 58397159 0 0
T1 14 13 0 0
T2 267729 267727 0 0
T3 295908 295906 0 0
T4 112652 112651 0 0
T8 122 120 0 0
T9 12 10 0 0
T10 2 0 0 0
T11 96 94 0 0
T12 97 95 0 0
T13 70 68 0 0
T14 1 4 0 0
T15 0 282958 0 0
T16 0 180123 0 0
T17 0 203385 0 0
T18 0 105750 0 0
T19 0 255018 0 0
T20 0 78623 0 0
T21 0 187473 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 81283939 81282315 0 0
T1 9722 9721 0 0
T2 158591 158590 0 0
T3 153030 153029 0 0
T4 158766 158766 0 0
T5 2 1 0 0
T6 4 3 0 0
T7 0 3 0 0
T8 22518 22517 0 0
T9 4271 4270 0 0
T10 1486 1485 0 0
T11 32417 32416 0 0
T12 39821 39820 0 0
T13 26262 26261 0 0
T22 0 3 0 0
T23 0 1 0 0
T24 0 4 0 0
T25 0 5 0 0
T26 0 2 0 0
T27 0 3 0 0
T28 0 3 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 1 0 0 0
T35 1 0 0 0
T36 1 0 0 0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
clk1_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
sel_i No No No INPUT
clk_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
clk1_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
sel_i No No No INPUT
clk_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 58349847 58349035 0 0
selKnown1 81283003 81282191 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 58349847 58349035 0 0
T2 267629 267628 0 0
T3 295813 295812 0 0
T4 111989 111989 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T11 1 0 0 0
T12 1 0 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 0 282958 0 0
T16 0 180123 0 0
T17 0 203385 0 0
T18 0 105750 0 0
T19 0 255018 0 0
T20 0 78623 0 0
T21 0 187473 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 81283003 81282191 0 0
T1 9722 9721 0 0
T2 158591 158590 0 0
T3 153030 153029 0 0
T4 158766 158766 0 0
T8 22518 22517 0 0
T9 4271 4270 0 0
T10 1486 1485 0 0
T11 32417 32416 0 0
T12 39821 39820 0 0
T13 26262 26261 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 48936 48124 0 0
selKnown1 936 124 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 48936 48124 0 0
T1 14 13 0 0
T2 100 99 0 0
T3 95 94 0 0
T4 663 662 0 0
T8 121 120 0 0
T9 11 10 0 0
T10 1 0 0 0
T11 95 94 0 0
T12 96 95 0 0
T13 69 68 0 0
T14 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 936 124 0 0
T5 2 1 0 0
T6 4 3 0 0
T7 0 3 0 0
T22 0 3 0 0
T23 0 1 0 0
T24 0 4 0 0
T25 0 5 0 0
T26 0 2 0 0
T27 0 3 0 0
T28 0 3 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 1 0 0 0
T35 1 0 0 0
T36 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%