Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.77 98.42 72.07 96.47 66.67 95.14 97.83


Total modules in report: 52
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_mubi4_dec 0.00 0.00
prim_count 2.15 2.15
prim_generic_clock_inv 66.67 66.67
prim_clock_inv 66.67 66.67
lc_ctrl_state_transition 70.95 96.77 25.00 91.07
prim_cdc_rand_delay 75.00 75.00
prim_clock_mux2 75.00 75.00
lc_ctrl_fsm 83.20 95.48 68.00 65.00 94.20 93.33
prim_onehot_check 85.71 100.00 71.43
lc_ctrl_state_decode 87.76 100.00 66.67 96.61
tlul_adapter_host 87.92 93.33 65.00 93.33 100.00
dmi_jtag_tap 88.24 88.24
prim_sync_reqack 88.67 94.59 71.43 100.00
prim_generic_clock_mux2 91.67 100.00 75.00 100.00
dmi_jtag 95.56 95.56
dmi_cdc 96.36 96.36
lc_ctrl_kmac_if 96.67 100.00 100.00 83.33 100.00 100.00
lc_ctrl_signal_decode 96.69 98.41 91.67 100.00
lc_ctrl 96.76 100.00 100.00 98.97 100.00 84.85
prim_fifo_async 96.86 96.86
prim_fifo_async ( parameter Width=34,Depth=1,OutputZeroIfEmpty=0,DepthW=1,PTRV_W=1,PTR_WIDTH=1 ) 94.81 94.81
prim_fifo_async ( parameter Width=41,Depth=1,OutputZeroIfEmpty=0,DepthW=1,PTRV_W=1,PTR_WIDTH=1 ) 98.91 98.91
lc_ctrl_reg_top 100.00 100.00 100.00 100.00 100.00
lc_ctrl_fsm_cov_if 100.00 100.00 100.00
lc_ctrl_csr_assert_fpv 100.00 100.00
prim_lc_sync 100.00 100.00 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=8,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sender 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_rsp_intg_chk 100.00 100.00 100.00
prim_sparse_fsm_flop 100.00 100.00 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_rsp_intg_gen 100.00 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
tlul_adapter_reg 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_esc_receiver 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_flop 100.00 100.00
prim_flop_2sync 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00
prim_sync_reqack_data ( parameter Width=128,DataSrc2Dst=1,DataReg=0 ) 100.00 100.00
prim_sync_reqack_data ( parameter Width=129,DataSrc2Dst=0,DataReg=1 ) 100.00 100.00
prim_generic_flop 100.00 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_sec_anchor_flop
prim_buf
tb
prim_sec_anchor_buf
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%