LC_CTRL Lint Results
Thursday June 13 2024 19:02:12 UTC
Branch: os_regression
Tool: ASCENTLINT
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
0 |
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0 |
220 |
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Messages for Build Mode 'default'
Lint Infos
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:99 Next state register 'gen_rz_hs_protocol.src_fsm_d' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:151 Next state register 'gen_rz_hs_protocol.dst_fsm_d' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:253 Next state register 'gen_nrz_hs_protocol.src_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:297 Next state register 'gen_nrz_hs_protocol.dst_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_diff_decode.sv:158 Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: dmi_jtag.sv:223 Next state register 'state_d' is not always assigned in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: dmi_jtag_tap.sv:297 Next state register 'tap_state_d' has no assignment in the default branch of the case statement for this finite state machine New
I NESTED_SUBPROG: lc_ctrl_pkg.sv:201 Function 'lc_tx_or' is called from within a function New
I NESTED_SUBPROG: lc_ctrl_pkg.sv:208 Function 'lc_tx_and' is called from within a function New
I NESTED_SUBPROG: tlul_pkg.sv:143 Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function New
I VAR_INDEX_WRITE: lc_ctrl.sv:413 Variable range select expression 'transition_token_d[k * 32 +: 32]' encountered New
I VAR_INDEX_WRITE: lc_ctrl.sv:447 Variable range select expression 'transition_token_d[k * 32 +: 32]' encountered New
I CASE_INC: lc_ctrl_fsm.sv:242 Case statement tag not specified for value 'b0000000000000000 and many other values New
I CASE_INC: lc_ctrl_kmac_if.sv:164 Case statement tag not specified for value 'b00000000 and many other values New
I CASE_INC: lc_ctrl_signal_decode.sv:76 Case statement tag not specified for value 'b0000000000000000 and many other values New
I CASE_INC: lc_ctrl_signal_decode.sv:93 Case statement New
I CASE_INC: lc_ctrl_state_decode.sv:57 Case statement tag not specified for value 'b0000000000000000 and many other values New
I CASE_INC: lc_ctrl_state_decode.sv:75 Case statement New
I CASE_INC: lc_ctrl_state_decode.sv:101 Case statement New
I CASE_INC: lc_ctrl_state_decode.sv:132 Case statement tag not specified for value 'b0000 and 13 other values New
I CASE_INC: lc_ctrl_state_transition.sv:84 Case statement New
I CASE_INC: lc_ctrl_state_transition.sv:147 Case statement tag not specified for value 16777216 ('h1000000) and many other values New
I CASE_INC: lc_ctrl_state_transition.sv:180 Case statement tag not specified for value 16777216 ('h1000000) and many other values New
I CASE_INC: prim_alert_sender.sv:199 Case statement tag not specified for value 'b111 New
I CASE_INC: prim_diff_decode.sv:115 Case statement tag not specified for value 'b11 New
I CASE_INC: prim_esc_receiver.sv:168 Case statement tag not specified for value 'b101 and 2 other values New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I CASE_INC: dmi_jtag.sv:157 Case statement tag not specified for value 'b101 and 2 other values New
I CASE_INC: dmi_jtag.sv:183 Case statement tag not specified for value 'b01 New
I CASE_INC: dmi_jtag.sv:214 Case statement tag not specified for value 'b00 and 1 other value New
I CASE_INC: dmi_jtag_tap.sv:155 Case statement tag not specified for value 'b00010 and 26 other values New
I CASE_INC: dmi_jtag_tap.sv:176 Case statement tag not specified for value 'b00000 and 28 other values New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:495 Declaration range '[0:0]' of 'claim_transition_if_flds_we' has a length of one New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:534 Declaration range '[0:0]' of 'transition_cmd_flds_we' has a length of one New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:598 Declaration range '[0:0]' of 'transition_token_0_flds_we' has a length of one New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:622 Declaration range '[0:0]' of 'transition_token_1_flds_we' has a length of one New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:646 Declaration range '[0:0]' of 'transition_token_2_flds_we' has a length of one New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:670 Declaration range '[0:0]' of 'transition_token_3_flds_we' has a length of one New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:693 Declaration range '[0:0]' of 'transition_target_flds_we' has a length of one New
I ONE_BIT_VEC: lc_ctrl_reg_top.sv:716 Declaration range '[0:0]' of 'otp_vendor_test_ctrl_flds_we' has a length of one New
I ONE_BIT_VEC: prim_buf.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'lc_ctrl.u_prim_mubi4_dec.gen_bits[0].u_prim_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_buf.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'lc_ctrl.u_prim_mubi4_dec.gen_bits[0].u_prim_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:27 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:26 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_xnor2.sv:21 Declaration range '[Width - 1:0]' ([0:0]) of 'in0_i' has a length of one, instance 'lc_ctrl.u_prim_esc_receiver0.u_decode_esc.gen_no_async.u_xnor2_sigint' of module 'prim_xnor2' (Width=1) New
I ONE_BIT_VEC: prim_xnor2.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'in1_i' has a length of one, instance 'lc_ctrl.u_prim_esc_receiver0.u_decode_esc.gen_no_async.u_xnor2_sigint' of module 'prim_xnor2' (Width=1) New
I ONE_BIT_VEC: prim_xnor2.sv:23 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'lc_ctrl.u_prim_esc_receiver0.u_decode_esc.gen_no_async.u_xnor2_sigint' of module 'prim_xnor2' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'lc_ctrl.u_prim_mubi4_dec.gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'lc_ctrl.u_prim_mubi4_dec.gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'lc_ctrl.u_prim_mubi4_dec.gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:13 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:15 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:18 Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'lc_ctrl.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_xnor2.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in0_i' has a length of one, instance 'lc_ctrl.u_prim_esc_receiver0.u_decode_esc.gen_no_async.u_xnor2_sigint.gen_generic.u_impl_generic' of module 'prim_generic_xnor2' (Width=1) New
I ONE_BIT_VEC: prim_generic_xnor2.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'in1_i' has a length of one, instance 'lc_ctrl.u_prim_esc_receiver0.u_decode_esc.gen_no_async.u_xnor2_sigint.gen_generic.u_impl_generic' of module 'prim_generic_xnor2' (Width=1) New
I ONE_BIT_VEC: prim_generic_xnor2.sv:12 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'lc_ctrl.u_prim_esc_receiver0.u_decode_esc.gen_no_async.u_xnor2_sigint.gen_generic.u_impl_generic' of module 'prim_generic_xnor2' (Width=1) New
I ONE_BIT_VEC: prim_lc_sync.sv:30 Declaration range '[NumCopies - 1:0]' ([0:0]) of 'lc_en_o' has a length of one, instance 'lc_ctrl.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack' of module 'prim_lc_sync' (NumCopies=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'lc_ctrl.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'lc_ctrl.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_subreg.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:25 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:29 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:34 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:35 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:39 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:17 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:24 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:28 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'lc_ctrl.u_reg.u_claim_transition_if_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'lc_ctrl.u_reg.u_alert_test_fatal_prog_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:14 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'lc_ctrl.u_reg.u_alert_test_fatal_prog_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:19 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'lc_ctrl.u_reg.u_alert_test_fatal_prog_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:20 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'lc_ctrl.u_reg.u_alert_test_fatal_prog_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'lc_ctrl.u_reg.u_alert_test_fatal_prog_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: tlul_adapter_host.sv:64 Declaration range '[g_multiple_reqs.ReqNumW - 1:0]' ([0:0]) of 'g_multiple_reqs.ReqNumOne' has a length of one, instance 'lc_ctrl.u_tap_tlul_host' of module 'tlul_adapter_host' (MAX_REQS=2,g_multiple_reqs.ReqNumW=1 ('$clog2(MAX_REQS)')) New
I ONE_BIT_VEC: tlul_adapter_host.sv:66 Declaration range '[g_multiple_reqs.ReqNumW - 1:0]' ([0:0]) of 'g_multiple_reqs.source_d' has a length of one, instance 'lc_ctrl.u_tap_tlul_host' of module 'tlul_adapter_host' (MAX_REQS=2,g_multiple_reqs.ReqNumW=1 ('$clog2(MAX_REQS)')) New
I ONE_BIT_VEC: tlul_adapter_host.sv:67 Declaration range '[g_multiple_reqs.ReqNumW - 1:0]' ([0:0]) of 'g_multiple_reqs.source_q' has a length of one, instance 'lc_ctrl.u_tap_tlul_host' of module 'tlul_adapter_host' (MAX_REQS=2,g_multiple_reqs.ReqNumW=1 ('$clog2(MAX_REQS)')) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tap_tl_d2h' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one New
I EXPLICIT_BITLEN: prim_esc_receiver.sv:115 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_esc_receiver.sv:118 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I MIN_NAME_LEN: lc_ctrl.sv:411 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl.sv:418 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl.sv:445 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl.sv:452 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_fsm.sv:147 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:151 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:151 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:156 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:182 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:182 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:187 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:200 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:200 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:207 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_pkg.sv:207 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:33 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:37 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:41 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:47 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:52 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:58 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:62 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:68 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:73 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:78 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:84 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:87 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:90 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:93 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:96 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:99 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:102 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:105 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:108 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:111 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:114 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:117 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:122 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:126 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:131 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:134 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:139 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:143 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:147 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:151 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:155 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:159 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:163 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:168 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:171 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:177 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:180 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:185 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: lc_ctrl_reg_pkg.sv:189 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:85 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:111 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:217 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:243 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:349 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:375 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:481 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:507 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:25 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:21 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:24 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:14 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:19 Name 'q' is shorter than minimum length 2 New
I ZERO_BASED: dm_pkg.sv:236 Declaration range '[31:18]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:236 Declaration range '[31:18]' of 'dtmcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:236 Declaration range '[31:18]' of 'zero1' is not zero-based New
I ZERO_BASED: dm_pkg.sv:240 Declaration range '[14:12]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:240 Declaration range '[14:12]' of 'dtmcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:240 Declaration range '[14:12]' of 'idle' is not zero-based New
I ZERO_BASED: dm_pkg.sv:241 Declaration range '[11:10]' of 'dmistat' is not zero-based New
I ZERO_BASED: dm_pkg.sv:241 Declaration range '[11:10]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:241 Declaration range '[11:10]' of 'dtmcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:242 Declaration range '[9:4]' of 'abits' is not zero-based New
I ZERO_BASED: dm_pkg.sv:242 Declaration range '[9:4]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:242 Declaration range '[9:4]' of 'dtmcs_t' is not zero-based New
I CONST_OUTPUT: lc_ctrl.sv:304 Output 'hw_rev_o.product_id' is driven by constant zeros New
I CONST_OUTPUT: lc_ctrl.sv:304 Output 'hw_rev_o.reserved' is driven by constant zeros New
I CONST_OUTPUT: lc_ctrl.sv:304 Output 'hw_rev_o.revision_id' is driven by constant zeros New
I CONST_OUTPUT: lc_ctrl.sv:304 Output 'hw_rev_o.silicon_creator_id' is driven by constant zeros New
I CONST_OUTPUT: lc_ctrl.sv:706 Output 'strap_en_override_o' is driven by constant zero by port 'u_lc_ctrl_fsm.strap_en_override_o' New
I CONST_OUTPUT: lc_ctrl_fsm.sv:625 Output 'strap_en_override_o' is driven by constant zero New
I CONST_OUTPUT: tlul_adapter_reg.sv:91 Output 'addr_o[1:0]' is driven by constant zeros New
I CONST_OUTPUT: tlul_adapter_reg.sv:195 Output 'intg_error_o' is driven by constant zero New
Lint Warnings
W STAR_PORT_CONN_USE: prim_flop_2sync.sv:35 '.*' wild card port connection encountered on instance 'gen_generic.u_impl_generic' New
Lint Errors
E IFDEF_CODE: prim_generic_flop_2sync.sv:35 Assignment to 'unused_sig' contained within `else block at prim_generic_flop_2sync.sv:33 prim_generic_flop_2sync.sv:33 New
Past Results