Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106742386

1

T1

274971

T2

984

T3

1421

auto[1]

1401741

1

T1

99

T4

297

T5

792

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106752810

1

T1

274773

T2

984

T3

1421

auto[1]

1391317

1

T1

297

T4

198

T5

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7570296	1			T1	4868		T2	106		T3	109
auto[IdleSt]	21819666	1			T1	149487		T2	878		T3	1312
auto[ClkMuxSt]	35604	1			T1	52		T10	1		T4	7
auto[CntIncrSt]	35327	1			T1	52		T10	1		T4	7
auto[CntProgSt]	1614061	1			T1	86		T10	2		T4	67
auto[TransCheckSt]	27659	1			T1	41		T10	1		T4	7
auto[TokenHashSt]	43721693	1			T1	676		T10	18		T4	76
auto[FlashRmaSt]	29300	1			T1	25		T4	7		T18	6
auto[TokenCheck0St]	12935	1			T1	15		T4	7		T18	6
auto[TokenCheck1St]	9665	1			T1	6		T4	7		T18	6
auto[TransProgSt]	456097	1			T1	12		T4	80		T18	78
auto[PostTransSt]	12930710	1			T1	115867		T10	762		T4	1761
auto[ScrapSt]	302942	1			T19	40		T36	3		T14	2084
auto[EscalateSt]	7003661	1			T1	3883		T4	1154		T5	1634
auto[InvalidSt]	12572438	1			T4	657		T18	220		T23	907

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2073	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12572438	1			T4	657		T18	220		T23	907
EscalateSt	7003661	1			T1	3883		T4	1154		T5	1634
ScrapSt	302942	1			T19	40		T36	3		T14	2084
PostTransSt	12930710	1			T1	115867		T10	762		T4	1761
TransProgSt	456097	1			T1	12		T4	80		T18	78
TokenCheck1St	9665	1			T1	6		T4	7		T18	6
TokenCheck0St	12935	1			T1	15		T4	7		T18	6
FlashRmaSt	29300	1			T1	25		T4	7		T18	6
TokenHashSt	43721693	1			T1	676		T10	18		T4	76
TransCheckSt	27659	1			T1	41		T10	1		T4	7
CntProgSt	1614061	1			T1	86		T10	2		T4	67
CntIncrSt	35327	1			T1	52		T10	1		T4	7
ClkMuxSt	35604	1			T1	52		T10	1		T4	7
IdleSt	21819666	1			T1	149487		T2	878		T3	1312
ResetSt	7570296	1			T1	4868		T2	106		T3	109
arcs[ResetSt=>IdleSt]	54558	1			T1	53		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	307	1			T19	1		T36	1		T14	5
arcs[IdleSt=>ClkMuxSt]	35392	1			T1	52		T10	1		T4	7
arcs[ClkMuxSt=>CntIncrSt]	35327	1			T1	52		T10	1		T4	7
arcs[CntIncrSt=>PostTransSt]	1830	1			T1	7		T7	36		T14	52
arcs[CntIncrSt=>CntProgSt]	33431	1			T1	45		T10	1		T4	7
arcs[CntProgSt=>PostTransSt]	4606	1			T1	4		T5	13		T7	34
arcs[CntProgSt=>TransCheckSt]	27659	1			T1	41		T10	1		T4	7
arcs[TransCheckSt=>PostTransSt]	3641	1			T1	7		T7	25		T21	28
arcs[TransCheckSt=>TokenHashSt]	23944	1			T1	34		T10	1		T4	7
arcs[TokenHashSt=>PostTransSt]	10308	1			T1	19		T10	1		T12	83
arcs[TokenHashSt=>FlashRmaSt]	13046	1			T1	15		T4	7		T18	6
arcs[FlashRmaSt=>TokenCheck0St]	12935	1			T1	15		T4	7		T18	6
arcs[TokenCheck0St=>PostTransSt]	3246	1			T1	9		T7	22		T21	16
arcs[TokenCheck0St=>TokenCheck1St]	9665	1			T1	6		T4	7		T18	6
arcs[TokenCheck1St=>PostTransSt]	643	1			T7	3		T21	9		T22	9
arcs[TransProgSt=>PostTransSt]	8149	1			T1	6		T4	7		T18	6
arcs[IdleSt=>EscalateSt]	180	1			T49	10		T47	7		T50	4
arcs[ClkMuxSt=>EscalateSt]	65	1			T36	1		T47	4		T48	2
arcs[CntIncrSt=>EscalateSt]	66	1			T36	3		T49	2		T47	1
arcs[CntProgSt=>EscalateSt]	1166	1			T36	40		T49	41		T47	19
arcs[TransCheckSt=>EscalateSt]	74	1			T36	1		T50	8		T52	1
arcs[TokenHashSt=>EscalateSt]	590	1			T36	11		T49	15		T47	9
arcs[FlashRmaSt=>EscalateSt]	111	1			T36	3		T49	4		T47	1
arcs[TokenCheck0St=>EscalateSt]	24	1			T48	1		T50	2		T51	1
arcs[TokenCheck1St=>EscalateSt]	126	1			T36	5		T49	3		T47	4
arcs[TransProgSt=>EscalateSt]	747	1			T36	19		T49	21		T47	14
arcs[PostTransSt=>EscalateSt]	4790	1			T1	4		T5	13		T7	34
arcs[InvalidSt=>EscalateSt]	14609	1			T4	5		T18	3		T23	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7570127	1			T1	4868		T2	106		T3	109
auto[0]	auto[IdleSt]	21819544	1			T1	149487		T2	878		T3	1312
auto[0]	auto[ClkMuxSt]	35561	1			T1	52		T10	1		T4	7
auto[0]	auto[CntIncrSt]	35284	1			T1	52		T10	1		T4	7
auto[0]	auto[CntProgSt]	1613278	1			T1	86		T10	2		T4	67
auto[0]	auto[TransCheckSt]	27613	1			T1	41		T10	1		T4	7
auto[0]	auto[TokenHashSt]	43721320	1			T1	676		T10	18		T4	76
auto[0]	auto[FlashRmaSt]	29222	1			T1	25		T4	7		T18	6
auto[0]	auto[TokenCheck0St]	12917	1			T1	15		T4	7		T18	6
auto[0]	auto[TokenCheck1St]	9571	1			T1	6		T4	7		T18	6
auto[0]	auto[TransProgSt]	455591	1			T1	12		T4	80		T18	78
auto[0]	auto[PostTransSt]	12928312	1			T1	115866		T10	762		T4	1761
auto[0]	auto[ScrapSt]	302902	1			T19	40		T36	2		T14	2084
auto[0]	auto[EscalateSt]	5613981	1			T1	3785		T4	860		T5	850
auto[0]	auto[InvalidSt]	12565090	1			T4	654		T18	220		T23	902
auto[1]	auto[ResetSt]	169	1			T36	3		T49	1		T47	9
auto[1]	auto[IdleSt]	122	1			T49	10		T47	4		T50	3
auto[1]	auto[ClkMuxSt]	43	1			T47	4		T48	2		T50	1
auto[1]	auto[CntIncrSt]	43	1			T36	3		T49	1		T47	1
auto[1]	auto[CntProgSt]	783	1			T36	27		T49	23		T47	16
auto[1]	auto[TransCheckSt]	46	1			T50	5		T228	5		T229	5
auto[1]	auto[TokenHashSt]	373	1			T36	7		T49	9		T47	8
auto[1]	auto[FlashRmaSt]	78	1			T36	3		T49	2		T47	1
auto[1]	auto[TokenCheck0St]	18	1			T48	1		T50	2		T51	1
auto[1]	auto[TokenCheck1St]	94	1			T36	4		T49	1		T47	4
auto[1]	auto[TransProgSt]	506	1			T36	15		T49	15		T47	9
auto[1]	auto[PostTransSt]	2398	1			T1	1		T5	8		T7	15
auto[1]	auto[ScrapSt]	40	1			T36	1		T49	2		T50	1
auto[1]	auto[EscalateSt]	1389680	1			T1	98		T4	294		T5	784
auto[1]	auto[InvalidSt]	7348	1			T4	3		T23	5		T7	93

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7570107	1			T1	4868		T2	106		T3	109
auto[0]	auto[IdleSt]	21819554	1			T1	149487		T2	878		T3	1312
auto[0]	auto[ClkMuxSt]	35559	1			T1	52		T10	1		T4	7
auto[0]	auto[CntIncrSt]	35283	1			T1	52		T10	1		T4	7
auto[0]	auto[CntProgSt]	1613317	1			T1	86		T10	2		T4	67
auto[0]	auto[TransCheckSt]	27606	1			T1	41		T10	1		T4	7
auto[0]	auto[TokenHashSt]	43721311	1			T1	676		T10	18		T4	76
auto[0]	auto[FlashRmaSt]	29232	1			T1	25		T4	7		T18	6
auto[0]	auto[TokenCheck0St]	12920	1			T1	15		T4	7		T18	6
auto[0]	auto[TokenCheck1St]	9582	1			T1	6		T4	7		T18	6
auto[0]	auto[TransProgSt]	455606	1			T1	12		T4	80		T18	78
auto[0]	auto[PostTransSt]	12928264	1			T1	115864		T10	762		T4	1761
auto[0]	auto[ScrapSt]	302902	1			T19	40		T36	2		T14	2084
auto[0]	auto[EscalateSt]	5624317	1			T1	3589		T4	958		T5	1144
auto[0]	auto[InvalidSt]	12565177	1			T4	655		T18	217		T23	906
auto[1]	auto[ResetSt]	189	1			T36	4		T49	1		T47	7
auto[1]	auto[IdleSt]	112	1			T49	1		T47	7		T50	1
auto[1]	auto[ClkMuxSt]	45	1			T36	1		T47	3		T50	1
auto[1]	auto[CntIncrSt]	44	1			T36	1		T49	1		T47	1
auto[1]	auto[CntProgSt]	744	1			T36	26		T49	32		T47	6
auto[1]	auto[TransCheckSt]	53	1			T36	1		T50	7		T52	1
auto[1]	auto[TokenHashSt]	382	1			T36	11		T49	10		T47	6
auto[1]	auto[FlashRmaSt]	68	1			T36	3		T49	3		T48	1
auto[1]	auto[TokenCheck0St]	15	1			T50	2		T230	1		T228	1
auto[1]	auto[TokenCheck1St]	83	1			T36	1		T49	3		T47	3
auto[1]	auto[TransProgSt]	491	1			T36	12		T49	15		T47	8
auto[1]	auto[PostTransSt]	2446	1			T1	3		T5	5		T7	19
auto[1]	auto[ScrapSt]	40	1			T36	1		T50	2		T231	2
auto[1]	auto[EscalateSt]	1379344	1			T1	294		T4	196		T5	490
auto[1]	auto[InvalidSt]	7261	1			T4	2		T18	3		T23	1