| T815 |
/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1574864866 |
|
|
Apr 21 01:17:56 PM PDT 24 |
Apr 21 01:18:09 PM PDT 24 |
393760037 ps |
| T816 |
/workspace/coverage/default/48.lc_ctrl_jtag_access.1307794954 |
|
|
Apr 21 01:20:16 PM PDT 24 |
Apr 21 01:20:19 PM PDT 24 |
252106109 ps |
| T163 |
/workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3564024858 |
|
|
Apr 21 01:19:46 PM PDT 24 |
Apr 21 01:26:34 PM PDT 24 |
25293469133 ps |
| T817 |
/workspace/coverage/default/30.lc_ctrl_sec_token_mux.756184064 |
|
|
Apr 21 01:19:10 PM PDT 24 |
Apr 21 01:19:19 PM PDT 24 |
845506579 ps |
| T818 |
/workspace/coverage/default/35.lc_ctrl_sec_token_digest.3663791515 |
|
|
Apr 21 01:19:22 PM PDT 24 |
Apr 21 01:19:34 PM PDT 24 |
1020858616 ps |
| T819 |
/workspace/coverage/default/39.lc_ctrl_stress_all.3469888083 |
|
|
Apr 21 01:19:41 PM PDT 24 |
Apr 21 01:20:16 PM PDT 24 |
3559722095 ps |
| T820 |
/workspace/coverage/default/45.lc_ctrl_sec_token_mux.242717198 |
|
|
Apr 21 01:20:01 PM PDT 24 |
Apr 21 01:20:10 PM PDT 24 |
426218515 ps |
| T821 |
/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2047920408 |
|
|
Apr 21 01:16:52 PM PDT 24 |
Apr 21 01:17:07 PM PDT 24 |
1380086640 ps |
| T822 |
/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1503454459 |
|
|
Apr 21 01:16:00 PM PDT 24 |
Apr 21 01:16:09 PM PDT 24 |
355290997 ps |
| T823 |
/workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3663895362 |
|
|
Apr 21 01:16:04 PM PDT 24 |
Apr 21 01:22:21 PM PDT 24 |
38248031318 ps |
| T824 |
/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1193820572 |
|
|
Apr 21 01:19:40 PM PDT 24 |
Apr 21 01:19:42 PM PDT 24 |
13867947 ps |
| T825 |
/workspace/coverage/default/25.lc_ctrl_jtag_access.2988609627 |
|
|
Apr 21 01:18:42 PM PDT 24 |
Apr 21 01:18:50 PM PDT 24 |
727707713 ps |
| T826 |
/workspace/coverage/default/24.lc_ctrl_sec_token_mux.117723125 |
|
|
Apr 21 01:18:42 PM PDT 24 |
Apr 21 01:18:50 PM PDT 24 |
309049156 ps |
| T170 |
/workspace/coverage/default/46.lc_ctrl_security_escalation.2249236349 |
|
|
Apr 21 01:20:08 PM PDT 24 |
Apr 21 01:20:15 PM PDT 24 |
259236313 ps |
| T827 |
/workspace/coverage/default/37.lc_ctrl_sec_token_digest.848568213 |
|
|
Apr 21 01:19:35 PM PDT 24 |
Apr 21 01:19:44 PM PDT 24 |
1018019882 ps |
| T828 |
/workspace/coverage/default/31.lc_ctrl_alert_test.1873172797 |
|
|
Apr 21 01:19:06 PM PDT 24 |
Apr 21 01:19:08 PM PDT 24 |
127278261 ps |
| T829 |
/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.503381866 |
|
|
Apr 21 01:18:33 PM PDT 24 |
Apr 21 01:18:34 PM PDT 24 |
35965625 ps |
| T830 |
/workspace/coverage/default/29.lc_ctrl_stress_all.4182070745 |
|
|
Apr 21 01:19:07 PM PDT 24 |
Apr 21 01:22:14 PM PDT 24 |
11774214041 ps |
| T831 |
/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3428477746 |
|
|
Apr 21 01:15:57 PM PDT 24 |
Apr 21 01:16:06 PM PDT 24 |
3140478478 ps |
| T45 |
/workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2109851335 |
|
|
Apr 21 01:17:32 PM PDT 24 |
Apr 21 01:30:08 PM PDT 24 |
115169685748 ps |
| T832 |
/workspace/coverage/default/33.lc_ctrl_prog_failure.1257876825 |
|
|
Apr 21 01:19:11 PM PDT 24 |
Apr 21 01:19:14 PM PDT 24 |
204462472 ps |
| T833 |
/workspace/coverage/default/33.lc_ctrl_sec_token_mux.2072703367 |
|
|
Apr 21 01:19:16 PM PDT 24 |
Apr 21 01:19:25 PM PDT 24 |
361415851 ps |
| T834 |
/workspace/coverage/default/44.lc_ctrl_state_post_trans.1671567895 |
|
|
Apr 21 01:20:01 PM PDT 24 |
Apr 21 01:20:04 PM PDT 24 |
75309343 ps |
| T835 |
/workspace/coverage/default/14.lc_ctrl_smoke.3181447420 |
|
|
Apr 21 01:17:42 PM PDT 24 |
Apr 21 01:17:44 PM PDT 24 |
61175248 ps |
| T836 |
/workspace/coverage/default/10.lc_ctrl_sec_mubi.2279888529 |
|
|
Apr 21 01:17:21 PM PDT 24 |
Apr 21 01:17:36 PM PDT 24 |
900740515 ps |
| T837 |
/workspace/coverage/default/15.lc_ctrl_prog_failure.168345704 |
|
|
Apr 21 01:17:49 PM PDT 24 |
Apr 21 01:17:53 PM PDT 24 |
80355556 ps |
| T838 |
/workspace/coverage/default/2.lc_ctrl_smoke.3228316205 |
|
|
Apr 21 01:15:47 PM PDT 24 |
Apr 21 01:15:51 PM PDT 24 |
159972146 ps |
| T839 |
/workspace/coverage/default/30.lc_ctrl_jtag_access.623137329 |
|
|
Apr 21 01:19:10 PM PDT 24 |
Apr 21 01:19:15 PM PDT 24 |
308068504 ps |
| T840 |
/workspace/coverage/default/10.lc_ctrl_stress_all.2976696705 |
|
|
Apr 21 01:17:18 PM PDT 24 |
Apr 21 01:19:40 PM PDT 24 |
17208459861 ps |
| T841 |
/workspace/coverage/default/46.lc_ctrl_smoke.2494092476 |
|
|
Apr 21 01:20:05 PM PDT 24 |
Apr 21 01:20:06 PM PDT 24 |
24022307 ps |
| T842 |
/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.157148071 |
|
|
Apr 21 01:15:49 PM PDT 24 |
Apr 21 01:16:02 PM PDT 24 |
908358984 ps |
| T843 |
/workspace/coverage/default/38.lc_ctrl_alert_test.3900080225 |
|
|
Apr 21 01:19:42 PM PDT 24 |
Apr 21 01:19:43 PM PDT 24 |
69388533 ps |
| T844 |
/workspace/coverage/default/28.lc_ctrl_prog_failure.877723080 |
|
|
Apr 21 01:19:07 PM PDT 24 |
Apr 21 01:19:11 PM PDT 24 |
203938476 ps |
| T845 |
/workspace/coverage/default/46.lc_ctrl_sec_mubi.1028938995 |
|
|
Apr 21 01:20:08 PM PDT 24 |
Apr 21 01:20:25 PM PDT 24 |
2643170291 ps |
| T846 |
/workspace/coverage/default/44.lc_ctrl_security_escalation.2973343693 |
|
|
Apr 21 01:19:58 PM PDT 24 |
Apr 21 01:20:09 PM PDT 24 |
2037856358 ps |
| T847 |
/workspace/coverage/default/34.lc_ctrl_state_post_trans.2936247766 |
|
|
Apr 21 01:19:18 PM PDT 24 |
Apr 21 01:19:26 PM PDT 24 |
117182536 ps |
| T848 |
/workspace/coverage/default/25.lc_ctrl_prog_failure.2910562084 |
|
|
Apr 21 01:18:43 PM PDT 24 |
Apr 21 01:18:46 PM PDT 24 |
63496042 ps |
| T849 |
/workspace/coverage/default/11.lc_ctrl_alert_test.1528377442 |
|
|
Apr 21 01:17:29 PM PDT 24 |
Apr 21 01:17:30 PM PDT 24 |
67359987 ps |
| T850 |
/workspace/coverage/default/25.lc_ctrl_smoke.1435877981 |
|
|
Apr 21 01:18:38 PM PDT 24 |
Apr 21 01:18:40 PM PDT 24 |
122167291 ps |
| T851 |
/workspace/coverage/default/20.lc_ctrl_prog_failure.960831197 |
|
|
Apr 21 01:18:23 PM PDT 24 |
Apr 21 01:18:26 PM PDT 24 |
109298087 ps |
| T852 |
/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3614579354 |
|
|
Apr 21 01:19:15 PM PDT 24 |
Apr 21 01:19:16 PM PDT 24 |
21890423 ps |
| T853 |
/workspace/coverage/default/12.lc_ctrl_smoke.1886191453 |
|
|
Apr 21 01:17:31 PM PDT 24 |
Apr 21 01:17:34 PM PDT 24 |
82037367 ps |
| T854 |
/workspace/coverage/default/38.lc_ctrl_sec_token_digest.610684305 |
|
|
Apr 21 01:19:40 PM PDT 24 |
Apr 21 01:19:50 PM PDT 24 |
278104921 ps |
| T855 |
/workspace/coverage/default/6.lc_ctrl_errors.418047034 |
|
|
Apr 21 01:16:39 PM PDT 24 |
Apr 21 01:16:51 PM PDT 24 |
879096846 ps |
| T856 |
/workspace/coverage/default/49.lc_ctrl_sec_token_mux.1972544971 |
|
|
Apr 21 01:20:23 PM PDT 24 |
Apr 21 01:20:38 PM PDT 24 |
2646240819 ps |
| T857 |
/workspace/coverage/default/33.lc_ctrl_sec_token_digest.434543304 |
|
|
Apr 21 01:19:17 PM PDT 24 |
Apr 21 01:19:40 PM PDT 24 |
1545091793 ps |
| T858 |
/workspace/coverage/default/0.lc_ctrl_errors.2564345500 |
|
|
Apr 21 01:15:28 PM PDT 24 |
Apr 21 01:15:45 PM PDT 24 |
1444403324 ps |
| T859 |
/workspace/coverage/default/6.lc_ctrl_sec_mubi.1057844762 |
|
|
Apr 21 01:16:49 PM PDT 24 |
Apr 21 01:17:01 PM PDT 24 |
773595875 ps |
| T860 |
/workspace/coverage/default/13.lc_ctrl_jtag_smoke.2641111239 |
|
|
Apr 21 01:17:35 PM PDT 24 |
Apr 21 01:17:43 PM PDT 24 |
1200735725 ps |
| T861 |
/workspace/coverage/default/15.lc_ctrl_sec_token_digest.747594112 |
|
|
Apr 21 01:17:56 PM PDT 24 |
Apr 21 01:18:08 PM PDT 24 |
808145394 ps |
| T862 |
/workspace/coverage/default/7.lc_ctrl_alert_test.2970193866 |
|
|
Apr 21 01:16:54 PM PDT 24 |
Apr 21 01:16:55 PM PDT 24 |
27899810 ps |
| T172 |
/workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3536434720 |
|
|
Apr 21 01:18:18 PM PDT 24 |
Apr 21 01:27:40 PM PDT 24 |
13712143766 ps |
| T863 |
/workspace/coverage/default/40.lc_ctrl_sec_token_digest.3305536061 |
|
|
Apr 21 01:19:55 PM PDT 24 |
Apr 21 01:20:04 PM PDT 24 |
1061955813 ps |
| T864 |
/workspace/coverage/default/47.lc_ctrl_state_post_trans.42226664 |
|
|
Apr 21 01:20:10 PM PDT 24 |
Apr 21 01:20:17 PM PDT 24 |
221804430 ps |
| T865 |
/workspace/coverage/default/30.lc_ctrl_sec_token_digest.992314196 |
|
|
Apr 21 01:19:10 PM PDT 24 |
Apr 21 01:19:22 PM PDT 24 |
1371423314 ps |
| T866 |
/workspace/coverage/default/25.lc_ctrl_stress_all.3341509246 |
|
|
Apr 21 01:18:50 PM PDT 24 |
Apr 21 01:19:36 PM PDT 24 |
8345734608 ps |
| T867 |
/workspace/coverage/default/36.lc_ctrl_prog_failure.2224483622 |
|
|
Apr 21 01:19:24 PM PDT 24 |
Apr 21 01:19:27 PM PDT 24 |
28563280 ps |
| T868 |
/workspace/coverage/default/34.lc_ctrl_security_escalation.1861040787 |
|
|
Apr 21 01:19:18 PM PDT 24 |
Apr 21 01:19:24 PM PDT 24 |
200772640 ps |
| T869 |
/workspace/coverage/default/19.lc_ctrl_sec_token_mux.2172116465 |
|
|
Apr 21 01:18:20 PM PDT 24 |
Apr 21 01:18:31 PM PDT 24 |
1777158167 ps |
| T870 |
/workspace/coverage/default/28.lc_ctrl_stress_all.1836418248 |
|
|
Apr 21 01:18:54 PM PDT 24 |
Apr 21 01:20:13 PM PDT 24 |
7562889958 ps |
| T871 |
/workspace/coverage/default/8.lc_ctrl_sec_mubi.3442249316 |
|
|
Apr 21 01:17:02 PM PDT 24 |
Apr 21 01:17:15 PM PDT 24 |
232124592 ps |
| T872 |
/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3682427615 |
|
|
Apr 21 01:17:48 PM PDT 24 |
Apr 21 01:17:50 PM PDT 24 |
29482155 ps |
| T873 |
/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2047437567 |
|
|
Apr 21 01:18:05 PM PDT 24 |
Apr 21 01:18:06 PM PDT 24 |
14649516 ps |
| T874 |
/workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2358653800 |
|
|
Apr 21 01:20:11 PM PDT 24 |
Apr 21 01:31:51 PM PDT 24 |
44905949428 ps |
| T875 |
/workspace/coverage/default/16.lc_ctrl_smoke.980994618 |
|
|
Apr 21 01:17:56 PM PDT 24 |
Apr 21 01:17:59 PM PDT 24 |
31665938 ps |
| T876 |
/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2202997132 |
|
|
Apr 21 01:15:31 PM PDT 24 |
Apr 21 01:15:50 PM PDT 24 |
3198042179 ps |
| T877 |
/workspace/coverage/default/12.lc_ctrl_state_post_trans.134291551 |
|
|
Apr 21 01:17:29 PM PDT 24 |
Apr 21 01:17:40 PM PDT 24 |
128241540 ps |
| T878 |
/workspace/coverage/default/33.lc_ctrl_sec_mubi.2582806571 |
|
|
Apr 21 01:19:16 PM PDT 24 |
Apr 21 01:19:29 PM PDT 24 |
2714877597 ps |
| T879 |
/workspace/coverage/default/9.lc_ctrl_errors.1930466060 |
|
|
Apr 21 01:17:05 PM PDT 24 |
Apr 21 01:17:20 PM PDT 24 |
548892265 ps |
| T108 |
/workspace/coverage/default/4.lc_ctrl_sec_cm.1168961488 |
|
|
Apr 21 01:16:27 PM PDT 24 |
Apr 21 01:16:49 PM PDT 24 |
412068069 ps |
| T122 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.350714718 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:51 PM PDT 24 |
22743510 ps |
| T130 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2812696024 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:54:45 PM PDT 24 |
140783294 ps |
| T128 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4222794579 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
85213449 ps |
| T164 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3113218746 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
28157657 ps |
| T214 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3429861741 |
|
|
Apr 21 12:54:30 PM PDT 24 |
Apr 21 12:54:31 PM PDT 24 |
15490509 ps |
| T123 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.973996479 |
|
|
Apr 21 12:55:08 PM PDT 24 |
Apr 21 12:55:10 PM PDT 24 |
24018009 ps |
| T215 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2887742123 |
|
|
Apr 21 12:54:21 PM PDT 24 |
Apr 21 12:54:23 PM PDT 24 |
22977413 ps |
| T154 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2961448512 |
|
|
Apr 21 12:54:25 PM PDT 24 |
Apr 21 12:54:28 PM PDT 24 |
134549026 ps |
| T152 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4158112520 |
|
|
Apr 21 12:54:56 PM PDT 24 |
Apr 21 12:54:58 PM PDT 24 |
59860734 ps |
| T153 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1380285863 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
208251113 ps |
| T119 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2713027914 |
|
|
Apr 21 12:54:38 PM PDT 24 |
Apr 21 12:54:40 PM PDT 24 |
41029282 ps |
| T129 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.185723784 |
|
|
Apr 21 12:54:56 PM PDT 24 |
Apr 21 12:54:58 PM PDT 24 |
22380127 ps |
| T880 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1984178082 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
251767444 ps |
| T150 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.455065581 |
|
|
Apr 21 12:54:29 PM PDT 24 |
Apr 21 12:54:32 PM PDT 24 |
315530597 ps |
| T223 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1284138040 |
|
|
Apr 21 12:54:47 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
357774000 ps |
| T120 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.4111145990 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
116874602 ps |
| T121 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2410651214 |
|
|
Apr 21 12:55:00 PM PDT 24 |
Apr 21 12:55:04 PM PDT 24 |
165385326 ps |
| T216 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1374115942 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
26551902 ps |
| T124 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1304530744 |
|
|
Apr 21 12:55:04 PM PDT 24 |
Apr 21 12:55:06 PM PDT 24 |
53055862 ps |
| T125 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3974068090 |
|
|
Apr 21 12:54:40 PM PDT 24 |
Apr 21 12:54:42 PM PDT 24 |
27488703 ps |
| T217 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3134406653 |
|
|
Apr 21 12:54:28 PM PDT 24 |
Apr 21 12:54:30 PM PDT 24 |
102586550 ps |
| T881 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2375485884 |
|
|
Apr 21 12:54:32 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
463419608 ps |
| T218 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3800818698 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:45 PM PDT 24 |
46805574 ps |
| T126 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3927175553 |
|
|
Apr 21 12:54:22 PM PDT 24 |
Apr 21 12:54:25 PM PDT 24 |
54954620 ps |
| T201 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3885670893 |
|
|
Apr 21 12:54:57 PM PDT 24 |
Apr 21 12:54:58 PM PDT 24 |
15557988 ps |
| T882 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.180713397 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:46 PM PDT 24 |
13086293 ps |
| T883 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.85673929 |
|
|
Apr 21 12:54:33 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
25331646 ps |
| T884 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.301804959 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:37 PM PDT 24 |
47606118 ps |
| T127 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1221363182 |
|
|
Apr 21 12:54:51 PM PDT 24 |
Apr 21 12:54:55 PM PDT 24 |
105441111 ps |
| T885 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4200319341 |
|
|
Apr 21 12:54:30 PM PDT 24 |
Apr 21 12:54:33 PM PDT 24 |
506804340 ps |
| T886 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.198155991 |
|
|
Apr 21 12:54:23 PM PDT 24 |
Apr 21 12:54:25 PM PDT 24 |
200443510 ps |
| T887 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.743971239 |
|
|
Apr 21 12:54:25 PM PDT 24 |
Apr 21 12:54:34 PM PDT 24 |
807941921 ps |
| T202 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2501530155 |
|
|
Apr 21 12:54:26 PM PDT 24 |
Apr 21 12:54:27 PM PDT 24 |
88481064 ps |
| T888 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.442933236 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
101660927 ps |
| T889 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.958113878 |
|
|
Apr 21 12:54:31 PM PDT 24 |
Apr 21 12:54:40 PM PDT 24 |
3544119182 ps |
| T219 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.168926654 |
|
|
Apr 21 12:54:35 PM PDT 24 |
Apr 21 12:54:36 PM PDT 24 |
87869694 ps |
| T890 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1771260296 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
1489020879 ps |
| T891 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1961466446 |
|
|
Apr 21 12:54:38 PM PDT 24 |
Apr 21 12:54:40 PM PDT 24 |
170828407 ps |
| T892 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1919489956 |
|
|
Apr 21 12:54:23 PM PDT 24 |
Apr 21 12:54:25 PM PDT 24 |
25355720 ps |
| T133 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3497697844 |
|
|
Apr 21 12:54:40 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
62865273 ps |
| T138 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2015343956 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:51 PM PDT 24 |
26618460 ps |
| T136 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3196972266 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:55 PM PDT 24 |
261532458 ps |
| T893 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.615944366 |
|
|
Apr 21 12:54:24 PM PDT 24 |
Apr 21 12:54:27 PM PDT 24 |
140820102 ps |
| T144 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4018172657 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:55 PM PDT 24 |
532025914 ps |
| T894 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3035441037 |
|
|
Apr 21 12:54:17 PM PDT 24 |
Apr 21 12:54:21 PM PDT 24 |
778928612 ps |
| T895 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3278833576 |
|
|
Apr 21 12:54:25 PM PDT 24 |
Apr 21 12:54:59 PM PDT 24 |
5746789281 ps |
| T220 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3287419986 |
|
|
Apr 21 12:54:32 PM PDT 24 |
Apr 21 12:54:33 PM PDT 24 |
29844934 ps |
| T221 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2588212876 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
48253629 ps |
| T896 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1805039309 |
|
|
Apr 21 12:54:44 PM PDT 24 |
Apr 21 12:54:46 PM PDT 24 |
43614449 ps |
| T897 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1984084511 |
|
|
Apr 21 12:54:24 PM PDT 24 |
Apr 21 12:54:26 PM PDT 24 |
91103533 ps |
| T898 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1590227433 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:47 PM PDT 24 |
185438215 ps |
| T899 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3040161130 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
55887051 ps |
| T900 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3950025305 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:46 PM PDT 24 |
320276706 ps |
| T901 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2871882362 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
3130652907 ps |
| T902 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4098791459 |
|
|
Apr 21 12:54:35 PM PDT 24 |
Apr 21 12:54:38 PM PDT 24 |
581224799 ps |
| T903 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.429069037 |
|
|
Apr 21 12:54:40 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
101071783 ps |
| T904 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2591125277 |
|
|
Apr 21 12:54:47 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
18654025 ps |
| T905 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.207574160 |
|
|
Apr 21 12:54:44 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
118118207 ps |
| T203 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1490729291 |
|
|
Apr 21 12:54:50 PM PDT 24 |
Apr 21 12:54:51 PM PDT 24 |
28067503 ps |
| T906 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2866713681 |
|
|
Apr 21 12:54:47 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
55459641 ps |
| T151 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2966255153 |
|
|
Apr 21 12:54:51 PM PDT 24 |
Apr 21 12:54:53 PM PDT 24 |
55081416 ps |
| T149 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.268531570 |
|
|
Apr 21 12:54:48 PM PDT 24 |
Apr 21 12:54:51 PM PDT 24 |
168288283 ps |
| T907 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1488393968 |
|
|
Apr 21 12:54:36 PM PDT 24 |
Apr 21 12:54:37 PM PDT 24 |
41850309 ps |
| T908 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1452258560 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:51 PM PDT 24 |
14787168 ps |
| T909 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2688281767 |
|
|
Apr 21 12:54:44 PM PDT 24 |
Apr 21 12:54:45 PM PDT 24 |
192847132 ps |
| T910 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4269285403 |
|
|
Apr 21 12:54:36 PM PDT 24 |
Apr 21 12:54:38 PM PDT 24 |
99647830 ps |
| T145 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2317624163 |
|
|
Apr 21 12:54:57 PM PDT 24 |
Apr 21 12:55:03 PM PDT 24 |
135104487 ps |
| T911 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.364231424 |
|
|
Apr 21 12:54:24 PM PDT 24 |
Apr 21 12:54:26 PM PDT 24 |
28149830 ps |
| T912 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.517954061 |
|
|
Apr 21 12:54:21 PM PDT 24 |
Apr 21 12:54:23 PM PDT 24 |
90135060 ps |
| T913 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2637221651 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
1359430147 ps |
| T914 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.172847910 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:36 PM PDT 24 |
102591403 ps |
| T915 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2373163150 |
|
|
Apr 21 12:54:38 PM PDT 24 |
Apr 21 12:54:40 PM PDT 24 |
85387536 ps |
| T139 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1443611111 |
|
|
Apr 21 12:54:33 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
505427678 ps |
| T916 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3907653361 |
|
|
Apr 21 12:54:37 PM PDT 24 |
Apr 21 12:55:03 PM PDT 24 |
4578247620 ps |
| T917 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3625044449 |
|
|
Apr 21 12:54:36 PM PDT 24 |
Apr 21 12:54:37 PM PDT 24 |
238445175 ps |
| T137 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3708816699 |
|
|
Apr 21 12:54:50 PM PDT 24 |
Apr 21 12:54:53 PM PDT 24 |
295122189 ps |
| T918 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.465596524 |
|
|
Apr 21 12:54:25 PM PDT 24 |
Apr 21 12:54:27 PM PDT 24 |
28564474 ps |
| T919 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1525817475 |
|
|
Apr 21 12:54:27 PM PDT 24 |
Apr 21 12:54:56 PM PDT 24 |
2579073290 ps |
| T146 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3938562342 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:54:47 PM PDT 24 |
81515957 ps |
| T920 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2684685802 |
|
|
Apr 21 12:54:19 PM PDT 24 |
Apr 21 12:54:24 PM PDT 24 |
104283350 ps |
| T921 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3465476663 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
99131666 ps |
| T922 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2071603025 |
|
|
Apr 21 12:54:30 PM PDT 24 |
Apr 21 12:54:32 PM PDT 24 |
39162414 ps |
| T923 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4128309144 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:55:03 PM PDT 24 |
1670348009 ps |
| T924 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1504468785 |
|
|
Apr 21 12:54:33 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
380169780 ps |
| T925 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3874627401 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:55:04 PM PDT 24 |
819552239 ps |
| T926 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.786565334 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
22489753 ps |
| T927 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2503892567 |
|
|
Apr 21 12:54:40 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
1378576567 ps |
| T131 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3678547922 |
|
|
Apr 21 12:54:19 PM PDT 24 |
Apr 21 12:54:23 PM PDT 24 |
211854040 ps |
| T204 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.916207183 |
|
|
Apr 21 12:54:55 PM PDT 24 |
Apr 21 12:54:56 PM PDT 24 |
77701759 ps |
| T928 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1805357102 |
|
|
Apr 21 12:54:29 PM PDT 24 |
Apr 21 12:54:31 PM PDT 24 |
399870761 ps |
| T929 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1643425113 |
|
|
Apr 21 12:54:27 PM PDT 24 |
Apr 21 12:54:30 PM PDT 24 |
100145468 ps |
| T930 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.210575898 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:47 PM PDT 24 |
56034032 ps |
| T931 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2129841293 |
|
|
Apr 21 12:54:39 PM PDT 24 |
Apr 21 12:54:41 PM PDT 24 |
46646537 ps |
| T932 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2124765393 |
|
|
Apr 21 12:54:47 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
116593254 ps |
| T933 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1621716377 |
|
|
Apr 21 12:54:48 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
66309462 ps |
| T934 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1505862946 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
90295049 ps |
| T935 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.281719464 |
|
|
Apr 21 12:54:32 PM PDT 24 |
Apr 21 12:54:50 PM PDT 24 |
3469726952 ps |
| T936 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.735542308 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
41838416 ps |
| T937 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.998827008 |
|
|
Apr 21 12:54:56 PM PDT 24 |
Apr 21 12:55:02 PM PDT 24 |
24323547 ps |
| T938 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3929208780 |
|
|
Apr 21 12:54:54 PM PDT 24 |
Apr 21 12:54:57 PM PDT 24 |
117544604 ps |
| T939 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.845077857 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
117843794 ps |
| T940 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.591331185 |
|
|
Apr 21 12:54:35 PM PDT 24 |
Apr 21 12:54:36 PM PDT 24 |
39925312 ps |
| T205 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.476943383 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:50 PM PDT 24 |
35463671 ps |
| T941 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4125985421 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:54:45 PM PDT 24 |
98292395 ps |
| T942 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3665160422 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
166348510 ps |
| T943 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.886127208 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
211635405 ps |
| T206 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.205648710 |
|
|
Apr 21 12:54:33 PM PDT 24 |
Apr 21 12:54:34 PM PDT 24 |
38189218 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2923733905 |
|
|
Apr 21 12:54:54 PM PDT 24 |
Apr 21 12:54:56 PM PDT 24 |
38537011 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3976259629 |
|
|
Apr 21 12:54:51 PM PDT 24 |
Apr 21 12:54:53 PM PDT 24 |
62076726 ps |
| T946 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.340567267 |
|
|
Apr 21 12:54:53 PM PDT 24 |
Apr 21 12:55:05 PM PDT 24 |
4418731280 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2923587544 |
|
|
Apr 21 12:54:38 PM PDT 24 |
Apr 21 12:54:41 PM PDT 24 |
23221795 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3620055728 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
45192781 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3537315047 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:38 PM PDT 24 |
142435041 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.734131633 |
|
|
Apr 21 12:54:36 PM PDT 24 |
Apr 21 12:54:37 PM PDT 24 |
58733661 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.20735099 |
|
|
Apr 21 12:54:17 PM PDT 24 |
Apr 21 12:54:19 PM PDT 24 |
33433778 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2801153399 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:52 PM PDT 24 |
73044875 ps |
| T953 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1278894745 |
|
|
Apr 21 12:54:37 PM PDT 24 |
Apr 21 12:54:39 PM PDT 24 |
231929027 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1876522625 |
|
|
Apr 21 12:54:57 PM PDT 24 |
Apr 21 12:55:01 PM PDT 24 |
83260103 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3579786763 |
|
|
Apr 21 12:54:48 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
18069088 ps |
| T956 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3003024969 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:49 PM PDT 24 |
362418772 ps |
| T957 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.195336205 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:51 PM PDT 24 |
102259141 ps |
| T207 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.902930012 |
|
|
Apr 21 12:54:38 PM PDT 24 |
Apr 21 12:54:40 PM PDT 24 |
51215098 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.92596588 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:54:45 PM PDT 24 |
46635485 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.400295527 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:54:57 PM PDT 24 |
1343408747 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.905201631 |
|
|
Apr 21 12:54:39 PM PDT 24 |
Apr 21 12:54:41 PM PDT 24 |
173410739 ps |
| T143 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2226684339 |
|
|
Apr 21 12:54:40 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
148056758 ps |
| T208 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1380262356 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:36 PM PDT 24 |
13651490 ps |
| T209 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.245436593 |
|
|
Apr 21 12:54:22 PM PDT 24 |
Apr 21 12:54:23 PM PDT 24 |
21901840 ps |
| T210 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2221098327 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
40252151 ps |
| T134 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.475535210 |
|
|
Apr 21 12:54:32 PM PDT 24 |
Apr 21 12:54:34 PM PDT 24 |
61159805 ps |
| T132 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1744203052 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
2299066736 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2521707181 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
28421023 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4176037599 |
|
|
Apr 21 12:54:35 PM PDT 24 |
Apr 21 12:54:39 PM PDT 24 |
155354660 ps |
| T211 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.507850323 |
|
|
Apr 21 12:54:20 PM PDT 24 |
Apr 21 12:54:22 PM PDT 24 |
36922247 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.436727673 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:46 PM PDT 24 |
97632275 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2365397485 |
|
|
Apr 21 12:54:57 PM PDT 24 |
Apr 21 12:54:59 PM PDT 24 |
73667893 ps |
| T965 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.208758823 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:44 PM PDT 24 |
115311804 ps |
| T966 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.852865288 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:46 PM PDT 24 |
292832566 ps |
| T967 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.33920178 |
|
|
Apr 21 12:54:51 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
213872732 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1586604510 |
|
|
Apr 21 12:54:44 PM PDT 24 |
Apr 21 12:54:45 PM PDT 24 |
39793136 ps |
| T140 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.649024502 |
|
|
Apr 21 12:54:31 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
503500103 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2334847539 |
|
|
Apr 21 12:54:41 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
34050710 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2259730349 |
|
|
Apr 21 12:54:38 PM PDT 24 |
Apr 21 12:54:52 PM PDT 24 |
5895021995 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1538447375 |
|
|
Apr 21 12:54:54 PM PDT 24 |
Apr 21 12:54:57 PM PDT 24 |
60901233 ps |
| T972 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2010946840 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:53 PM PDT 24 |
98299131 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3144928721 |
|
|
Apr 21 12:54:44 PM PDT 24 |
Apr 21 12:54:47 PM PDT 24 |
317241872 ps |
| T974 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3684206968 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:53 PM PDT 24 |
94087490 ps |
| T975 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1324543337 |
|
|
Apr 21 12:54:34 PM PDT 24 |
Apr 21 12:54:36 PM PDT 24 |
63614684 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.419090235 |
|
|
Apr 21 12:54:51 PM PDT 24 |
Apr 21 12:54:53 PM PDT 24 |
86157869 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.390219149 |
|
|
Apr 21 12:54:35 PM PDT 24 |
Apr 21 12:54:39 PM PDT 24 |
256313166 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1936416874 |
|
|
Apr 21 12:54:28 PM PDT 24 |
Apr 21 12:54:30 PM PDT 24 |
160404283 ps |
| T979 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1421597418 |
|
|
Apr 21 12:54:40 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
114451628 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1185628785 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:50 PM PDT 24 |
262576063 ps |
| T981 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.836319984 |
|
|
Apr 21 12:54:50 PM PDT 24 |
Apr 21 12:54:55 PM PDT 24 |
362636055 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2830199833 |
|
|
Apr 21 12:54:39 PM PDT 24 |
Apr 21 12:54:42 PM PDT 24 |
166786369 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3174448706 |
|
|
Apr 21 12:54:49 PM PDT 24 |
Apr 21 12:54:51 PM PDT 24 |
93024128 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3740608503 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:47 PM PDT 24 |
13870636 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1870555435 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
28115611 ps |
| T135 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.10288737 |
|
|
Apr 21 12:54:45 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
139536005 ps |
| T213 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1046714417 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:43 PM PDT 24 |
54127175 ps |
| T147 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3066833422 |
|
|
Apr 21 12:54:44 PM PDT 24 |
Apr 21 12:54:47 PM PDT 24 |
213542884 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3925970242 |
|
|
Apr 21 12:54:31 PM PDT 24 |
Apr 21 12:54:32 PM PDT 24 |
17256724 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1327231540 |
|
|
Apr 21 12:54:44 PM PDT 24 |
Apr 21 12:54:46 PM PDT 24 |
89577343 ps |
| T988 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1974431933 |
|
|
Apr 21 12:54:42 PM PDT 24 |
Apr 21 12:54:50 PM PDT 24 |
289133054 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3618375696 |
|
|
Apr 21 12:54:35 PM PDT 24 |
Apr 21 12:54:36 PM PDT 24 |
26880025 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1104749614 |
|
|
Apr 21 12:54:39 PM PDT 24 |
Apr 21 12:54:40 PM PDT 24 |
40451732 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2615734394 |
|
|
Apr 21 12:54:43 PM PDT 24 |
Apr 21 12:54:45 PM PDT 24 |
54537578 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3346261651 |
|
|
Apr 21 12:54:37 PM PDT 24 |
Apr 21 12:54:38 PM PDT 24 |
14624399 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2212181434 |
|
|
Apr 21 12:54:39 PM PDT 24 |
Apr 21 12:54:42 PM PDT 24 |
514445701 ps |
| T148 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3121680351 |
|
|
Apr 21 12:54:32 PM PDT 24 |
Apr 21 12:54:35 PM PDT 24 |
195349716 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1303134748 |
|
|
Apr 21 12:54:46 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
20266910 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3013674170 |
|
|
Apr 21 12:54:25 PM PDT 24 |
Apr 21 12:54:27 PM PDT 24 |
168541745 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1939762097 |
|
|
Apr 21 12:54:47 PM PDT 24 |
Apr 21 12:54:48 PM PDT 24 |
29568550 ps |
| T997 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.865822733 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
443390339 ps |
| T141 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3534028358 |
|
|
Apr 21 12:54:33 PM PDT 24 |
Apr 21 12:54:39 PM PDT 24 |
137573151 ps |
| T998 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2096683078 |
|
|
Apr 21 12:54:48 PM PDT 24 |
Apr 21 12:54:50 PM PDT 24 |
33169588 ps |
| T999 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3792615038 |
|
|
Apr 21 12:54:56 PM PDT 24 |
Apr 21 12:54:57 PM PDT 24 |
100703419 ps |
| T142 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3941595049 |
|
|
Apr 21 12:54:50 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
253443542 ps |
| T212 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1724910069 |
|
|
Apr 21 12:54:52 PM PDT 24 |
Apr 21 12:54:54 PM PDT 24 |
97576248 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2733193672 |
|
|
Apr 21 12:54:23 PM PDT 24 |
Apr 21 12:54:25 PM PDT 24 |
25062823 ps |