Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51455 |
1 |
|
|
T1 |
135 |
|
T2 |
94 |
|
T3 |
75 |
auto[1] |
1812 |
1 |
|
|
T1 |
8 |
|
T3 |
8 |
|
T14 |
24 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52560 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
auto[1] |
707 |
1 |
|
|
T34 |
15 |
|
T35 |
20 |
|
T51 |
17 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51505 |
1 |
|
|
T1 |
140 |
|
T2 |
82 |
|
T3 |
83 |
auto[1] |
1762 |
1 |
|
|
T1 |
3 |
|
T2 |
12 |
|
T11 |
3 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51434 |
1 |
|
|
T1 |
141 |
|
T2 |
79 |
|
T3 |
81 |
auto[1] |
1833 |
1 |
|
|
T1 |
2 |
|
T2 |
15 |
|
T3 |
2 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51368 |
1 |
|
|
T1 |
140 |
|
T2 |
86 |
|
T3 |
82 |
auto[1] |
1899 |
1 |
|
|
T1 |
3 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48526 |
1 |
|
|
T1 |
97 |
|
T2 |
94 |
|
T3 |
69 |
no_err_inj |
4741 |
1 |
|
|
T1 |
46 |
|
T3 |
14 |
|
T9 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51434 |
1 |
|
|
T1 |
131 |
|
T2 |
94 |
|
T3 |
77 |
auto[1] |
1833 |
1 |
|
|
T1 |
12 |
|
T3 |
6 |
|
T14 |
15 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52527 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
auto[1] |
740 |
1 |
|
|
T34 |
18 |
|
T35 |
23 |
|
T51 |
19 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37486 |
1 |
|
|
T1 |
105 |
|
T2 |
94 |
|
T3 |
74 |
auto[1] |
15781 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51411 |
1 |
|
|
T1 |
141 |
|
T2 |
86 |
|
T3 |
83 |
auto[1] |
1856 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T11 |
6 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51364 |
1 |
|
|
T1 |
142 |
|
T2 |
84 |
|
T3 |
83 |
auto[1] |
1903 |
1 |
|
|
T1 |
1 |
|
T2 |
10 |
|
T11 |
5 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51451 |
1 |
|
|
T1 |
143 |
|
T2 |
83 |
|
T3 |
80 |
auto[1] |
1816 |
1 |
|
|
T2 |
11 |
|
T3 |
3 |
|
T11 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51418 |
1 |
|
|
T1 |
137 |
|
T2 |
94 |
|
T3 |
75 |
auto[1] |
1849 |
1 |
|
|
T1 |
6 |
|
T3 |
8 |
|
T14 |
22 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51010 |
1 |
|
|
T1 |
132 |
|
T2 |
94 |
|
T3 |
74 |
auto[1] |
2257 |
1 |
|
|
T1 |
11 |
|
T3 |
9 |
|
T10 |
9 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52549 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
auto[1] |
718 |
1 |
|
|
T34 |
19 |
|
T35 |
13 |
|
T51 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52544 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
auto[1] |
723 |
1 |
|
|
T34 |
7 |
|
T35 |
21 |
|
T51 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52538 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
auto[1] |
729 |
1 |
|
|
T34 |
13 |
|
T35 |
22 |
|
T51 |
16 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50492 |
1 |
|
|
T1 |
104 |
|
T2 |
94 |
|
T3 |
73 |
auto[1] |
2775 |
1 |
|
|
T1 |
39 |
|
T3 |
10 |
|
T22 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49468 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
auto[1] |
3799 |
1 |
|
|
T17 |
90 |
|
T42 |
93 |
|
T40 |
54 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51394 |
1 |
|
|
T1 |
143 |
|
T2 |
79 |
|
T3 |
83 |
auto[1] |
1873 |
1 |
|
|
T2 |
15 |
|
T11 |
10 |
|
T14 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51417 |
1 |
|
|
T1 |
141 |
|
T2 |
87 |
|
T3 |
83 |
auto[1] |
1850 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T11 |
5 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51444 |
1 |
|
|
T1 |
143 |
|
T2 |
86 |
|
T3 |
83 |
auto[1] |
1823 |
1 |
|
|
T2 |
8 |
|
T11 |
8 |
|
T14 |
10 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51403 |
1 |
|
|
T1 |
130 |
|
T2 |
94 |
|
T3 |
80 |
auto[1] |
1864 |
1 |
|
|
T1 |
13 |
|
T3 |
3 |
|
T14 |
19 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47735 |
1 |
|
|
T1 |
137 |
|
T2 |
94 |
|
T3 |
72 |
auto[1] |
5532 |
1 |
|
|
T1 |
6 |
|
T3 |
11 |
|
T14 |
23 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49303 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
auto[1] |
3964 |
1 |
|
|
T15 |
97 |
|
T49 |
97 |
|
T50 |
81 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53267 |
1 |
|
|
T1 |
143 |
|
T2 |
94 |
|
T3 |
83 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51461 |
1 |
|
|
T1 |
132 |
|
T2 |
94 |
|
T3 |
78 |
auto[1] |
1806 |
1 |
|
|
T1 |
11 |
|
T3 |
5 |
|
T14 |
20 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51417 |
1 |
|
|
T1 |
133 |
|
T2 |
94 |
|
T3 |
78 |
auto[1] |
1850 |
1 |
|
|
T1 |
10 |
|
T3 |
5 |
|
T14 |
14 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51539 |
1 |
|
|
T1 |
136 |
|
T2 |
94 |
|
T3 |
75 |
auto[1] |
1728 |
1 |
|
|
T1 |
7 |
|
T3 |
8 |
|
T14 |
19 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47119 |
1 |
|
|
T1 |
84 |
|
T2 |
94 |
|
T3 |
63 |
auto[0] |
no_err_inj |
3373 |
1 |
|
|
T1 |
20 |
|
T3 |
10 |
|
T9 |
5 |
auto[1] |
err_inj |
1407 |
1 |
|
|
T1 |
13 |
|
T3 |
6 |
|
T22 |
8 |
auto[1] |
no_err_inj |
1368 |
1 |
|
|
T1 |
26 |
|
T3 |
4 |
|
T22 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48800 |
1 |
|
|
T1 |
104 |
|
T2 |
87 |
|
T3 |
73 |
auto[0] |
auto[1] |
1692 |
1 |
|
|
T2 |
7 |
|
T11 |
5 |
|
T14 |
8 |
auto[1] |
auto[0] |
2617 |
1 |
|
|
T1 |
37 |
|
T3 |
10 |
|
T22 |
14 |
auto[1] |
auto[1] |
158 |
1 |
|
|
T1 |
2 |
|
T22 |
1 |
|
T60 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48732 |
1 |
|
|
T1 |
104 |
|
T2 |
84 |
|
T3 |
73 |
auto[0] |
auto[1] |
1760 |
1 |
|
|
T2 |
10 |
|
T11 |
5 |
|
T14 |
5 |
auto[1] |
auto[0] |
2632 |
1 |
|
|
T1 |
38 |
|
T3 |
10 |
|
T22 |
14 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T1 |
1 |
|
T22 |
1 |
|
T60 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48811 |
1 |
|
|
T1 |
104 |
|
T2 |
86 |
|
T3 |
73 |
auto[0] |
auto[1] |
1681 |
1 |
|
|
T2 |
8 |
|
T11 |
8 |
|
T14 |
10 |
auto[1] |
auto[0] |
2633 |
1 |
|
|
T1 |
39 |
|
T3 |
10 |
|
T22 |
14 |
auto[1] |
auto[1] |
142 |
1 |
|
|
T22 |
1 |
|
T60 |
3 |
|
T208 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48807 |
1 |
|
|
T1 |
104 |
|
T2 |
79 |
|
T3 |
73 |
auto[0] |
auto[1] |
1685 |
1 |
|
|
T2 |
15 |
|
T11 |
5 |
|
T14 |
8 |
auto[1] |
auto[0] |
2627 |
1 |
|
|
T1 |
37 |
|
T3 |
8 |
|
T22 |
12 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T22 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48764 |
1 |
|
|
T1 |
104 |
|
T2 |
86 |
|
T3 |
73 |
auto[0] |
auto[1] |
1728 |
1 |
|
|
T2 |
8 |
|
T11 |
12 |
|
T14 |
7 |
auto[1] |
auto[0] |
2604 |
1 |
|
|
T1 |
36 |
|
T3 |
9 |
|
T22 |
14 |
auto[1] |
auto[1] |
171 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T22 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48899 |
1 |
|
|
T1 |
104 |
|
T2 |
82 |
|
T3 |
73 |
auto[0] |
auto[1] |
1593 |
1 |
|
|
T2 |
12 |
|
T11 |
3 |
|
T14 |
11 |
auto[1] |
auto[0] |
2606 |
1 |
|
|
T1 |
36 |
|
T3 |
10 |
|
T22 |
15 |
auto[1] |
auto[1] |
169 |
1 |
|
|
T1 |
3 |
|
T60 |
1 |
|
T87 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36362 |
1 |
|
|
T1 |
97 |
|
T2 |
94 |
|
T3 |
66 |
auto[0] |
auto[1] |
1124 |
1 |
|
|
T1 |
8 |
|
T3 |
8 |
|
T30 |
10 |
auto[1] |
auto[0] |
15093 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
688 |
1 |
|
|
T14 |
24 |
|
T32 |
12 |
|
T73 |
23 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36366 |
1 |
|
|
T1 |
93 |
|
T2 |
94 |
|
T3 |
68 |
auto[0] |
auto[1] |
1120 |
1 |
|
|
T1 |
12 |
|
T3 |
6 |
|
T30 |
11 |
auto[1] |
auto[0] |
15068 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
713 |
1 |
|
|
T14 |
15 |
|
T32 |
7 |
|
T73 |
17 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36103 |
1 |
|
|
T1 |
105 |
|
T2 |
94 |
|
T3 |
74 |
auto[0] |
auto[1] |
1383 |
1 |
|
|
T10 |
9 |
|
T22 |
19 |
|
T60 |
5 |
auto[1] |
auto[0] |
14907 |
1 |
|
|
T1 |
27 |
|
T12 |
5 |
|
T13 |
8 |
auto[1] |
auto[1] |
874 |
1 |
|
|
T1 |
11 |
|
T3 |
9 |
|
T20 |
2 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36395 |
1 |
|
|
T1 |
99 |
|
T2 |
94 |
|
T3 |
66 |
auto[0] |
auto[1] |
1091 |
1 |
|
|
T1 |
6 |
|
T3 |
8 |
|
T30 |
6 |
auto[1] |
auto[0] |
15023 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
758 |
1 |
|
|
T14 |
22 |
|
T32 |
8 |
|
T73 |
22 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32699 |
1 |
|
|
T1 |
99 |
|
T2 |
94 |
|
T3 |
63 |
auto[0] |
auto[1] |
4787 |
1 |
|
|
T1 |
6 |
|
T3 |
11 |
|
T30 |
6 |
auto[1] |
auto[0] |
15036 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
745 |
1 |
|
|
T14 |
23 |
|
T32 |
9 |
|
T73 |
14 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36457 |
1 |
|
|
T1 |
104 |
|
T2 |
87 |
|
T3 |
74 |
auto[0] |
auto[1] |
1029 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T11 |
5 |
auto[1] |
auto[0] |
14960 |
1 |
|
|
T1 |
37 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
821 |
1 |
|
|
T1 |
1 |
|
T14 |
8 |
|
T60 |
2 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36447 |
1 |
|
|
T1 |
105 |
|
T2 |
79 |
|
T3 |
74 |
auto[0] |
auto[1] |
1039 |
1 |
|
|
T2 |
15 |
|
T11 |
10 |
|
T72 |
12 |
auto[1] |
auto[0] |
14947 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
834 |
1 |
|
|
T14 |
9 |
|
T60 |
4 |
|
T209 |
14 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36340 |
1 |
|
|
T1 |
104 |
|
T2 |
84 |
|
T3 |
74 |
auto[0] |
auto[1] |
1146 |
1 |
|
|
T1 |
1 |
|
T2 |
10 |
|
T11 |
5 |
auto[1] |
auto[0] |
15024 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
757 |
1 |
|
|
T14 |
5 |
|
T60 |
2 |
|
T209 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36389 |
1 |
|
|
T1 |
105 |
|
T2 |
86 |
|
T3 |
74 |
auto[0] |
auto[1] |
1097 |
1 |
|
|
T2 |
8 |
|
T11 |
6 |
|
T72 |
9 |
auto[1] |
auto[0] |
15022 |
1 |
|
|
T1 |
36 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
759 |
1 |
|
|
T1 |
2 |
|
T14 |
17 |
|
T60 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36455 |
1 |
|
|
T1 |
103 |
|
T2 |
79 |
|
T3 |
72 |
auto[0] |
auto[1] |
1031 |
1 |
|
|
T1 |
2 |
|
T2 |
15 |
|
T3 |
2 |
auto[1] |
auto[0] |
14979 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
802 |
1 |
|
|
T14 |
8 |
|
T60 |
1 |
|
T209 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36480 |
1 |
|
|
T1 |
104 |
|
T2 |
82 |
|
T3 |
74 |
auto[0] |
auto[1] |
1006 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T11 |
3 |
auto[1] |
auto[0] |
15025 |
1 |
|
|
T1 |
36 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
756 |
1 |
|
|
T1 |
2 |
|
T14 |
11 |
|
T209 |
9 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36393 |
1 |
|
|
T1 |
98 |
|
T2 |
94 |
|
T3 |
66 |
auto[0] |
auto[1] |
1093 |
1 |
|
|
T1 |
7 |
|
T3 |
8 |
|
T30 |
7 |
auto[1] |
auto[0] |
15146 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
635 |
1 |
|
|
T14 |
19 |
|
T32 |
8 |
|
T73 |
19 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36381 |
1 |
|
|
T1 |
95 |
|
T2 |
94 |
|
T3 |
69 |
auto[0] |
auto[1] |
1105 |
1 |
|
|
T1 |
10 |
|
T3 |
5 |
|
T30 |
9 |
auto[1] |
auto[0] |
15036 |
1 |
|
|
T1 |
38 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
745 |
1 |
|
|
T14 |
14 |
|
T32 |
10 |
|
T73 |
23 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35905 |
1 |
|
|
T1 |
80 |
|
T2 |
94 |
|
T3 |
64 |
auto[0] |
auto[1] |
1581 |
1 |
|
|
T1 |
25 |
|
T3 |
10 |
|
T22 |
15 |
auto[1] |
auto[0] |
14587 |
1 |
|
|
T1 |
24 |
|
T3 |
9 |
|
T12 |
5 |
auto[1] |
auto[1] |
1194 |
1 |
|
|
T1 |
14 |
|
T60 |
28 |
|
T87 |
13 |