Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104279186

1

T1

107752

T2

21329

T3

120097

auto[1]

1400089

1

T1

1577

T2

4257

T3

690

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104280553

1

T1

107753

T2

22418

T3

119506

auto[1]

1398722

1

T1

1575

T2

3168

T3

1281

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7191486	1			T1	23259		T2	8966		T3	7946
auto[IdleSt]	20385086	1			T1	47592		T2	1480		T3	42183
auto[ClkMuxSt]	35576	1			T1	131		T3	76		T8	1
auto[CntIncrSt]	35246	1			T1	128		T3	76		T8	1
auto[CntProgSt]	1776725	1			T1	228		T3	136		T8	2
auto[TransCheckSt]	27449	1			T1	99		T3	56		T8	1
auto[TokenHashSt]	44045478	1			T1	944989		T3	33451		T8	202
auto[FlashRmaSt]	28022	1			T1	127		T3	44		T9	5
auto[TokenCheck0St]	12681	1			T1	55		T3	29		T9	5
auto[TokenCheck1St]	9340	1			T1	44		T3	23		T9	5
auto[TransProgSt]	456809	1			T1	86		T3	45		T9	99
auto[PostTransSt]	12460366	1			T1	40627		T3	24710		T8	772
auto[ScrapSt]	332405	1			T1	1394		T3	143		T13	417
auto[EscalateSt]	6871402	1			T1	13375		T2	9475		T3	11344
auto[InvalidSt]	12009241	1			T1	6971		T2	5655		T3	525

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1963	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12009241	1			T1	6971		T2	5655		T3	525
EscalateSt	6871402	1			T1	13375		T2	9475		T3	11344
ScrapSt	332405	1			T1	1394		T3	143		T13	417
PostTransSt	12460366	1			T1	40627		T3	24710		T8	772
TransProgSt	456809	1			T1	86		T3	45		T9	99
TokenCheck1St	9340	1			T1	44		T3	23		T9	5
TokenCheck0St	12681	1			T1	55		T3	29		T9	5
FlashRmaSt	28022	1			T1	127		T3	44		T9	5
TokenHashSt	44045478	1			T1	944989		T3	33451		T8	202
TransCheckSt	27449	1			T1	99		T3	56		T8	1
CntProgSt	1776725	1			T1	228		T3	136		T8	2
CntIncrSt	35246	1			T1	128		T3	76		T8	1
ClkMuxSt	35576	1			T1	131		T3	76		T8	1
IdleSt	20385086	1			T1	47592		T2	1480		T3	42183
ResetSt	7191486	1			T1	23259		T2	8966		T3	7946
arcs[ResetSt=>IdleSt]	53444	1			T1	149		T2	84		T3	84
arcs[IdleSt=>ScrapSt]	286	1			T1	2		T3	1		T13	1
arcs[IdleSt=>ClkMuxSt]	35312	1			T1	128		T3	76		T8	1
arcs[ClkMuxSt=>CntIncrSt]	35246	1			T1	128		T3	76		T8	1
arcs[CntIncrSt=>PostTransSt]	1852	1			T1	10		T3	5		T14	14
arcs[CntIncrSt=>CntProgSt]	33325	1			T1	118		T3	71		T8	1
arcs[CntProgSt=>PostTransSt]	4746	1			T1	19		T3	15		T10	9
arcs[CntProgSt=>TransCheckSt]	27449	1			T1	99		T3	56		T8	1
arcs[TransCheckSt=>PostTransSt]	3723	1			T1	7		T3	8		T14	19
arcs[TransCheckSt=>TokenHashSt]	23614	1			T1	92		T3	48		T8	1
arcs[TokenHashSt=>PostTransSt]	10209	1			T1	37		T3	19		T8	1
arcs[TokenHashSt=>FlashRmaSt]	12764	1			T1	55		T3	29		T9	5
arcs[FlashRmaSt=>TokenCheck0St]	12681	1			T1	55		T3	29		T9	5
arcs[TokenCheck0St=>PostTransSt]	3319	1			T1	11		T3	6		T14	15
arcs[TokenCheck0St=>TokenCheck1St]	9340	1			T1	44		T3	23		T9	5
arcs[TokenCheck1St=>PostTransSt]	669	1			T1	1		T15	6		T32	2
arcs[TransProgSt=>PostTransSt]	7748	1			T1	43		T3	23		T9	5
arcs[IdleSt=>EscalateSt]	220	1			T17	6		T42	8		T41	1
arcs[ClkMuxSt=>EscalateSt]	66	1			T17	1		T40	1		T41	1
arcs[CntIncrSt=>EscalateSt]	69	1			T17	2		T42	3		T40	3
arcs[CntProgSt=>EscalateSt]	1130	1			T17	27		T42	13		T40	4
arcs[TransCheckSt=>EscalateSt]	112	1			T42	8		T40	8		T41	5
arcs[TokenHashSt=>EscalateSt]	641	1			T14	2		T17	15		T42	23
arcs[FlashRmaSt=>EscalateSt]	83	1			T17	1		T42	7		T40	4
arcs[TokenCheck0St=>EscalateSt]	22	1			T17	1		T42	1		T46	3
arcs[TokenCheck1St=>EscalateSt]	154	1			T17	5		T42	5		T40	1
arcs[TransProgSt=>EscalateSt]	769	1			T17	21		T42	8		T40	4
arcs[PostTransSt=>EscalateSt]	4988	1			T1	19		T3	17		T10	9
arcs[InvalidSt=>EscalateSt]	13709	1			T1	13		T2	75		T3	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7191315	1			T1	23259		T2	8966		T3	7946
auto[0]	auto[IdleSt]	20384947	1			T1	47592		T2	1480		T3	42183
auto[0]	auto[ClkMuxSt]	35531	1			T1	131		T3	76		T8	1
auto[0]	auto[CntIncrSt]	35198	1			T1	128		T3	76		T8	1
auto[0]	auto[CntProgSt]	1775974	1			T1	228		T3	136		T8	2
auto[0]	auto[TransCheckSt]	27375	1			T1	99		T3	56		T8	1
auto[0]	auto[TokenHashSt]	44045045	1			T1	944989		T3	33451		T8	202
auto[0]	auto[FlashRmaSt]	27967	1			T1	127		T3	44		T9	5
auto[0]	auto[TokenCheck0St]	12662	1			T1	55		T3	29		T9	5
auto[0]	auto[TokenCheck1St]	9234	1			T1	44		T3	23		T9	5
auto[0]	auto[TransProgSt]	456315	1			T1	86		T3	45		T9	99
auto[0]	auto[PostTransSt]	12457787	1			T1	40620		T3	24705		T8	772
auto[0]	auto[ScrapSt]	332361	1			T1	1394		T3	143		T13	417
auto[0]	auto[EscalateSt]	5483143	1			T1	11814		T2	5261		T3	10661
auto[0]	auto[InvalidSt]	12002369	1			T1	6962		T2	5612		T3	523
auto[1]	auto[ResetSt]	171	1			T17	4		T42	3		T40	2
auto[1]	auto[IdleSt]	139	1			T17	4		T42	4		T41	1
auto[1]	auto[ClkMuxSt]	45	1			T17	1		T40	1		T46	2
auto[1]	auto[CntIncrSt]	48	1			T17	1		T42	3		T40	1
auto[1]	auto[CntProgSt]	751	1			T17	20		T42	11		T40	4
auto[1]	auto[TransCheckSt]	74	1			T42	7		T40	3		T41	3
auto[1]	auto[TokenHashSt]	433	1			T14	1		T17	10		T42	16
auto[1]	auto[FlashRmaSt]	55	1			T17	1		T42	4		T40	2
auto[1]	auto[TokenCheck0St]	19	1			T17	1		T42	1		T46	3
auto[1]	auto[TokenCheck1St]	106	1			T17	5		T42	3		T41	1
auto[1]	auto[TransProgSt]	494	1			T17	10		T42	5		T40	3
auto[1]	auto[PostTransSt]	2579	1			T1	7		T3	5		T10	9
auto[1]	auto[ScrapSt]	44	1			T17	2		T42	2		T71	1
auto[1]	auto[EscalateSt]	1388259	1			T1	1561		T2	4214		T3	683
auto[1]	auto[InvalidSt]	6872	1			T1	9		T2	43		T3	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7191309	1			T1	23259		T2	8966		T3	7946
auto[0]	auto[IdleSt]	20384934	1			T1	47592		T2	1480		T3	42183
auto[0]	auto[ClkMuxSt]	35534	1			T1	131		T3	76		T8	1
auto[0]	auto[CntIncrSt]	35196	1			T1	128		T3	76		T8	1
auto[0]	auto[CntProgSt]	1775956	1			T1	228		T3	136		T8	2
auto[0]	auto[TransCheckSt]	27365	1			T1	99		T3	56		T8	1
auto[0]	auto[TokenHashSt]	44045053	1			T1	944989		T3	33451		T8	202
auto[0]	auto[FlashRmaSt]	27969	1			T1	127		T3	44		T9	5
auto[0]	auto[TokenCheck0St]	12664	1			T1	55		T3	29		T9	5
auto[0]	auto[TokenCheck1St]	9238	1			T1	44		T3	23		T9	5
auto[0]	auto[TransProgSt]	456277	1			T1	86		T3	45		T9	99
auto[0]	auto[PostTransSt]	12457881	1			T1	40615		T3	24698		T8	772
auto[0]	auto[ScrapSt]	332358	1			T1	1394		T3	143		T13	417
auto[0]	auto[EscalateSt]	5484452	1			T1	11816		T2	6339		T3	10076
auto[0]	auto[InvalidSt]	12002404	1			T1	6967		T2	5623		T3	524
auto[1]	auto[ResetSt]	177	1			T17	5		T42	4		T40	1
auto[1]	auto[IdleSt]	152	1			T17	3		T42	6		T41	1
auto[1]	auto[ClkMuxSt]	42	1			T41	1		T46	1		T207	2
auto[1]	auto[CntIncrSt]	50	1			T17	2		T42	2		T40	3
auto[1]	auto[CntProgSt]	769	1			T17	16		T42	8		T40	1
auto[1]	auto[TransCheckSt]	84	1			T42	4		T40	7		T41	3
auto[1]	auto[TokenHashSt]	425	1			T14	1		T17	10		T42	14
auto[1]	auto[FlashRmaSt]	53	1			T42	6		T40	3		T41	1
auto[1]	auto[TokenCheck0St]	17	1			T17	1		T42	1		T46	2
auto[1]	auto[TokenCheck1St]	102	1			T17	2		T42	4		T40	1
auto[1]	auto[TransProgSt]	532	1			T17	15		T42	4		T40	3
auto[1]	auto[PostTransSt]	2485	1			T1	12		T3	12		T14	13
auto[1]	auto[ScrapSt]	47	1			T17	1		T42	1		T40	1
auto[1]	auto[EscalateSt]	1386950	1			T1	1559		T2	3136		T3	1268
auto[1]	auto[InvalidSt]	6837	1			T1	4		T2	32		T3	1