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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.13 97.82 95.38 93.31 100.00 98.52 98.76 96.11


Total test records in report: 999
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T167 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.946132684 Apr 23 02:47:56 PM PDT 24 Apr 23 02:56:53 PM PDT 24 15665846145 ps
T814 /workspace/coverage/default/49.lc_ctrl_prog_failure.407779314 Apr 23 02:49:56 PM PDT 24 Apr 23 02:49:58 PM PDT 24 67712268 ps
T815 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2221740842 Apr 23 02:49:22 PM PDT 24 Apr 23 02:49:31 PM PDT 24 244597025 ps
T816 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2693151705 Apr 23 02:47:38 PM PDT 24 Apr 23 02:47:39 PM PDT 24 11332104 ps
T817 /workspace/coverage/default/31.lc_ctrl_prog_failure.3900133750 Apr 23 02:49:05 PM PDT 24 Apr 23 02:49:09 PM PDT 24 413834797 ps
T818 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1164603731 Apr 23 02:47:57 PM PDT 24 Apr 23 02:48:11 PM PDT 24 337296782 ps
T819 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1108257715 Apr 23 02:48:14 PM PDT 24 Apr 23 02:48:25 PM PDT 24 538869468 ps
T820 /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.450507662 Apr 23 02:47:22 PM PDT 24 Apr 23 02:48:04 PM PDT 24 2689713278 ps
T821 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1978798283 Apr 23 02:49:00 PM PDT 24 Apr 23 02:49:01 PM PDT 24 32129230 ps
T822 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1721096007 Apr 23 02:47:03 PM PDT 24 Apr 23 02:47:13 PM PDT 24 371272769 ps
T823 /workspace/coverage/default/45.lc_ctrl_prog_failure.1157993215 Apr 23 02:49:45 PM PDT 24 Apr 23 02:49:49 PM PDT 24 282070678 ps
T824 /workspace/coverage/default/38.lc_ctrl_security_escalation.2514570564 Apr 23 02:49:26 PM PDT 24 Apr 23 02:49:33 PM PDT 24 239192377 ps
T825 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2590540723 Apr 23 02:47:28 PM PDT 24 Apr 23 02:47:40 PM PDT 24 1770368183 ps
T826 /workspace/coverage/default/42.lc_ctrl_errors.4234590720 Apr 23 02:49:38 PM PDT 24 Apr 23 02:49:49 PM PDT 24 291963840 ps
T827 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1972494082 Apr 23 02:47:05 PM PDT 24 Apr 23 02:47:17 PM PDT 24 607780951 ps
T828 /workspace/coverage/default/32.lc_ctrl_security_escalation.2389897512 Apr 23 02:49:08 PM PDT 24 Apr 23 02:49:20 PM PDT 24 6055833002 ps
T829 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1760652526 Apr 23 02:46:53 PM PDT 24 Apr 23 02:47:05 PM PDT 24 1182036614 ps
T830 /workspace/coverage/default/14.lc_ctrl_state_post_trans.2401078591 Apr 23 02:47:55 PM PDT 24 Apr 23 02:48:01 PM PDT 24 229759201 ps
T831 /workspace/coverage/default/20.lc_ctrl_alert_test.1347583698 Apr 23 02:48:28 PM PDT 24 Apr 23 02:48:29 PM PDT 24 27327810 ps
T832 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3628998941 Apr 23 02:46:56 PM PDT 24 Apr 23 02:47:04 PM PDT 24 590484751 ps
T833 /workspace/coverage/default/18.lc_ctrl_sec_mubi.1204857052 Apr 23 02:48:20 PM PDT 24 Apr 23 02:48:32 PM PDT 24 757869741 ps
T834 /workspace/coverage/default/14.lc_ctrl_smoke.1645098018 Apr 23 02:47:56 PM PDT 24 Apr 23 02:47:58 PM PDT 24 17943384 ps
T835 /workspace/coverage/default/44.lc_ctrl_sec_mubi.3724320751 Apr 23 02:49:44 PM PDT 24 Apr 23 02:49:59 PM PDT 24 1324761342 ps
T836 /workspace/coverage/default/20.lc_ctrl_state_post_trans.292564473 Apr 23 02:48:25 PM PDT 24 Apr 23 02:48:36 PM PDT 24 213425202 ps
T837 /workspace/coverage/default/32.lc_ctrl_jtag_access.4252658120 Apr 23 02:49:07 PM PDT 24 Apr 23 02:49:15 PM PDT 24 1585958640 ps
T838 /workspace/coverage/default/21.lc_ctrl_errors.265124238 Apr 23 02:48:26 PM PDT 24 Apr 23 02:48:41 PM PDT 24 321205840 ps
T839 /workspace/coverage/default/32.lc_ctrl_state_post_trans.1827656952 Apr 23 02:49:09 PM PDT 24 Apr 23 02:49:18 PM PDT 24 363031862 ps
T840 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1142581025 Apr 23 02:46:44 PM PDT 24 Apr 23 02:46:51 PM PDT 24 220128281 ps
T841 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.4261986843 Apr 23 02:49:36 PM PDT 24 Apr 23 02:49:48 PM PDT 24 1626614110 ps
T842 /workspace/coverage/default/27.lc_ctrl_smoke.2861864133 Apr 23 02:48:53 PM PDT 24 Apr 23 02:48:57 PM PDT 24 352140297 ps
T843 /workspace/coverage/default/1.lc_ctrl_state_failure.2160115355 Apr 23 02:46:51 PM PDT 24 Apr 23 02:47:20 PM PDT 24 912588244 ps
T844 /workspace/coverage/default/2.lc_ctrl_jtag_errors.2931812734 Apr 23 02:46:58 PM PDT 24 Apr 23 02:47:23 PM PDT 24 1413231799 ps
T845 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.676647000 Apr 23 02:49:57 PM PDT 24 Apr 23 02:50:08 PM PDT 24 555436834 ps
T846 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2066402070 Apr 23 02:48:16 PM PDT 24 Apr 23 02:48:19 PM PDT 24 426800258 ps
T847 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.401401679 Apr 23 02:48:57 PM PDT 24 Apr 23 02:49:11 PM PDT 24 2634296514 ps
T848 /workspace/coverage/default/1.lc_ctrl_sec_mubi.1163475313 Apr 23 02:46:54 PM PDT 24 Apr 23 02:47:06 PM PDT 24 372003085 ps
T849 /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2640183651 Apr 23 02:48:08 PM PDT 24 Apr 23 02:49:07 PM PDT 24 1227195247 ps
T850 /workspace/coverage/default/31.lc_ctrl_state_failure.2889583529 Apr 23 02:49:00 PM PDT 24 Apr 23 02:49:28 PM PDT 24 218534600 ps
T851 /workspace/coverage/default/39.lc_ctrl_alert_test.163707846 Apr 23 02:49:30 PM PDT 24 Apr 23 02:49:31 PM PDT 24 16941609 ps
T852 /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1219461896 Apr 23 02:49:12 PM PDT 24 Apr 23 02:49:24 PM PDT 24 1840959734 ps
T853 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2698298735 Apr 23 02:47:16 PM PDT 24 Apr 23 02:47:53 PM PDT 24 5047208783 ps
T854 /workspace/coverage/default/36.lc_ctrl_smoke.251075316 Apr 23 02:49:18 PM PDT 24 Apr 23 02:49:20 PM PDT 24 109859637 ps
T855 /workspace/coverage/default/38.lc_ctrl_sec_mubi.2977313316 Apr 23 02:49:26 PM PDT 24 Apr 23 02:49:38 PM PDT 24 228138503 ps
T856 /workspace/coverage/default/8.lc_ctrl_prog_failure.3914503695 Apr 23 02:47:30 PM PDT 24 Apr 23 02:47:33 PM PDT 24 277309898 ps
T857 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1083516458 Apr 23 02:49:38 PM PDT 24 Apr 23 02:49:51 PM PDT 24 373950552 ps
T858 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3425084823 Apr 23 02:47:31 PM PDT 24 Apr 23 02:48:17 PM PDT 24 916722206 ps
T859 /workspace/coverage/default/30.lc_ctrl_security_escalation.448068398 Apr 23 02:49:00 PM PDT 24 Apr 23 02:49:11 PM PDT 24 556203652 ps
T860 /workspace/coverage/default/24.lc_ctrl_sec_mubi.788294454 Apr 23 02:48:36 PM PDT 24 Apr 23 02:48:52 PM PDT 24 521799049 ps
T861 /workspace/coverage/default/45.lc_ctrl_smoke.1606799839 Apr 23 02:49:43 PM PDT 24 Apr 23 02:49:47 PM PDT 24 113805195 ps
T44 /workspace/coverage/default/3.lc_ctrl_sec_cm.2077458480 Apr 23 02:47:04 PM PDT 24 Apr 23 02:47:38 PM PDT 24 794650549 ps
T862 /workspace/coverage/default/19.lc_ctrl_jtag_errors.3042837782 Apr 23 02:48:23 PM PDT 24 Apr 23 02:49:11 PM PDT 24 1607900707 ps
T45 /workspace/coverage/default/1.lc_ctrl_sec_cm.4055529434 Apr 23 02:46:57 PM PDT 24 Apr 23 02:47:22 PM PDT 24 180939759 ps
T863 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.543394132 Apr 23 02:48:25 PM PDT 24 Apr 23 02:48:34 PM PDT 24 2354331810 ps
T864 /workspace/coverage/default/8.lc_ctrl_stress_all.1621196657 Apr 23 02:47:34 PM PDT 24 Apr 23 02:50:25 PM PDT 24 7453222665 ps
T865 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2171449767 Apr 23 02:49:03 PM PDT 24 Apr 23 02:49:11 PM PDT 24 228313936 ps
T866 /workspace/coverage/default/28.lc_ctrl_stress_all.3814125399 Apr 23 02:48:57 PM PDT 24 Apr 23 02:53:02 PM PDT 24 11580184870 ps
T867 /workspace/coverage/default/5.lc_ctrl_smoke.4011486423 Apr 23 02:47:10 PM PDT 24 Apr 23 02:47:14 PM PDT 24 233021871 ps
T868 /workspace/coverage/default/24.lc_ctrl_state_post_trans.4154240706 Apr 23 02:48:37 PM PDT 24 Apr 23 02:48:42 PM PDT 24 76405988 ps
T869 /workspace/coverage/default/0.lc_ctrl_prog_failure.292958713 Apr 23 02:46:46 PM PDT 24 Apr 23 02:46:49 PM PDT 24 173034821 ps
T870 /workspace/coverage/default/2.lc_ctrl_security_escalation.2778020442 Apr 23 02:47:06 PM PDT 24 Apr 23 02:47:14 PM PDT 24 931830104 ps
T871 /workspace/coverage/default/44.lc_ctrl_errors.737627277 Apr 23 02:49:42 PM PDT 24 Apr 23 02:49:54 PM PDT 24 289224870 ps
T69 /workspace/coverage/default/15.lc_ctrl_stress_all.704930228 Apr 23 02:48:07 PM PDT 24 Apr 23 02:48:54 PM PDT 24 3191243837 ps
T872 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.774587763 Apr 23 02:47:21 PM PDT 24 Apr 23 02:47:33 PM PDT 24 3305344639 ps
T873 /workspace/coverage/default/3.lc_ctrl_jtag_priority.53638424 Apr 23 02:47:03 PM PDT 24 Apr 23 02:47:07 PM PDT 24 178887552 ps
T91 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2929408097 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:04 PM PDT 24 491528763 ps
T104 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.470479854 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:09 PM PDT 24 74466978 ps
T95 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2563837020 Apr 23 01:45:13 PM PDT 24 Apr 23 01:45:15 PM PDT 24 107855140 ps
T105 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2967086597 Apr 23 01:45:11 PM PDT 24 Apr 23 01:45:13 PM PDT 24 81267997 ps
T874 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.478191851 Apr 23 01:45:12 PM PDT 24 Apr 23 01:45:13 PM PDT 24 97005584 ps
T134 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1792236117 Apr 23 01:45:16 PM PDT 24 Apr 23 01:45:18 PM PDT 24 29831385 ps
T92 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2829628481 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:17 PM PDT 24 131781506 ps
T102 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2510243194 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:06 PM PDT 24 69074693 ps
T147 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.213701534 Apr 23 01:45:11 PM PDT 24 Apr 23 01:45:13 PM PDT 24 39874183 ps
T103 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3030996638 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:17 PM PDT 24 186442751 ps
T182 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2142489618 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:17 PM PDT 24 26775064 ps
T135 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3917966819 Apr 23 01:45:21 PM PDT 24 Apr 23 01:45:23 PM PDT 24 61246892 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3005350342 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:17 PM PDT 24 52756695 ps
T196 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3713462500 Apr 23 01:44:55 PM PDT 24 Apr 23 01:44:57 PM PDT 24 54040462 ps
T197 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3516611711 Apr 23 01:44:56 PM PDT 24 Apr 23 01:44:58 PM PDT 24 37826290 ps
T183 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1885855626 Apr 23 01:45:00 PM PDT 24 Apr 23 01:45:02 PM PDT 24 14219896 ps
T127 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1812373565 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:05 PM PDT 24 232021107 ps
T198 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.656556452 Apr 23 01:44:52 PM PDT 24 Apr 23 01:44:54 PM PDT 24 21964111 ps
T93 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3487060606 Apr 23 01:45:17 PM PDT 24 Apr 23 01:45:20 PM PDT 24 84367362 ps
T128 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1434409284 Apr 23 01:45:00 PM PDT 24 Apr 23 01:45:02 PM PDT 24 24250795 ps
T875 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2000173404 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:08 PM PDT 24 32309208 ps
T123 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2828295661 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:08 PM PDT 24 555519743 ps
T876 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1434936637 Apr 23 01:45:14 PM PDT 24 Apr 23 01:45:16 PM PDT 24 23395501 ps
T96 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3185105521 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:10 PM PDT 24 571502745 ps
T877 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1102485555 Apr 23 01:44:53 PM PDT 24 Apr 23 01:44:55 PM PDT 24 26468852 ps
T97 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3210752287 Apr 23 01:45:12 PM PDT 24 Apr 23 01:45:14 PM PDT 24 48638723 ps
T148 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1309920307 Apr 23 01:45:10 PM PDT 24 Apr 23 01:45:13 PM PDT 24 20878634 ps
T124 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3631969272 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:05 PM PDT 24 767717907 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.102620699 Apr 23 01:44:56 PM PDT 24 Apr 23 01:44:58 PM PDT 24 16732275 ps
T879 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.320069596 Apr 23 01:45:08 PM PDT 24 Apr 23 01:45:11 PM PDT 24 187499977 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1700638986 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:04 PM PDT 24 15630633 ps
T98 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.178992667 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:06 PM PDT 24 76724587 ps
T126 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3854002887 Apr 23 01:44:54 PM PDT 24 Apr 23 01:44:56 PM PDT 24 63953752 ps
T200 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.863944666 Apr 23 01:44:52 PM PDT 24 Apr 23 01:45:24 PM PDT 24 1335578332 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3092194530 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:04 PM PDT 24 106576137 ps
T99 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2946043328 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:06 PM PDT 24 131228414 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1732531128 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:07 PM PDT 24 43688271 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1716533941 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:12 PM PDT 24 391502877 ps
T111 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3860121464 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:14 PM PDT 24 241203639 ps
T184 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1605821725 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:04 PM PDT 24 41129554 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1308031766 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:06 PM PDT 24 64043803 ps
T125 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2699874834 Apr 23 01:44:48 PM PDT 24 Apr 23 01:44:51 PM PDT 24 155542955 ps
T885 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4235912851 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:04 PM PDT 24 474792911 ps
T886 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2625779623 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:10 PM PDT 24 3745845555 ps
T100 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4070169831 Apr 23 01:45:13 PM PDT 24 Apr 23 01:45:16 PM PDT 24 236775251 ps
T106 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2262617069 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:07 PM PDT 24 335827091 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1372403332 Apr 23 01:44:54 PM PDT 24 Apr 23 01:45:03 PM PDT 24 4367162423 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2878951970 Apr 23 01:44:58 PM PDT 24 Apr 23 01:45:00 PM PDT 24 55737939 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4285106317 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:11 PM PDT 24 20027469 ps
T890 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2151707968 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:03 PM PDT 24 26203303 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3513802144 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:12 PM PDT 24 36960788 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3691687390 Apr 23 01:44:53 PM PDT 24 Apr 23 01:44:55 PM PDT 24 77419375 ps
T893 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.931743261 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:08 PM PDT 24 467106445 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2196567560 Apr 23 01:44:59 PM PDT 24 Apr 23 01:45:01 PM PDT 24 84776282 ps
T895 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4257018651 Apr 23 01:45:17 PM PDT 24 Apr 23 01:45:19 PM PDT 24 33943574 ps
T108 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4163027356 Apr 23 01:45:08 PM PDT 24 Apr 23 01:45:12 PM PDT 24 126160798 ps
T185 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.484104907 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:06 PM PDT 24 14337758 ps
T186 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1685498507 Apr 23 01:45:00 PM PDT 24 Apr 23 01:45:03 PM PDT 24 59386188 ps
T896 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.970339146 Apr 23 01:44:51 PM PDT 24 Apr 23 01:44:53 PM PDT 24 88451378 ps
T109 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2820490452 Apr 23 01:44:56 PM PDT 24 Apr 23 01:45:00 PM PDT 24 114451644 ps
T120 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.654271554 Apr 23 01:45:13 PM PDT 24 Apr 23 01:45:17 PM PDT 24 72434123 ps
T187 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2309037321 Apr 23 01:45:08 PM PDT 24 Apr 23 01:45:10 PM PDT 24 17545848 ps
T188 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1972282005 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:07 PM PDT 24 18247155 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1393087082 Apr 23 01:45:00 PM PDT 24 Apr 23 01:45:03 PM PDT 24 267864750 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3293846216 Apr 23 01:44:55 PM PDT 24 Apr 23 01:44:58 PM PDT 24 108987428 ps
T899 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.775268927 Apr 23 01:45:00 PM PDT 24 Apr 23 01:45:03 PM PDT 24 18014610 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3165002183 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:04 PM PDT 24 32712352 ps
T901 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1491971544 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:17 PM PDT 24 16031602 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2286353177 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:12 PM PDT 24 283239331 ps
T191 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1109229404 Apr 23 01:44:56 PM PDT 24 Apr 23 01:44:58 PM PDT 24 33174131 ps
T903 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1225168841 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:11 PM PDT 24 831981721 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.197774046 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:04 PM PDT 24 1183771974 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3058375409 Apr 23 01:44:51 PM PDT 24 Apr 23 01:44:53 PM PDT 24 54186063 ps
T906 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1872370886 Apr 23 01:45:11 PM PDT 24 Apr 23 01:45:14 PM PDT 24 410523148 ps
T907 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3470271810 Apr 23 01:45:29 PM PDT 24 Apr 23 01:45:32 PM PDT 24 138946671 ps
T908 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1593171082 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:11 PM PDT 24 67298946 ps
T909 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.101265339 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:15 PM PDT 24 7737017618 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4070298357 Apr 23 01:45:10 PM PDT 24 Apr 23 01:45:13 PM PDT 24 1170063767 ps
T911 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.505542794 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:11 PM PDT 24 217245822 ps
T912 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1191380316 Apr 23 01:45:27 PM PDT 24 Apr 23 01:45:28 PM PDT 24 57433004 ps
T913 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2427801521 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:04 PM PDT 24 65244640 ps
T914 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496267909 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:07 PM PDT 24 370712088 ps
T189 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.752705770 Apr 23 01:44:55 PM PDT 24 Apr 23 01:44:56 PM PDT 24 15040715 ps
T122 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1162327780 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:13 PM PDT 24 126656672 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3503698840 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:05 PM PDT 24 489422942 ps
T190 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4022892507 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:05 PM PDT 24 41248657 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2203527309 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:19 PM PDT 24 497102861 ps
T917 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1392762873 Apr 23 01:45:08 PM PDT 24 Apr 23 01:45:11 PM PDT 24 21786085 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1181743810 Apr 23 01:44:56 PM PDT 24 Apr 23 01:45:00 PM PDT 24 253890681 ps
T195 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.767934199 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:11 PM PDT 24 60622942 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2147666405 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:08 PM PDT 24 52012678 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3945516535 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:06 PM PDT 24 305303242 ps
T921 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4028822684 Apr 23 01:45:00 PM PDT 24 Apr 23 01:45:04 PM PDT 24 164126385 ps
T922 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3216863862 Apr 23 01:45:12 PM PDT 24 Apr 23 01:45:15 PM PDT 24 153721593 ps
T923 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1804741942 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:18 PM PDT 24 250655809 ps
T110 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.806215206 Apr 23 01:45:14 PM PDT 24 Apr 23 01:45:16 PM PDT 24 119578213 ps
T924 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2394945016 Apr 23 01:45:17 PM PDT 24 Apr 23 01:45:19 PM PDT 24 16255109 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3995847407 Apr 23 01:44:59 PM PDT 24 Apr 23 01:45:01 PM PDT 24 12693128 ps
T192 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.494138506 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:05 PM PDT 24 15993257 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1472144535 Apr 23 01:44:59 PM PDT 24 Apr 23 01:45:02 PM PDT 24 61867201 ps
T927 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1390161615 Apr 23 01:44:59 PM PDT 24 Apr 23 01:45:20 PM PDT 24 1084392524 ps
T928 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3391466239 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:10 PM PDT 24 60084914 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2147470094 Apr 23 01:45:08 PM PDT 24 Apr 23 01:45:11 PM PDT 24 107783819 ps
T115 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3198314088 Apr 23 01:45:18 PM PDT 24 Apr 23 01:45:23 PM PDT 24 87325529 ps
T930 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1743535530 Apr 23 01:45:17 PM PDT 24 Apr 23 01:45:20 PM PDT 24 1178924645 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.755012593 Apr 23 01:44:54 PM PDT 24 Apr 23 01:44:56 PM PDT 24 45755156 ps
T932 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2118178801 Apr 23 01:45:12 PM PDT 24 Apr 23 01:45:14 PM PDT 24 26944112 ps
T113 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.499273780 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:15 PM PDT 24 134752725 ps
T933 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2975987428 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:08 PM PDT 24 51808263 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3063708145 Apr 23 01:45:11 PM PDT 24 Apr 23 01:45:14 PM PDT 24 433245554 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1190942724 Apr 23 01:44:49 PM PDT 24 Apr 23 01:44:52 PM PDT 24 200473551 ps
T936 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2159371772 Apr 23 01:45:10 PM PDT 24 Apr 23 01:45:12 PM PDT 24 153767693 ps
T937 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3261060247 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:05 PM PDT 24 32756242 ps
T938 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.751929395 Apr 23 01:45:20 PM PDT 24 Apr 23 01:45:23 PM PDT 24 112864921 ps
T939 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2586108339 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:17 PM PDT 24 252030413 ps
T114 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3198807237 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:17 PM PDT 24 168691097 ps
T940 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3335656131 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:07 PM PDT 24 300685409 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1475120224 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:08 PM PDT 24 114525783 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3788061207 Apr 23 01:44:52 PM PDT 24 Apr 23 01:44:54 PM PDT 24 88105708 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1057087682 Apr 23 01:44:58 PM PDT 24 Apr 23 01:45:02 PM PDT 24 98524177 ps
T944 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1193537372 Apr 23 01:45:20 PM PDT 24 Apr 23 01:45:22 PM PDT 24 152616126 ps
T945 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2865749249 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:09 PM PDT 24 70419170 ps
T946 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1213823775 Apr 23 01:44:49 PM PDT 24 Apr 23 01:44:51 PM PDT 24 97657575 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1624352691 Apr 23 01:44:49 PM PDT 24 Apr 23 01:45:03 PM PDT 24 574498528 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.36774912 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:09 PM PDT 24 418138651 ps
T949 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2154066036 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:06 PM PDT 24 43570395 ps
T950 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2374632448 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:03 PM PDT 24 22247342 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3622941592 Apr 23 01:44:59 PM PDT 24 Apr 23 01:45:01 PM PDT 24 72284912 ps
T952 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.553191361 Apr 23 01:44:54 PM PDT 24 Apr 23 01:44:56 PM PDT 24 32370085 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.618180199 Apr 23 01:44:54 PM PDT 24 Apr 23 01:44:56 PM PDT 24 34816052 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.851336713 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:31 PM PDT 24 3331827870 ps
T107 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2253719377 Apr 23 01:45:10 PM PDT 24 Apr 23 01:45:13 PM PDT 24 252477236 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1152743548 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:08 PM PDT 24 125662186 ps
T955 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.206348113 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:16 PM PDT 24 974254807 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2347376872 Apr 23 01:45:08 PM PDT 24 Apr 23 01:45:13 PM PDT 24 528469998 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3997503612 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:24 PM PDT 24 1367879920 ps
T958 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.791607122 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:23 PM PDT 24 326226172 ps
T959 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2491302023 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:07 PM PDT 24 68182163 ps
T960 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2447534804 Apr 23 01:44:58 PM PDT 24 Apr 23 01:45:08 PM PDT 24 362499871 ps
T961 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1501094368 Apr 23 01:44:58 PM PDT 24 Apr 23 01:44:59 PM PDT 24 54820843 ps
T962 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2166267391 Apr 23 01:45:14 PM PDT 24 Apr 23 01:45:16 PM PDT 24 31046170 ps
T963 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1453960272 Apr 23 01:45:20 PM PDT 24 Apr 23 01:45:22 PM PDT 24 53169129 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1297853547 Apr 23 01:44:53 PM PDT 24 Apr 23 01:44:54 PM PDT 24 22960140 ps
T965 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2610623094 Apr 23 01:45:13 PM PDT 24 Apr 23 01:45:16 PM PDT 24 31439351 ps
T966 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2746028482 Apr 23 01:45:40 PM PDT 24 Apr 23 01:45:42 PM PDT 24 160436544 ps
T967 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4001579235 Apr 23 01:44:58 PM PDT 24 Apr 23 01:45:01 PM PDT 24 78874028 ps
T968 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3353815928 Apr 23 01:44:54 PM PDT 24 Apr 23 01:44:57 PM PDT 24 535955838 ps
T969 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2130101092 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:12 PM PDT 24 3725481832 ps
T970 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1039421685 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:14 PM PDT 24 639099203 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.726642363 Apr 23 01:45:09 PM PDT 24 Apr 23 01:45:15 PM PDT 24 524108478 ps
T117 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2148173230 Apr 23 01:45:15 PM PDT 24 Apr 23 01:45:17 PM PDT 24 250866467 ps
T972 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1213005158 Apr 23 01:44:58 PM PDT 24 Apr 23 01:45:01 PM PDT 24 92461691 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1001568171 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:05 PM PDT 24 123605340 ps
T974 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2618431765 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:07 PM PDT 24 57074630 ps
T975 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3288514794 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:11 PM PDT 24 397242890 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2891644449 Apr 23 01:44:52 PM PDT 24 Apr 23 01:45:01 PM PDT 24 807873593 ps
T977 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2261570783 Apr 23 01:44:56 PM PDT 24 Apr 23 01:44:58 PM PDT 24 61541808 ps
T978 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3179612699 Apr 23 01:45:14 PM PDT 24 Apr 23 01:45:23 PM PDT 24 897221150 ps
T118 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3650001556 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:09 PM PDT 24 219216972 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2032094453 Apr 23 01:44:57 PM PDT 24 Apr 23 01:45:01 PM PDT 24 61476927 ps
T979 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3187009045 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:14 PM PDT 24 476873708 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.919049438 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:12 PM PDT 24 1365818645 ps
T194 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.497960783 Apr 23 01:44:51 PM PDT 24 Apr 23 01:44:53 PM PDT 24 20391795 ps
T981 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.163266773 Apr 23 01:45:14 PM PDT 24 Apr 23 01:45:17 PM PDT 24 231263697 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1439002888 Apr 23 01:45:00 PM PDT 24 Apr 23 01:45:12 PM PDT 24 1700642517 ps
T983 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.788646576 Apr 23 01:45:11 PM PDT 24 Apr 23 01:45:13 PM PDT 24 184701051 ps
T116 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2421447682 Apr 23 01:45:13 PM PDT 24 Apr 23 01:45:15 PM PDT 24 113606481 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3881584634 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:09 PM PDT 24 109231890 ps
T985 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1690036296 Apr 23 01:45:17 PM PDT 24 Apr 23 01:45:19 PM PDT 24 14827963 ps
T986 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.471499679 Apr 23 01:44:57 PM PDT 24 Apr 23 01:44:58 PM PDT 24 23943148 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1291396235 Apr 23 01:45:07 PM PDT 24 Apr 23 01:45:12 PM PDT 24 116178999 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.377222475 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:06 PM PDT 24 2280166052 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2257465520 Apr 23 01:45:01 PM PDT 24 Apr 23 01:45:03 PM PDT 24 99200252 ps
T990 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.930242092 Apr 23 01:45:18 PM PDT 24 Apr 23 01:45:20 PM PDT 24 164400596 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4237699208 Apr 23 01:45:03 PM PDT 24 Apr 23 01:45:07 PM PDT 24 532056077 ps
T992 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3786949154 Apr 23 01:45:17 PM PDT 24 Apr 23 01:45:18 PM PDT 24 47192840 ps
T119 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.689346864 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:08 PM PDT 24 229046562 ps
T993 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1967497885 Apr 23 01:44:57 PM PDT 24 Apr 23 01:44:58 PM PDT 24 18556664 ps
T994 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2017778314 Apr 23 01:45:02 PM PDT 24 Apr 23 01:45:05 PM PDT 24 851827488 ps
T995 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1097827822 Apr 23 01:45:04 PM PDT 24 Apr 23 01:45:06 PM PDT 24 73074434 ps
T996 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1920604899 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:14 PM PDT 24 1420585664 ps
T997 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1027305170 Apr 23 01:45:05 PM PDT 24 Apr 23 01:45:07 PM PDT 24 45921143 ps
T998 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2451351002 Apr 23 01:45:13 PM PDT 24 Apr 23 01:45:18 PM PDT 24 137283018 ps
T999 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.195387485 Apr 23 01:45:11 PM PDT 24 Apr 23 01:45:13 PM PDT 24 19798575 ps
T112 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1679375453 Apr 23 01:45:06 PM PDT 24 Apr 23 01:45:09 PM PDT 24 171388171 ps

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2842887898
Short name T1
Test name
Test status
Simulation time 33722080426 ps
CPU time 248.75 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 251116 kb
Host smart-c161f71b-f2bf-4347-b757-a75f8beef703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842887898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2842887898
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.696504913
Short name T17
Test name
Test status
Simulation time 915482449 ps
CPU time 13.75 seconds
Started Apr 23 02:49:04 PM PDT 24
Finished Apr 23 02:49:18 PM PDT 24
Peak memory 218016 kb
Host smart-1e772c4c-0e5f-4169-a365-5974e19bb7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696504913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.696504913
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1849284544
Short name T34
Test name
Test status
Simulation time 439412292 ps
CPU time 9.59 seconds
Started Apr 23 02:49:35 PM PDT 24
Finished Apr 23 02:49:45 PM PDT 24
Peak memory 218064 kb
Host smart-d993dc58-462c-43e5-94a2-47b9b7219267
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849284544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1849284544
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1809266594
Short name T19
Test name
Test status
Simulation time 45764955766 ps
CPU time 1092.47 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 03:06:36 PM PDT 24
Peak memory 316708 kb
Host smart-a1662fd0-1318-4cde-9233-b3519261939a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1809266594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1809266594
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2829628481
Short name T92
Test name
Test status
Simulation time 131781506 ps
CPU time 1.59 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 217480 kb
Host smart-531840e6-2dc5-403d-89d0-c4b4b9059b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829628481 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2829628481
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1563232045
Short name T15
Test name
Test status
Simulation time 2855650568 ps
CPU time 16.23 seconds
Started Apr 23 02:49:19 PM PDT 24
Finished Apr 23 02:49:36 PM PDT 24
Peak memory 218124 kb
Host smart-65b1936f-5a95-4b2b-bba5-c97981169f8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563232045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1563232045
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2056377356
Short name T145
Test name
Test status
Simulation time 804717616 ps
CPU time 10.21 seconds
Started Apr 23 02:46:50 PM PDT 24
Finished Apr 23 02:47:01 PM PDT 24
Peak memory 224744 kb
Host smart-cce3eb9c-fa5f-4d14-84b8-d581c8fb32d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056377356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2056377356
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3137596468
Short name T14
Test name
Test status
Simulation time 51179005941 ps
CPU time 704.03 seconds
Started Apr 23 02:49:54 PM PDT 24
Finished Apr 23 03:01:38 PM PDT 24
Peak memory 293660 kb
Host smart-483efe5e-92b7-4b26-b486-76cea7910762
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137596468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3137596468
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4055529434
Short name T45
Test name
Test status
Simulation time 180939759 ps
CPU time 24.44 seconds
Started Apr 23 02:46:57 PM PDT 24
Finished Apr 23 02:47:22 PM PDT 24
Peak memory 269580 kb
Host smart-89f45085-ff51-43a4-bb7b-c00f9cac5d2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055529434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4055529434
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.885531902
Short name T23
Test name
Test status
Simulation time 121151830 ps
CPU time 2.12 seconds
Started Apr 23 02:46:53 PM PDT 24
Finished Apr 23 02:46:56 PM PDT 24
Peak memory 216920 kb
Host smart-ab16d24c-a1e4-4558-bfb6-d01a090a2a08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885531902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.885531902
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4163027356
Short name T108
Test name
Test status
Simulation time 126160798 ps
CPU time 3.07 seconds
Started Apr 23 01:45:08 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 222296 kb
Host smart-59d17d18-e877-4259-84c4-4db0157194e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163027356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.4163027356
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1397381541
Short name T259
Test name
Test status
Simulation time 24210967 ps
CPU time 0.8 seconds
Started Apr 23 02:47:55 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 209376 kb
Host smart-840fc1fe-bfee-4f28-a0c0-00b471e3b87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397381541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1397381541
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2699874834
Short name T125
Test name
Test status
Simulation time 155542955 ps
CPU time 1.75 seconds
Started Apr 23 01:44:48 PM PDT 24
Finished Apr 23 01:44:51 PM PDT 24
Peak memory 209160 kb
Host smart-1aa28564-32a4-4dbf-9ae7-807f32b639cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699874834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2699874834
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1972282005
Short name T188
Test name
Test status
Simulation time 18247155 ps
CPU time 1.25 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 209756 kb
Host smart-669dd7f3-584b-46d2-b96b-334ff7717856
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972282005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1972282005
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3185105521
Short name T96
Test name
Test status
Simulation time 571502745 ps
CPU time 3.39 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:10 PM PDT 24
Peak memory 217444 kb
Host smart-e89b407f-2e0f-499f-8612-8fa4b171e7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185105521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3185105521
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.521989586
Short name T42
Test name
Test status
Simulation time 443912755 ps
CPU time 14.23 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:21 PM PDT 24
Peak memory 218052 kb
Host smart-5d70c763-272c-4f5b-bb24-6571f339d33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521989586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.521989586
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.558259873
Short name T32
Test name
Test status
Simulation time 17913586293 ps
CPU time 181.44 seconds
Started Apr 23 02:48:47 PM PDT 24
Finished Apr 23 02:51:49 PM PDT 24
Peak memory 251068 kb
Host smart-2d13d3aa-37be-4aff-a5da-d7fca45752ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558259873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.558259873
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.499273780
Short name T113
Test name
Test status
Simulation time 134752725 ps
CPU time 4.56 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:15 PM PDT 24
Peak memory 217484 kb
Host smart-108f28e3-3ca1-4171-ac67-b2b2255244b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499273780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.499273780
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.79864233
Short name T38
Test name
Test status
Simulation time 77295611555 ps
CPU time 723.83 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:59:43 PM PDT 24
Peak memory 545968 kb
Host smart-6550d19f-665e-43e5-9a95-8cc66cf2c528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=79864233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.79864233
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.689346864
Short name T119
Test name
Test status
Simulation time 229046562 ps
CPU time 3.07 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 221920 kb
Host smart-dbf69acb-c30f-4dcb-afbd-b1fecd631477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689346864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.689346864
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2034761022
Short name T680
Test name
Test status
Simulation time 540819020 ps
CPU time 28.7 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:47:18 PM PDT 24
Peak memory 250980 kb
Host smart-e105c517-43be-4086-87e9-b1122ac839dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034761022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2034761022
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2142489618
Short name T182
Test name
Test status
Simulation time 26775064 ps
CPU time 0.85 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 209268 kb
Host smart-3a487dea-dc2f-4a99-b54e-f7b6f6899f37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142489618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2142489618
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1287577380
Short name T8
Test name
Test status
Simulation time 51608259 ps
CPU time 0.93 seconds
Started Apr 23 02:47:44 PM PDT 24
Finished Apr 23 02:47:45 PM PDT 24
Peak memory 212900 kb
Host smart-d9ea9d63-241c-4f08-826c-364188d278dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287577380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1287577380
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2148173230
Short name T117
Test name
Test status
Simulation time 250866467 ps
CPU time 1.85 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 221612 kb
Host smart-c43867f0-927a-4339-a592-f36d84f79acd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148173230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2148173230
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.42151970
Short name T204
Test name
Test status
Simulation time 13396958 ps
CPU time 0.82 seconds
Started Apr 23 02:46:42 PM PDT 24
Finished Apr 23 02:46:43 PM PDT 24
Peak memory 209388 kb
Host smart-da4a6472-d0b4-442c-ab1f-3b07ad4dae94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42151970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.42151970
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2448968003
Short name T201
Test name
Test status
Simulation time 21444985 ps
CPU time 0.81 seconds
Started Apr 23 02:46:50 PM PDT 24
Finished Apr 23 02:46:52 PM PDT 24
Peak memory 209308 kb
Host smart-84a120cf-4519-4958-a5c2-8a9ec8bcfb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448968003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2448968003
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2975105884
Short name T205
Test name
Test status
Simulation time 11560646 ps
CPU time 0.95 seconds
Started Apr 23 02:47:15 PM PDT 24
Finished Apr 23 02:47:16 PM PDT 24
Peak memory 209564 kb
Host smart-89bf39da-b32c-426a-95a6-277dcd2f70f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975105884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2975105884
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.416197942
Short name T39
Test name
Test status
Simulation time 126488116910 ps
CPU time 624.94 seconds
Started Apr 23 02:49:31 PM PDT 24
Finished Apr 23 02:59:57 PM PDT 24
Peak memory 316768 kb
Host smart-094e7249-677d-48f7-8780-1132d26c2d84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=416197942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.416197942
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2929408097
Short name T91
Test name
Test status
Simulation time 491528763 ps
CPU time 2.69 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 217576 kb
Host smart-6b560492-32c2-4f40-b822-26b3193f6c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929408097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2929408097
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2032094453
Short name T121
Test name
Test status
Simulation time 61476927 ps
CPU time 2.73 seconds
Started Apr 23 01:44:57 PM PDT 24
Finished Apr 23 01:45:01 PM PDT 24
Peak memory 217404 kb
Host smart-b68207ba-9201-4bc2-90d2-a6163bfd0f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032094453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2032094453
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2253719377
Short name T107
Test name
Test status
Simulation time 252477236 ps
CPU time 2.25 seconds
Started Apr 23 01:45:10 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 221900 kb
Host smart-a97d80ef-a366-419b-a015-23d8d6bc62f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253719377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2253719377
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1162327780
Short name T122
Test name
Test status
Simulation time 126656672 ps
CPU time 2.51 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 217424 kb
Host smart-f8ef5412-649a-48b2-ac1a-8608121e1a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162327780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1162327780
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3198314088
Short name T115
Test name
Test status
Simulation time 87325529 ps
CPU time 3.9 seconds
Started Apr 23 01:45:18 PM PDT 24
Finished Apr 23 01:45:23 PM PDT 24
Peak memory 217476 kb
Host smart-518c2cc0-e30f-4d33-b655-80b99320caea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198314088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3198314088
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.806215206
Short name T110
Test name
Test status
Simulation time 119578213 ps
CPU time 1.88 seconds
Started Apr 23 01:45:14 PM PDT 24
Finished Apr 23 01:45:16 PM PDT 24
Peak memory 221664 kb
Host smart-138c1c58-7a98-45eb-bbc6-27f0ccd3bc62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806215206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.806215206
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3650001556
Short name T118
Test name
Test status
Simulation time 219216972 ps
CPU time 2.44 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:09 PM PDT 24
Peak memory 217392 kb
Host smart-653ff18f-e486-491b-9df0-88ce0f72f4a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650001556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3650001556
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1679375453
Short name T112
Test name
Test status
Simulation time 171388171 ps
CPU time 2.33 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:09 PM PDT 24
Peak memory 221740 kb
Host smart-303acb67-7fd2-42f1-9cbf-b1046a957200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679375453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1679375453
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3989171561
Short name T211
Test name
Test status
Simulation time 641537665 ps
CPU time 20.14 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:20 PM PDT 24
Peak memory 251004 kb
Host smart-8e547381-c6ee-4ff2-8d38-7dc96cb22919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989171561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3989171561
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4264831190
Short name T368
Test name
Test status
Simulation time 3957611207 ps
CPU time 60.36 seconds
Started Apr 23 02:46:47 PM PDT 24
Finished Apr 23 02:47:48 PM PDT 24
Peak memory 251132 kb
Host smart-55da7dc3-4a99-4c91-8423-0a14f2487999
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264831190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4264831190
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.618180199
Short name T193
Test name
Test status
Simulation time 34816052 ps
CPU time 1.75 seconds
Started Apr 23 01:44:54 PM PDT 24
Finished Apr 23 01:44:56 PM PDT 24
Peak memory 209248 kb
Host smart-2c26c2a5-f6e3-4bca-b851-0272c2fdedd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618180199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.618180199
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3058375409
Short name T905
Test name
Test status
Simulation time 54186063 ps
CPU time 1.47 seconds
Started Apr 23 01:44:51 PM PDT 24
Finished Apr 23 01:44:53 PM PDT 24
Peak memory 208824 kb
Host smart-948e6007-c50a-405c-8e0b-39f16a53d337
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058375409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3058375409
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.755012593
Short name T931
Test name
Test status
Simulation time 45755156 ps
CPU time 1.02 seconds
Started Apr 23 01:44:54 PM PDT 24
Finished Apr 23 01:44:56 PM PDT 24
Peak memory 209804 kb
Host smart-aeecd627-ab69-47e9-9f19-a77124041fa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755012593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.755012593
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2618431765
Short name T974
Test name
Test status
Simulation time 57074630 ps
CPU time 2.18 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 219248 kb
Host smart-5557dcef-bfe9-4e54-9c08-0193890aa431
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618431765 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2618431765
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3995847407
Short name T925
Test name
Test status
Simulation time 12693128 ps
CPU time 1.04 seconds
Started Apr 23 01:44:59 PM PDT 24
Finished Apr 23 01:45:01 PM PDT 24
Peak memory 209220 kb
Host smart-61adfa26-0049-494d-8091-26a0407ec7e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995847407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3995847407
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3165002183
Short name T900
Test name
Test status
Simulation time 32712352 ps
CPU time 1.09 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 207852 kb
Host smart-912057aa-c14d-4dd8-9249-8e54b11b17cd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165002183 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3165002183
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1624352691
Short name T947
Test name
Test status
Simulation time 574498528 ps
CPU time 13.44 seconds
Started Apr 23 01:44:49 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 209072 kb
Host smart-2f9121c3-2172-4e3f-a304-624e7fc4a648
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624352691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1624352691
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.863944666
Short name T200
Test name
Test status
Simulation time 1335578332 ps
CPU time 32.07 seconds
Started Apr 23 01:44:52 PM PDT 24
Finished Apr 23 01:45:24 PM PDT 24
Peak memory 209108 kb
Host smart-3cab4b82-5a74-41c1-9f1f-659e66f53281
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863944666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.863944666
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3788061207
Short name T942
Test name
Test status
Simulation time 88105708 ps
CPU time 1.81 seconds
Started Apr 23 01:44:52 PM PDT 24
Finished Apr 23 01:44:54 PM PDT 24
Peak memory 210616 kb
Host smart-580c24be-c5ef-4c9e-bbf4-9b27efc52e7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788061207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3788061207
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1225168841
Short name T903
Test name
Test status
Simulation time 831981721 ps
CPU time 5.89 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 217632 kb
Host smart-3c60851b-d04b-4685-bf69-36860994f7a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122516
8841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1225168841
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.970339146
Short name T896
Test name
Test status
Simulation time 88451378 ps
CPU time 1.11 seconds
Started Apr 23 01:44:51 PM PDT 24
Finished Apr 23 01:44:53 PM PDT 24
Peak memory 209188 kb
Host smart-775b5022-fbdb-48be-8400-1483f59ff487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970339146 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.970339146
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3691687390
Short name T892
Test name
Test status
Simulation time 77419375 ps
CPU time 1.09 seconds
Started Apr 23 01:44:53 PM PDT 24
Finished Apr 23 01:44:55 PM PDT 24
Peak memory 209248 kb
Host smart-480d734f-87f7-40b9-9d9c-53d53c60d385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691687390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3691687390
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2946043328
Short name T99
Test name
Test status
Simulation time 131228414 ps
CPU time 2.8 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 217392 kb
Host smart-8c84a106-e76d-4be5-8f5b-609b560a3626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946043328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2946043328
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1685498507
Short name T186
Test name
Test status
Simulation time 59386188 ps
CPU time 1.63 seconds
Started Apr 23 01:45:00 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 209248 kb
Host smart-c3d3c76d-37bc-42c8-b7e8-cab7c1b871a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685498507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1685498507
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2975987428
Short name T933
Test name
Test status
Simulation time 51808263 ps
CPU time 2.02 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 209248 kb
Host smart-704390c8-1143-459a-b861-82a303034596
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975987428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2975987428
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1885855626
Short name T183
Test name
Test status
Simulation time 14219896 ps
CPU time 1.13 seconds
Started Apr 23 01:45:00 PM PDT 24
Finished Apr 23 01:45:02 PM PDT 24
Peak memory 209804 kb
Host smart-cc29088f-6abe-4fc3-a48a-f041d48b99f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885855626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1885855626
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1700638986
Short name T880
Test name
Test status
Simulation time 15630633 ps
CPU time 1.01 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 217428 kb
Host smart-11a7d15a-fa42-44af-a512-c1c2d3338d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700638986 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1700638986
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1297853547
Short name T964
Test name
Test status
Simulation time 22960140 ps
CPU time 1.1 seconds
Started Apr 23 01:44:53 PM PDT 24
Finished Apr 23 01:44:54 PM PDT 24
Peak memory 209040 kb
Host smart-718e8af8-21ce-4f3e-98b2-5bba2d4b58e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297853547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1297853547
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4235912851
Short name T885
Test name
Test status
Simulation time 474792911 ps
CPU time 1.38 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 209072 kb
Host smart-eb02b09b-3b7e-4a6c-b2c2-3d37f53f20b8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235912851 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.4235912851
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2203527309
Short name T916
Test name
Test status
Simulation time 497102861 ps
CPU time 11.67 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:19 PM PDT 24
Peak memory 209040 kb
Host smart-810e8ae5-4cd0-42d6-9f19-266ba961664b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203527309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2203527309
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2891644449
Short name T976
Test name
Test status
Simulation time 807873593 ps
CPU time 8.49 seconds
Started Apr 23 01:44:52 PM PDT 24
Finished Apr 23 01:45:01 PM PDT 24
Peak memory 209196 kb
Host smart-d0783b58-d446-4a54-8075-2199dd9ce32a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891644449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2891644449
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2196567560
Short name T894
Test name
Test status
Simulation time 84776282 ps
CPU time 1.48 seconds
Started Apr 23 01:44:59 PM PDT 24
Finished Apr 23 01:45:01 PM PDT 24
Peak memory 210548 kb
Host smart-07bcd8d4-919d-4425-836e-12d1a162baf4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196567560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2196567560
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4028822684
Short name T921
Test name
Test status
Simulation time 164126385 ps
CPU time 3.17 seconds
Started Apr 23 01:45:00 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 217420 kb
Host smart-c247b80c-fd27-4c94-84dd-d484d38fbc29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402882
2684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4028822684
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.788646576
Short name T983
Test name
Test status
Simulation time 184701051 ps
CPU time 1.13 seconds
Started Apr 23 01:45:11 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 209204 kb
Host smart-e286f5bf-4048-4ad5-bc33-6318138e6229
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788646576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.788646576
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1213823775
Short name T946
Test name
Test status
Simulation time 97657575 ps
CPU time 1.37 seconds
Started Apr 23 01:44:49 PM PDT 24
Finished Apr 23 01:44:51 PM PDT 24
Peak memory 209360 kb
Host smart-5c48c667-36c4-4e17-889b-01b024fcf947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213823775 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1213823775
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1102485555
Short name T877
Test name
Test status
Simulation time 26468852 ps
CPU time 1.19 seconds
Started Apr 23 01:44:53 PM PDT 24
Finished Apr 23 01:44:55 PM PDT 24
Peak memory 209292 kb
Host smart-da5dd51c-d8d4-4f6e-883c-1f516524e67a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102485555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1102485555
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.197774046
Short name T904
Test name
Test status
Simulation time 1183771974 ps
CPU time 2.9 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 217584 kb
Host smart-d0e5a81b-fbc4-4eec-8e68-ffc9bb9873d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197774046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.197774046
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2610623094
Short name T965
Test name
Test status
Simulation time 31439351 ps
CPU time 2.24 seconds
Started Apr 23 01:45:13 PM PDT 24
Finished Apr 23 01:45:16 PM PDT 24
Peak memory 219732 kb
Host smart-a1401171-541c-4f20-a97c-0d3498a06145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610623094 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2610623094
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1593171082
Short name T908
Test name
Test status
Simulation time 67298946 ps
CPU time 0.94 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 208844 kb
Host smart-1d2d4dc0-22fd-4d22-8ebd-6d28f4899623
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593171082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1593171082
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2166267391
Short name T962
Test name
Test status
Simulation time 31046170 ps
CPU time 1.05 seconds
Started Apr 23 01:45:14 PM PDT 24
Finished Apr 23 01:45:16 PM PDT 24
Peak memory 209192 kb
Host smart-ee2726e8-6a6c-4f6f-857c-038b86b1dc82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166267391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2166267391
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1039421685
Short name T970
Test name
Test status
Simulation time 639099203 ps
CPU time 3.43 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 217332 kb
Host smart-0014155c-a327-43c7-85ab-5a6211a1ea03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039421685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1039421685
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2967086597
Short name T105
Test name
Test status
Simulation time 81267997 ps
CPU time 1.11 seconds
Started Apr 23 01:45:11 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 217504 kb
Host smart-b2ac2044-7a71-43ac-bfb9-e9219e35eac5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967086597 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2967086597
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.767934199
Short name T195
Test name
Test status
Simulation time 60622942 ps
CPU time 0.89 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 209224 kb
Host smart-999433c1-2315-4b23-a8e1-da8c79666802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767934199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.767934199
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2865749249
Short name T945
Test name
Test status
Simulation time 70419170 ps
CPU time 1.21 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:09 PM PDT 24
Peak memory 209388 kb
Host smart-6cdd1fee-ff8a-4964-93b3-f9b994dc777a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865749249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2865749249
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3210752287
Short name T97
Test name
Test status
Simulation time 48638723 ps
CPU time 1.67 seconds
Started Apr 23 01:45:12 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 217644 kb
Host smart-39f6216e-7992-4450-be83-6807d4f4291a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210752287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3210752287
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.213701534
Short name T147
Test name
Test status
Simulation time 39874183 ps
CPU time 1.66 seconds
Started Apr 23 01:45:11 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 217632 kb
Host smart-91e94b13-d4ae-4ca1-95c3-bc0264528f4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213701534 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.213701534
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1191380316
Short name T912
Test name
Test status
Simulation time 57433004 ps
CPU time 0.86 seconds
Started Apr 23 01:45:27 PM PDT 24
Finished Apr 23 01:45:28 PM PDT 24
Peak memory 209216 kb
Host smart-159f4858-f385-42cf-a551-2f38f30bb729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191380316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1191380316
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2118178801
Short name T932
Test name
Test status
Simulation time 26944112 ps
CPU time 1.06 seconds
Started Apr 23 01:45:12 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 209264 kb
Host smart-c00345f8-a2d3-4532-9419-e4b79f415f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118178801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2118178801
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3860121464
Short name T111
Test name
Test status
Simulation time 241203639 ps
CPU time 3.99 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 217532 kb
Host smart-a04e9d46-bd56-4940-b69e-fcf8f5599f37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860121464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3860121464
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2563837020
Short name T95
Test name
Test status
Simulation time 107855140 ps
CPU time 1.37 seconds
Started Apr 23 01:45:13 PM PDT 24
Finished Apr 23 01:45:15 PM PDT 24
Peak memory 217516 kb
Host smart-d8036dcb-8def-4c1a-ba98-fe6ae5526e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563837020 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2563837020
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.478191851
Short name T874
Test name
Test status
Simulation time 97005584 ps
CPU time 0.91 seconds
Started Apr 23 01:45:12 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 209284 kb
Host smart-531acb2d-407b-4b76-8661-b3526642e1e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478191851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.478191851
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1193537372
Short name T944
Test name
Test status
Simulation time 152616126 ps
CPU time 1.44 seconds
Started Apr 23 01:45:20 PM PDT 24
Finished Apr 23 01:45:22 PM PDT 24
Peak memory 211396 kb
Host smart-2c2859ec-0725-49e1-a3dd-7d91c6b13001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193537372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1193537372
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1872370886
Short name T906
Test name
Test status
Simulation time 410523148 ps
CPU time 1.96 seconds
Started Apr 23 01:45:11 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 217572 kb
Host smart-c3da8697-9754-4920-91cf-9309ddac08ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872370886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1872370886
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.654271554
Short name T120
Test name
Test status
Simulation time 72434123 ps
CPU time 2.87 seconds
Started Apr 23 01:45:13 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 217424 kb
Host smart-15558a08-7ed0-4085-b36d-3387c59a7e65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654271554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.654271554
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.930242092
Short name T990
Test name
Test status
Simulation time 164400596 ps
CPU time 1.55 seconds
Started Apr 23 01:45:18 PM PDT 24
Finished Apr 23 01:45:20 PM PDT 24
Peak memory 222832 kb
Host smart-d92a13cb-085c-4a74-b656-970d9dda1d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930242092 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.930242092
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.195387485
Short name T999
Test name
Test status
Simulation time 19798575 ps
CPU time 0.94 seconds
Started Apr 23 01:45:11 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 209248 kb
Host smart-50cd60ae-9da6-430d-82b8-70857846cbbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195387485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.195387485
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.163266773
Short name T981
Test name
Test status
Simulation time 231263697 ps
CPU time 2.1 seconds
Started Apr 23 01:45:14 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 211364 kb
Host smart-63a88e40-9da5-4f8a-aad4-eed4ee225e20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163266773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.163266773
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3179612699
Short name T978
Test name
Test status
Simulation time 897221150 ps
CPU time 3.77 seconds
Started Apr 23 01:45:14 PM PDT 24
Finished Apr 23 01:45:23 PM PDT 24
Peak memory 217560 kb
Host smart-1d049808-ed9c-426c-a854-05d0c207956f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179612699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3179612699
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4070169831
Short name T100
Test name
Test status
Simulation time 236775251 ps
CPU time 2.02 seconds
Started Apr 23 01:45:13 PM PDT 24
Finished Apr 23 01:45:16 PM PDT 24
Peak memory 221560 kb
Host smart-327aa9db-fe1b-47c4-af0d-c1ba7838bf78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070169831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.4070169831
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.751929395
Short name T938
Test name
Test status
Simulation time 112864921 ps
CPU time 2.28 seconds
Started Apr 23 01:45:20 PM PDT 24
Finished Apr 23 01:45:23 PM PDT 24
Peak memory 218604 kb
Host smart-761cdb70-a25a-4003-a56b-98cf6c2c73cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751929395 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.751929395
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3786949154
Short name T992
Test name
Test status
Simulation time 47192840 ps
CPU time 0.89 seconds
Started Apr 23 01:45:17 PM PDT 24
Finished Apr 23 01:45:18 PM PDT 24
Peak memory 209208 kb
Host smart-c87d156a-2019-4cf0-9bc2-3e878fcd2147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786949154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3786949154
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1434936637
Short name T876
Test name
Test status
Simulation time 23395501 ps
CPU time 1.23 seconds
Started Apr 23 01:45:14 PM PDT 24
Finished Apr 23 01:45:16 PM PDT 24
Peak memory 209272 kb
Host smart-8f253d4d-c9bb-48df-b967-df9e50e9e801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434936637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1434936637
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3216863862
Short name T922
Test name
Test status
Simulation time 153721593 ps
CPU time 2.76 seconds
Started Apr 23 01:45:12 PM PDT 24
Finished Apr 23 01:45:15 PM PDT 24
Peak memory 217580 kb
Host smart-6868e1e7-3d7e-410a-8c42-0386a4ebb983
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216863862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3216863862
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2394945016
Short name T924
Test name
Test status
Simulation time 16255109 ps
CPU time 1.04 seconds
Started Apr 23 01:45:17 PM PDT 24
Finished Apr 23 01:45:19 PM PDT 24
Peak memory 209328 kb
Host smart-6f21adb3-571b-4153-8635-9ce97539f025
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394945016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2394945016
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1804741942
Short name T923
Test name
Test status
Simulation time 250655809 ps
CPU time 2.01 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:18 PM PDT 24
Peak memory 217616 kb
Host smart-be3525db-930e-4f43-9e05-06cd13e43a18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804741942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1804741942
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2586108339
Short name T939
Test name
Test status
Simulation time 252030413 ps
CPU time 1.7 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 219268 kb
Host smart-42450c5b-d43c-4904-97c3-0f3614117696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586108339 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2586108339
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1690036296
Short name T985
Test name
Test status
Simulation time 14827963 ps
CPU time 0.96 seconds
Started Apr 23 01:45:17 PM PDT 24
Finished Apr 23 01:45:19 PM PDT 24
Peak memory 208692 kb
Host smart-a1cf9d73-0f06-4afa-affb-310dc7b3f2ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690036296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1690036296
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1792236117
Short name T134
Test name
Test status
Simulation time 29831385 ps
CPU time 1.43 seconds
Started Apr 23 01:45:16 PM PDT 24
Finished Apr 23 01:45:18 PM PDT 24
Peak memory 209336 kb
Host smart-b5a83196-b341-41e7-bdd0-534f07c81343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792236117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1792236117
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1743535530
Short name T930
Test name
Test status
Simulation time 1178924645 ps
CPU time 2.35 seconds
Started Apr 23 01:45:17 PM PDT 24
Finished Apr 23 01:45:20 PM PDT 24
Peak memory 217516 kb
Host smart-c6a08e3c-9bc2-4fb2-8643-098d55986408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743535530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1743535530
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2421447682
Short name T116
Test name
Test status
Simulation time 113606481 ps
CPU time 2.06 seconds
Started Apr 23 01:45:13 PM PDT 24
Finished Apr 23 01:45:15 PM PDT 24
Peak memory 221416 kb
Host smart-bfc8f58b-2a63-40cb-8fc5-9bac532c6036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421447682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2421447682
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4257018651
Short name T895
Test name
Test status
Simulation time 33943574 ps
CPU time 1.21 seconds
Started Apr 23 01:45:17 PM PDT 24
Finished Apr 23 01:45:19 PM PDT 24
Peak memory 217568 kb
Host smart-46da6370-5ca0-482e-b3e1-1e2d6b18d5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257018651 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4257018651
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3917966819
Short name T135
Test name
Test status
Simulation time 61246892 ps
CPU time 0.9 seconds
Started Apr 23 01:45:21 PM PDT 24
Finished Apr 23 01:45:23 PM PDT 24
Peak memory 208948 kb
Host smart-44774ef1-b571-459f-abce-db1b06b2292b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917966819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3917966819
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2746028482
Short name T966
Test name
Test status
Simulation time 160436544 ps
CPU time 1.28 seconds
Started Apr 23 01:45:40 PM PDT 24
Finished Apr 23 01:45:42 PM PDT 24
Peak memory 211100 kb
Host smart-f32c2bbb-31b7-413b-9fd2-aad2c3b74fe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746028482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2746028482
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3470271810
Short name T907
Test name
Test status
Simulation time 138946671 ps
CPU time 2.4 seconds
Started Apr 23 01:45:29 PM PDT 24
Finished Apr 23 01:45:32 PM PDT 24
Peak memory 218528 kb
Host smart-d546df36-2bb4-4784-9d4b-f69769715eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470271810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3470271810
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1453960272
Short name T963
Test name
Test status
Simulation time 53169129 ps
CPU time 1.19 seconds
Started Apr 23 01:45:20 PM PDT 24
Finished Apr 23 01:45:22 PM PDT 24
Peak memory 217792 kb
Host smart-90eefe87-155d-4d04-9ce1-3ab0d171381b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453960272 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1453960272
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1491971544
Short name T901
Test name
Test status
Simulation time 16031602 ps
CPU time 0.91 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 209268 kb
Host smart-37c10b00-1f24-4fac-909f-5afaa7fbdabf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491971544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1491971544
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3030996638
Short name T103
Test name
Test status
Simulation time 186442751 ps
CPU time 1.41 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 211220 kb
Host smart-fdc7e4eb-5403-4cbd-87c1-64ef483d5c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030996638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3030996638
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.791607122
Short name T958
Test name
Test status
Simulation time 326226172 ps
CPU time 2.83 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:23 PM PDT 24
Peak memory 218288 kb
Host smart-05b195a4-9ea4-4808-8fa4-e2739853e357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791607122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.791607122
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3487060606
Short name T93
Test name
Test status
Simulation time 84367362 ps
CPU time 2.35 seconds
Started Apr 23 01:45:17 PM PDT 24
Finished Apr 23 01:45:20 PM PDT 24
Peak memory 221628 kb
Host smart-d132dbe2-7493-43f8-b09e-da31998b47b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487060606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3487060606
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2000173404
Short name T875
Test name
Test status
Simulation time 32309208 ps
CPU time 1.39 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 209236 kb
Host smart-ae146c24-b944-4217-84f4-f32da3dd139d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000173404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2000173404
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1109229404
Short name T191
Test name
Test status
Simulation time 33174131 ps
CPU time 1.25 seconds
Started Apr 23 01:44:56 PM PDT 24
Finished Apr 23 01:44:58 PM PDT 24
Peak memory 208384 kb
Host smart-2a6901aa-f19d-4db0-8502-dda232d8dff2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109229404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1109229404
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.553191361
Short name T952
Test name
Test status
Simulation time 32370085 ps
CPU time 1.9 seconds
Started Apr 23 01:44:54 PM PDT 24
Finished Apr 23 01:44:56 PM PDT 24
Peak memory 223804 kb
Host smart-650259c2-1393-4f76-8a90-bf8bc8fff6a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553191361 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.553191361
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1967497885
Short name T993
Test name
Test status
Simulation time 18556664 ps
CPU time 1.12 seconds
Started Apr 23 01:44:57 PM PDT 24
Finished Apr 23 01:44:58 PM PDT 24
Peak memory 209100 kb
Host smart-080c8da8-a63a-4c14-801d-640d5041e011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967497885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1967497885
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1434409284
Short name T128
Test name
Test status
Simulation time 24250795 ps
CPU time 1.28 seconds
Started Apr 23 01:45:00 PM PDT 24
Finished Apr 23 01:45:02 PM PDT 24
Peak memory 209156 kb
Host smart-4279ed00-bb52-4604-91a6-5484a1aa3061
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434409284 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1434409284
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2447534804
Short name T960
Test name
Test status
Simulation time 362499871 ps
CPU time 9.71 seconds
Started Apr 23 01:44:58 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 208948 kb
Host smart-675e8ab2-9437-41ff-b48e-18742ea37ee2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447534804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2447534804
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1372403332
Short name T887
Test name
Test status
Simulation time 4367162423 ps
CPU time 8.96 seconds
Started Apr 23 01:44:54 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 209140 kb
Host smart-2315a9a6-5907-4830-972c-d7290d8c40a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372403332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1372403332
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2828295661
Short name T123
Test name
Test status
Simulation time 555519743 ps
CPU time 2.01 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 210728 kb
Host smart-b98199ce-a3ab-4ce4-bdc2-16497a474fc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828295661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2828295661
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2820490452
Short name T109
Test name
Test status
Simulation time 114451644 ps
CPU time 2.38 seconds
Started Apr 23 01:44:56 PM PDT 24
Finished Apr 23 01:45:00 PM PDT 24
Peak memory 220056 kb
Host smart-c14ac884-6389-4faf-ad67-1254c1dcc263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282049
0452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2820490452
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3854002887
Short name T126
Test name
Test status
Simulation time 63953752 ps
CPU time 1.06 seconds
Started Apr 23 01:44:54 PM PDT 24
Finished Apr 23 01:44:56 PM PDT 24
Peak memory 209132 kb
Host smart-1ef105bd-9423-47ad-8982-06bcaec3dffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854002887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3854002887
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.656556452
Short name T198
Test name
Test status
Simulation time 21964111 ps
CPU time 1.44 seconds
Started Apr 23 01:44:52 PM PDT 24
Finished Apr 23 01:44:54 PM PDT 24
Peak memory 209264 kb
Host smart-614825b9-ab70-4979-afef-8121c6bf1cfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656556452 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.656556452
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1472144535
Short name T926
Test name
Test status
Simulation time 61867201 ps
CPU time 1.22 seconds
Started Apr 23 01:44:59 PM PDT 24
Finished Apr 23 01:45:02 PM PDT 24
Peak memory 209248 kb
Host smart-a19c78b0-e275-4119-aff6-af246d4ef131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472144535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1472144535
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4022892507
Short name T190
Test name
Test status
Simulation time 41248657 ps
CPU time 1.87 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 209308 kb
Host smart-9358ddc4-686b-4533-abf6-56efc3502003
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022892507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4022892507
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.775268927
Short name T899
Test name
Test status
Simulation time 18014610 ps
CPU time 1.45 seconds
Started Apr 23 01:45:00 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 209224 kb
Host smart-37ff68e1-1d8a-4d04-9ee7-9af59858e3dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775268927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.775268927
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.102620699
Short name T878
Test name
Test status
Simulation time 16732275 ps
CPU time 1.06 seconds
Started Apr 23 01:44:56 PM PDT 24
Finished Apr 23 01:44:58 PM PDT 24
Peak memory 210504 kb
Host smart-24000148-ffee-401a-b2e6-f21e9fbbb356
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102620699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.102620699
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2261570783
Short name T977
Test name
Test status
Simulation time 61541808 ps
CPU time 1.84 seconds
Started Apr 23 01:44:56 PM PDT 24
Finished Apr 23 01:44:58 PM PDT 24
Peak memory 217612 kb
Host smart-e29b3e61-c305-4e09-b5e3-670e56500470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261570783 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2261570783
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.752705770
Short name T189
Test name
Test status
Simulation time 15040715 ps
CPU time 0.87 seconds
Started Apr 23 01:44:55 PM PDT 24
Finished Apr 23 01:44:56 PM PDT 24
Peak memory 208720 kb
Host smart-f0292b71-5097-4a3a-ae34-d69ab7b76aaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752705770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.752705770
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1732531128
Short name T882
Test name
Test status
Simulation time 43688271 ps
CPU time 1.17 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 208964 kb
Host smart-caf5d200-c44a-4843-920e-c62bf460030b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732531128 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1732531128
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.377222475
Short name T988
Test name
Test status
Simulation time 2280166052 ps
CPU time 3.15 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 208428 kb
Host smart-d72ee7b2-7769-4e56-b6d3-09c24bc04bba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377222475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.377222475
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1439002888
Short name T982
Test name
Test status
Simulation time 1700642517 ps
CPU time 11.05 seconds
Started Apr 23 01:45:00 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 209000 kb
Host smart-2e0fdf61-d1b7-403c-a7e4-964badc104c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439002888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1439002888
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2147470094
Short name T929
Test name
Test status
Simulation time 107783819 ps
CPU time 1.57 seconds
Started Apr 23 01:45:08 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 210588 kb
Host smart-7362395e-a906-47f5-a73e-780397e8a0dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147470094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2147470094
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4237699208
Short name T991
Test name
Test status
Simulation time 532056077 ps
CPU time 3.12 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 218148 kb
Host smart-4d605200-5c0d-4e95-a5e3-5dc8ecf63ff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423769
9208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4237699208
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1190942724
Short name T935
Test name
Test status
Simulation time 200473551 ps
CPU time 2.91 seconds
Started Apr 23 01:44:49 PM PDT 24
Finished Apr 23 01:44:52 PM PDT 24
Peak memory 209208 kb
Host smart-5520bf74-dd4b-494a-838d-38ac431d7b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190942724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1190942724
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3516611711
Short name T197
Test name
Test status
Simulation time 37826290 ps
CPU time 1.45 seconds
Started Apr 23 01:44:56 PM PDT 24
Finished Apr 23 01:44:58 PM PDT 24
Peak memory 211340 kb
Host smart-b8a844dc-eca6-43b7-9a48-3795f831eb61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516611711 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3516611711
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3092194530
Short name T881
Test name
Test status
Simulation time 106576137 ps
CPU time 1.04 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 209016 kb
Host smart-6961b75a-8010-4940-b737-c85b8815541a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092194530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3092194530
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2154066036
Short name T949
Test name
Test status
Simulation time 43570395 ps
CPU time 3.03 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 217468 kb
Host smart-82e92fbf-23aa-4d96-bb7f-89767f8b0544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154066036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2154066036
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1393087082
Short name T897
Test name
Test status
Simulation time 267864750 ps
CPU time 1.92 seconds
Started Apr 23 01:45:00 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 221756 kb
Host smart-a9bee011-fc69-4312-9a32-f711bdc99bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393087082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1393087082
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.494138506
Short name T192
Test name
Test status
Simulation time 15993257 ps
CPU time 1.02 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 208716 kb
Host smart-db09a062-2ab1-47e6-87cb-47d582ceae27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494138506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.494138506
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2491302023
Short name T959
Test name
Test status
Simulation time 68182163 ps
CPU time 1.81 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 209108 kb
Host smart-23d7e4f6-a224-467d-9a55-9e4571433743
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491302023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2491302023
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2878951970
Short name T888
Test name
Test status
Simulation time 55737939 ps
CPU time 0.89 seconds
Started Apr 23 01:44:58 PM PDT 24
Finished Apr 23 01:45:00 PM PDT 24
Peak memory 209684 kb
Host smart-d64b1ddd-9981-4de4-bbe1-8c60fa2c96c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878951970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2878951970
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1308031766
Short name T884
Test name
Test status
Simulation time 64043803 ps
CPU time 1.07 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 217580 kb
Host smart-e4c20c26-ba99-40dc-b355-9b0830b7bf45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308031766 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1308031766
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.497960783
Short name T194
Test name
Test status
Simulation time 20391795 ps
CPU time 0.98 seconds
Started Apr 23 01:44:51 PM PDT 24
Finished Apr 23 01:44:53 PM PDT 24
Peak memory 208888 kb
Host smart-aa6ddae7-69ea-4425-821a-a3e0a0f6416a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497960783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.497960783
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2427801521
Short name T913
Test name
Test status
Simulation time 65244640 ps
CPU time 1.26 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 209148 kb
Host smart-e43883d5-5936-44c6-82e8-bda4eb8e51b7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427801521 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2427801521
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1181743810
Short name T918
Test name
Test status
Simulation time 253890681 ps
CPU time 3.47 seconds
Started Apr 23 01:44:56 PM PDT 24
Finished Apr 23 01:45:00 PM PDT 24
Peak memory 208976 kb
Host smart-c8e157a1-fc00-48c2-8f89-99f12a5e4dc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181743810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1181743810
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3997503612
Short name T957
Test name
Test status
Simulation time 1367879920 ps
CPU time 9.19 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:24 PM PDT 24
Peak memory 207832 kb
Host smart-82741e08-8040-4fcb-a656-bc0215e1c2d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997503612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3997503612
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3353815928
Short name T968
Test name
Test status
Simulation time 535955838 ps
CPU time 1.83 seconds
Started Apr 23 01:44:54 PM PDT 24
Finished Apr 23 01:44:57 PM PDT 24
Peak memory 210376 kb
Host smart-8dbc54e3-5fa5-4a12-8115-dff8ccc4e434
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353815928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3353815928
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1152743548
Short name T954
Test name
Test status
Simulation time 125662186 ps
CPU time 2.44 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 218456 kb
Host smart-1e875343-bb39-48c7-9a1c-f0a303e38f45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115274
3548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1152743548
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3622941592
Short name T951
Test name
Test status
Simulation time 72284912 ps
CPU time 1.46 seconds
Started Apr 23 01:44:59 PM PDT 24
Finished Apr 23 01:45:01 PM PDT 24
Peak memory 209148 kb
Host smart-3cbe3fb8-ef44-45ac-869a-0c0f1155bb37
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622941592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3622941592
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.471499679
Short name T986
Test name
Test status
Simulation time 23943148 ps
CPU time 1.02 seconds
Started Apr 23 01:44:57 PM PDT 24
Finished Apr 23 01:44:58 PM PDT 24
Peak memory 209084 kb
Host smart-b97f4a82-7014-4ae1-af53-966fd2fbcb46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471499679 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.471499679
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3713462500
Short name T196
Test name
Test status
Simulation time 54040462 ps
CPU time 1.01 seconds
Started Apr 23 01:44:55 PM PDT 24
Finished Apr 23 01:44:57 PM PDT 24
Peak memory 209252 kb
Host smart-9668e11c-17a5-4647-9b6e-1f9f21df50e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713462500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3713462500
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3293846216
Short name T898
Test name
Test status
Simulation time 108987428 ps
CPU time 2.71 seconds
Started Apr 23 01:44:55 PM PDT 24
Finished Apr 23 01:44:58 PM PDT 24
Peak memory 217488 kb
Host smart-72fcb5fc-20e4-4acb-85dd-0007419d7131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293846216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3293846216
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1001568171
Short name T973
Test name
Test status
Simulation time 123605340 ps
CPU time 1.96 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 221548 kb
Host smart-12466b17-a1e9-45ec-a3b6-4475cbe62833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001568171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1001568171
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4001579235
Short name T967
Test name
Test status
Simulation time 78874028 ps
CPU time 1.37 seconds
Started Apr 23 01:44:58 PM PDT 24
Finished Apr 23 01:45:01 PM PDT 24
Peak memory 217528 kb
Host smart-46dee31b-be72-402a-b67e-7bd3b3457e33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001579235 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4001579235
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2309037321
Short name T187
Test name
Test status
Simulation time 17545848 ps
CPU time 0.94 seconds
Started Apr 23 01:45:08 PM PDT 24
Finished Apr 23 01:45:10 PM PDT 24
Peak memory 217212 kb
Host smart-c4045673-7e48-401f-bfd9-51c368851862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309037321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2309037321
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2151707968
Short name T890
Test name
Test status
Simulation time 26203303 ps
CPU time 0.98 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 207752 kb
Host smart-75fff5fd-1927-4dd0-844b-82163298ecbb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151707968 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2151707968
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.101265339
Short name T909
Test name
Test status
Simulation time 7737017618 ps
CPU time 13.21 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:15 PM PDT 24
Peak memory 208540 kb
Host smart-92eebc82-da5e-41ba-a7d9-73bc646ce98e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101265339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.101265339
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1390161615
Short name T927
Test name
Test status
Simulation time 1084392524 ps
CPU time 19.64 seconds
Started Apr 23 01:44:59 PM PDT 24
Finished Apr 23 01:45:20 PM PDT 24
Peak memory 207856 kb
Host smart-4e542093-b785-4502-b7c4-743552ca40f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390161615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1390161615
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2017778314
Short name T994
Test name
Test status
Simulation time 851827488 ps
CPU time 1.41 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 210588 kb
Host smart-49cf1870-b6d6-4a78-a3cb-8b1f7613a348
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017778314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2017778314
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3063708145
Short name T934
Test name
Test status
Simulation time 433245554 ps
CPU time 1.8 seconds
Started Apr 23 01:45:11 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 218976 kb
Host smart-3be6cfc5-21e0-43d5-bd5e-185960314270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306370
8145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3063708145
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1097827822
Short name T995
Test name
Test status
Simulation time 73074434 ps
CPU time 1.35 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 209152 kb
Host smart-c9f7c137-643a-4f67-ad9e-d545d093cbba
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097827822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1097827822
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2510243194
Short name T102
Test name
Test status
Simulation time 69074693 ps
CPU time 1.44 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 209312 kb
Host smart-5f32a142-a863-4003-b763-584918b55a9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510243194 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2510243194
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3881584634
Short name T984
Test name
Test status
Simulation time 109231890 ps
CPU time 1.3 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:09 PM PDT 24
Peak memory 209232 kb
Host smart-308baa40-9be6-4367-8767-6fdd3d3d6cf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881584634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3881584634
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1057087682
Short name T943
Test name
Test status
Simulation time 98524177 ps
CPU time 2.78 seconds
Started Apr 23 01:44:58 PM PDT 24
Finished Apr 23 01:45:02 PM PDT 24
Peak memory 217600 kb
Host smart-4b3ecc7c-76e9-4d05-80bb-6cd228c2d3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057087682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1057087682
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2374632448
Short name T950
Test name
Test status
Simulation time 22247342 ps
CPU time 1.39 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 217608 kb
Host smart-17e39581-9932-4671-96aa-86aae47ff0be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374632448 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2374632448
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1501094368
Short name T961
Test name
Test status
Simulation time 54820843 ps
CPU time 0.91 seconds
Started Apr 23 01:44:58 PM PDT 24
Finished Apr 23 01:44:59 PM PDT 24
Peak memory 209192 kb
Host smart-7a094ecc-f275-43e5-8bb7-e8408dc5c9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501094368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1501094368
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1812373565
Short name T127
Test name
Test status
Simulation time 232021107 ps
CPU time 1.18 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 209132 kb
Host smart-83d60319-feed-4dbd-8fdb-21e2eed2d85b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812373565 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1812373565
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1920604899
Short name T996
Test name
Test status
Simulation time 1420585664 ps
CPU time 6.91 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 208984 kb
Host smart-87218ca9-ca29-4786-8ebd-71812445098b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920604899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1920604899
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2130101092
Short name T969
Test name
Test status
Simulation time 3725481832 ps
CPU time 6.77 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 208572 kb
Host smart-f3377067-38d1-43fc-bf1c-e7f75ad86a11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130101092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2130101092
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3945516535
Short name T920
Test name
Test status
Simulation time 305303242 ps
CPU time 1.95 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 210800 kb
Host smart-a5c3afca-4468-4c08-9644-ad39cf0f1f92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945516535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3945516535
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1475120224
Short name T941
Test name
Test status
Simulation time 114525783 ps
CPU time 2.02 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 217992 kb
Host smart-83cb9557-ca34-4b87-9529-ae85b98be3f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147512
0224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1475120224
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3503698840
Short name T915
Test name
Test status
Simulation time 489422942 ps
CPU time 1.44 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 208176 kb
Host smart-6f4130fd-af34-4194-8372-1c169b87b24f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503698840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3503698840
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1392762873
Short name T917
Test name
Test status
Simulation time 21786085 ps
CPU time 1.56 seconds
Started Apr 23 01:45:08 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 209132 kb
Host smart-8040e3d2-2b24-4e5b-bb42-cbba20c3f913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392762873 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1392762873
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1027305170
Short name T997
Test name
Test status
Simulation time 45921143 ps
CPU time 1.38 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 209176 kb
Host smart-106ab10a-fcd7-4837-bb08-02d5da1bdafa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027305170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1027305170
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2347376872
Short name T956
Test name
Test status
Simulation time 528469998 ps
CPU time 4.6 seconds
Started Apr 23 01:45:08 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 217548 kb
Host smart-e3ebad63-819e-43b3-8fcd-d5eea73c5ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347376872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2347376872
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2262617069
Short name T106
Test name
Test status
Simulation time 335827091 ps
CPU time 2.79 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 222368 kb
Host smart-d1246069-f979-41dd-b325-c1604ce088a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262617069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2262617069
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1309920307
Short name T148
Test name
Test status
Simulation time 20878634 ps
CPU time 1.66 seconds
Started Apr 23 01:45:10 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 221932 kb
Host smart-abbb0ded-4bde-4bfc-97d1-d7fb590de28a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309920307 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1309920307
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1605821725
Short name T184
Test name
Test status
Simulation time 41129554 ps
CPU time 0.89 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:04 PM PDT 24
Peak memory 209252 kb
Host smart-7099f461-bd61-4606-b402-189c8ee0b921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605821725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1605821725
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1716533941
Short name T883
Test name
Test status
Simulation time 391502877 ps
CPU time 2.1 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 208868 kb
Host smart-66971511-4406-490d-8831-8d7700fea1d6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716533941 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1716533941
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.931743261
Short name T893
Test name
Test status
Simulation time 467106445 ps
CPU time 4.37 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 208916 kb
Host smart-094f44ce-18c8-4a3b-8c35-e07ac8ca6d42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931743261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.931743261
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.919049438
Short name T980
Test name
Test status
Simulation time 1365818645 ps
CPU time 6.86 seconds
Started Apr 23 01:45:05 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 208212 kb
Host smart-73e7f80b-e578-4195-9ffb-a24a69f2b54a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919049438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.919049438
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1213005158
Short name T972
Test name
Test status
Simulation time 92461691 ps
CPU time 1.69 seconds
Started Apr 23 01:44:58 PM PDT 24
Finished Apr 23 01:45:01 PM PDT 24
Peak memory 210764 kb
Host smart-58b9af20-43c5-4900-b630-0ead72f5f482
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213005158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1213005158
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496267909
Short name T914
Test name
Test status
Simulation time 370712088 ps
CPU time 1.94 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 217836 kb
Host smart-916a0d31-4450-4fce-b8aa-4c0528460e13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349626
7909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496267909
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1291396235
Short name T987
Test name
Test status
Simulation time 116178999 ps
CPU time 3.26 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 209024 kb
Host smart-e88c7670-e6f1-45c4-8784-009a09cf8253
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291396235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1291396235
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2257465520
Short name T989
Test name
Test status
Simulation time 99200252 ps
CPU time 1.09 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:03 PM PDT 24
Peak memory 209380 kb
Host smart-c76d57ac-58fa-41b8-8aa2-9d4bf0dd0a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257465520 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2257465520
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3005350342
Short name T136
Test name
Test status
Simulation time 52756695 ps
CPU time 1.4 seconds
Started Apr 23 01:45:15 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 209172 kb
Host smart-782b39e5-e495-4249-8eb8-434c1125dbd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005350342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3005350342
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3335656131
Short name T940
Test name
Test status
Simulation time 300685409 ps
CPU time 3.35 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 217512 kb
Host smart-c974554f-edab-4151-ba6d-c43957c4e7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335656131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3335656131
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.178992667
Short name T98
Test name
Test status
Simulation time 76724587 ps
CPU time 1.81 seconds
Started Apr 23 01:45:03 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 217528 kb
Host smart-919ddd6f-7416-4122-894e-58dc2da6e772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178992667 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.178992667
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.484104907
Short name T185
Test name
Test status
Simulation time 14337758 ps
CPU time 0.84 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:06 PM PDT 24
Peak memory 209192 kb
Host smart-5fe11529-d27a-4787-b350-be98fa339c66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484104907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.484104907
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.36774912
Short name T948
Test name
Test status
Simulation time 418138651 ps
CPU time 1 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:09 PM PDT 24
Peak memory 209080 kb
Host smart-87dcb798-2d66-41e9-a03c-a9461359eff9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36774912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_alert_test.36774912
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3631969272
Short name T124
Test name
Test status
Simulation time 767717907 ps
CPU time 2.75 seconds
Started Apr 23 01:45:01 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 208440 kb
Host smart-dbd1aa7d-9323-47b0-acc3-dab3b7ddaaed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631969272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3631969272
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.851336713
Short name T953
Test name
Test status
Simulation time 3331827870 ps
CPU time 24.65 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:31 PM PDT 24
Peak memory 209220 kb
Host smart-41704cae-353a-40d2-a8e2-29decd17e2d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851336713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.851336713
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3288514794
Short name T975
Test name
Test status
Simulation time 397242890 ps
CPU time 2.88 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 210892 kb
Host smart-92f4a567-be19-4661-a1e9-fc486020c5bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288514794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3288514794
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.505542794
Short name T911
Test name
Test status
Simulation time 217245822 ps
CPU time 5.75 seconds
Started Apr 23 01:45:04 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 217776 kb
Host smart-03d7dc22-85b0-4f1b-bfd9-126b4c46273f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505542
794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.505542794
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4070298357
Short name T910
Test name
Test status
Simulation time 1170063767 ps
CPU time 1.59 seconds
Started Apr 23 01:45:10 PM PDT 24
Finished Apr 23 01:45:13 PM PDT 24
Peak memory 209084 kb
Host smart-7026450c-2567-477a-9547-cd6da6ac796d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070298357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.4070298357
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3261060247
Short name T937
Test name
Test status
Simulation time 32756242 ps
CPU time 1.53 seconds
Started Apr 23 01:45:02 PM PDT 24
Finished Apr 23 01:45:05 PM PDT 24
Peak memory 209256 kb
Host smart-935fc6f9-4ab9-49c7-8fbf-6dd3d9f6c202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261060247 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3261060247
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.470479854
Short name T104
Test name
Test status
Simulation time 74466978 ps
CPU time 1.31 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:09 PM PDT 24
Peak memory 211180 kb
Host smart-04089d4e-fa6d-4cd5-aee0-f2ecda9dbf8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470479854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.470479854
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2286353177
Short name T902
Test name
Test status
Simulation time 283239331 ps
CPU time 3.83 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 217564 kb
Host smart-c45d0379-746d-462f-aed1-81c51ea08562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286353177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2286353177
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3198807237
Short name T114
Test name
Test status
Simulation time 168691097 ps
CPU time 2.24 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:17 PM PDT 24
Peak memory 217424 kb
Host smart-1e83fa98-64ef-4008-9105-bdd0e3524d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198807237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3198807237
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2159371772
Short name T936
Test name
Test status
Simulation time 153767693 ps
CPU time 1.32 seconds
Started Apr 23 01:45:10 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 217696 kb
Host smart-dfea16b9-8d0f-422b-b5d8-537fd4ab62bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159371772 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2159371772
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4285106317
Short name T889
Test name
Test status
Simulation time 20027469 ps
CPU time 0.86 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 209184 kb
Host smart-cf2ac6a3-8994-4701-b800-b13182c07e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285106317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.4285106317
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.320069596
Short name T879
Test name
Test status
Simulation time 187499977 ps
CPU time 1.21 seconds
Started Apr 23 01:45:08 PM PDT 24
Finished Apr 23 01:45:11 PM PDT 24
Peak memory 207880 kb
Host smart-4c862bb9-07ee-4dbf-b785-8f7d29658f7e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320069596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.320069596
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2625779623
Short name T886
Test name
Test status
Simulation time 3745845555 ps
CPU time 2.57 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:10 PM PDT 24
Peak memory 208500 kb
Host smart-eea899d5-6a27-4159-a62c-0a1ba44d4934
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625779623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2625779623
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3187009045
Short name T979
Test name
Test status
Simulation time 476873708 ps
CPU time 7.48 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:14 PM PDT 24
Peak memory 208924 kb
Host smart-f7219c81-947b-4c88-97f3-16bc6b15dee6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187009045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3187009045
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.206348113
Short name T955
Test name
Test status
Simulation time 974254807 ps
CPU time 6.04 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:16 PM PDT 24
Peak memory 210868 kb
Host smart-fc097127-af19-4a45-b924-a4f87f9654f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206348113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.206348113
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2451351002
Short name T998
Test name
Test status
Simulation time 137283018 ps
CPU time 4.06 seconds
Started Apr 23 01:45:13 PM PDT 24
Finished Apr 23 01:45:18 PM PDT 24
Peak memory 217544 kb
Host smart-8b42482b-48ed-453b-8d57-9ca6364955a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245135
1002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2451351002
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3391466239
Short name T928
Test name
Test status
Simulation time 60084914 ps
CPU time 1.39 seconds
Started Apr 23 01:45:07 PM PDT 24
Finished Apr 23 01:45:10 PM PDT 24
Peak memory 209172 kb
Host smart-d936f7c4-dab9-49e8-981e-291db8550b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391466239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3391466239
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2147666405
Short name T919
Test name
Test status
Simulation time 52012678 ps
CPU time 1.05 seconds
Started Apr 23 01:45:06 PM PDT 24
Finished Apr 23 01:45:08 PM PDT 24
Peak memory 217400 kb
Host smart-9e1d1da4-1967-400b-b9c7-be8269bfb776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147666405 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2147666405
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3513802144
Short name T891
Test name
Test status
Simulation time 36960788 ps
CPU time 1.85 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:12 PM PDT 24
Peak memory 217520 kb
Host smart-2bc6c3d1-bb41-4d6b-bc5e-155f5e0425a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513802144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3513802144
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.726642363
Short name T971
Test name
Test status
Simulation time 524108478 ps
CPU time 5.2 seconds
Started Apr 23 01:45:09 PM PDT 24
Finished Apr 23 01:45:15 PM PDT 24
Peak memory 217320 kb
Host smart-b58603f4-436e-4c2d-b924-adf8e3756913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726642363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.726642363
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2571842637
Short name T276
Test name
Test status
Simulation time 29192172 ps
CPU time 1.19 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:46:51 PM PDT 24
Peak memory 209580 kb
Host smart-6573650c-c8d4-4343-9362-bda985a42a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571842637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2571842637
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3876322701
Short name T759
Test name
Test status
Simulation time 1297392058 ps
CPU time 13.57 seconds
Started Apr 23 02:46:46 PM PDT 24
Finished Apr 23 02:47:00 PM PDT 24
Peak memory 217972 kb
Host smart-6d0ced22-daf3-4ed8-bb7c-9500399d5f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876322701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3876322701
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.325417777
Short name T7
Test name
Test status
Simulation time 3326974036 ps
CPU time 14.5 seconds
Started Apr 23 02:46:48 PM PDT 24
Finished Apr 23 02:47:03 PM PDT 24
Peak memory 217776 kb
Host smart-bf7756a9-d435-4988-ac0c-4b5140bba4df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325417777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.325417777
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3595179431
Short name T588
Test name
Test status
Simulation time 8727656844 ps
CPU time 68.4 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:47:58 PM PDT 24
Peak memory 218808 kb
Host smart-937f8f96-6725-4d67-a275-68fb04305b8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595179431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3595179431
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1143781044
Short name T162
Test name
Test status
Simulation time 1134500904 ps
CPU time 4.65 seconds
Started Apr 23 02:46:50 PM PDT 24
Finished Apr 23 02:46:55 PM PDT 24
Peak memory 217332 kb
Host smart-c048fc93-47f4-4230-926c-adf869347688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143781044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
143781044
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.817193063
Short name T397
Test name
Test status
Simulation time 700587439 ps
CPU time 3.95 seconds
Started Apr 23 02:46:46 PM PDT 24
Finished Apr 23 02:46:51 PM PDT 24
Peak memory 217980 kb
Host smart-4e014c1f-aeab-4de7-a2b0-6887a8b6ffac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817193063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.817193063
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.398718075
Short name T64
Test name
Test status
Simulation time 713948914 ps
CPU time 21.06 seconds
Started Apr 23 02:46:47 PM PDT 24
Finished Apr 23 02:47:09 PM PDT 24
Peak memory 213256 kb
Host smart-280330f8-c1fc-46bb-911f-3fe047e3368b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398718075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.398718075
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1142581025
Short name T840
Test name
Test status
Simulation time 220128281 ps
CPU time 6.46 seconds
Started Apr 23 02:46:44 PM PDT 24
Finished Apr 23 02:46:51 PM PDT 24
Peak memory 213396 kb
Host smart-6b294b34-c3ba-4247-b4d4-52f670c9f33e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142581025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1142581025
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.13859990
Short name T350
Test name
Test status
Simulation time 2951813810 ps
CPU time 15.8 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:47:05 PM PDT 24
Peak memory 250724 kb
Host smart-8844d62a-0c89-491c-b7e8-f63a40ee7a60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13859990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_state_post_trans.13859990
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.292958713
Short name T869
Test name
Test status
Simulation time 173034821 ps
CPU time 2.24 seconds
Started Apr 23 02:46:46 PM PDT 24
Finished Apr 23 02:46:49 PM PDT 24
Peak memory 217964 kb
Host smart-5d8f75af-fb25-48d1-996b-b65d7481d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292958713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.292958713
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4037108869
Short name T805
Test name
Test status
Simulation time 201032253 ps
CPU time 5.99 seconds
Started Apr 23 02:46:47 PM PDT 24
Finished Apr 23 02:46:53 PM PDT 24
Peak memory 214176 kb
Host smart-98782b7c-9b08-4bae-ac76-3e8d83171c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037108869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4037108869
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3979471889
Short name T70
Test name
Test status
Simulation time 1168626130 ps
CPU time 23.59 seconds
Started Apr 23 02:46:51 PM PDT 24
Finished Apr 23 02:47:15 PM PDT 24
Peak memory 282228 kb
Host smart-10b66991-8983-42d0-ab53-c9c82b53c701
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979471889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3979471889
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3688810969
Short name T455
Test name
Test status
Simulation time 961688178 ps
CPU time 21.83 seconds
Started Apr 23 02:46:47 PM PDT 24
Finished Apr 23 02:47:09 PM PDT 24
Peak memory 226104 kb
Host smart-3ef17e65-b9e8-45f9-ae92-b46e24e242fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688810969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3688810969
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1227732267
Short name T247
Test name
Test status
Simulation time 1332461352 ps
CPU time 14.69 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:47:05 PM PDT 24
Peak memory 217888 kb
Host smart-8f770a9b-1060-4ace-b7c1-ee690ef9d979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227732267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1227732267
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3904071230
Short name T462
Test name
Test status
Simulation time 1211372803 ps
CPU time 12.22 seconds
Started Apr 23 02:46:48 PM PDT 24
Finished Apr 23 02:47:01 PM PDT 24
Peak memory 218012 kb
Host smart-f1a81431-1e4c-4ea9-b268-168ac0f1b786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904071230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
904071230
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.602170473
Short name T626
Test name
Test status
Simulation time 545592986 ps
CPU time 11.92 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:47:02 PM PDT 24
Peak memory 217984 kb
Host smart-fb3e7d26-21ec-45d4-9d20-51147257eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602170473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.602170473
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1329060084
Short name T485
Test name
Test status
Simulation time 31450575 ps
CPU time 1.67 seconds
Started Apr 23 02:46:48 PM PDT 24
Finished Apr 23 02:46:50 PM PDT 24
Peak memory 213500 kb
Host smart-1a3d9591-5fa8-4f59-a3a2-d0293d53ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329060084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1329060084
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3278290267
Short name T330
Test name
Test status
Simulation time 261676283 ps
CPU time 6.84 seconds
Started Apr 23 02:46:46 PM PDT 24
Finished Apr 23 02:46:53 PM PDT 24
Peak memory 250944 kb
Host smart-14369e75-91b4-4102-a728-e4c53e33891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278290267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3278290267
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1237285216
Short name T176
Test name
Test status
Simulation time 3108490549 ps
CPU time 54.3 seconds
Started Apr 23 02:46:51 PM PDT 24
Finished Apr 23 02:47:46 PM PDT 24
Peak memory 251096 kb
Host smart-e73e1910-6cbc-4420-b787-49de08786541
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237285216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1237285216
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.23617995
Short name T497
Test name
Test status
Simulation time 42882242 ps
CPU time 0.88 seconds
Started Apr 23 02:46:44 PM PDT 24
Finished Apr 23 02:46:46 PM PDT 24
Peak memory 211752 kb
Host smart-957d154b-93b7-4605-aa7e-d0f879852a7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23617995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_volatile_unlock_smoke.23617995
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3947465170
Short name T566
Test name
Test status
Simulation time 25548110 ps
CPU time 0.94 seconds
Started Apr 23 02:46:57 PM PDT 24
Finished Apr 23 02:46:59 PM PDT 24
Peak memory 209584 kb
Host smart-5524119e-002c-4b9a-a6c8-ed960f3d7a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947465170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3947465170
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2015403378
Short name T336
Test name
Test status
Simulation time 560694499 ps
CPU time 10.81 seconds
Started Apr 23 02:46:50 PM PDT 24
Finished Apr 23 02:47:01 PM PDT 24
Peak memory 218000 kb
Host smart-7e96e2a4-72bc-4808-ab4b-91691449d516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015403378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2015403378
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2000084590
Short name T360
Test name
Test status
Simulation time 15178876162 ps
CPU time 33.68 seconds
Started Apr 23 02:46:54 PM PDT 24
Finished Apr 23 02:47:28 PM PDT 24
Peak memory 219016 kb
Host smart-0874e9fa-2d0f-46f9-ae72-913730242106
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000084590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2000084590
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2033838022
Short name T257
Test name
Test status
Simulation time 5575590780 ps
CPU time 13.36 seconds
Started Apr 23 02:46:51 PM PDT 24
Finished Apr 23 02:47:05 PM PDT 24
Peak memory 217856 kb
Host smart-2b5d6c9d-c146-4dc1-a9c8-17bf71a8a50d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033838022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
033838022
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.620671662
Short name T384
Test name
Test status
Simulation time 549496179 ps
CPU time 15.15 seconds
Started Apr 23 02:46:52 PM PDT 24
Finished Apr 23 02:47:07 PM PDT 24
Peak memory 218032 kb
Host smart-0b332e72-6bc4-45fa-b47c-d709f8257be2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620671662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.620671662
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1078490648
Short name T13
Test name
Test status
Simulation time 1817932905 ps
CPU time 17.93 seconds
Started Apr 23 02:46:54 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 213304 kb
Host smart-920346f9-deae-4fee-93f3-9b87f0e3850d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078490648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1078490648
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4089336613
Short name T53
Test name
Test status
Simulation time 546372833 ps
CPU time 3.07 seconds
Started Apr 23 02:46:53 PM PDT 24
Finished Apr 23 02:46:57 PM PDT 24
Peak memory 213436 kb
Host smart-8fcb4f48-7bff-4349-985a-998c07e78e79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089336613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
4089336613
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.590934818
Short name T507
Test name
Test status
Simulation time 4955363444 ps
CPU time 33.86 seconds
Started Apr 23 02:46:53 PM PDT 24
Finished Apr 23 02:47:28 PM PDT 24
Peak memory 267484 kb
Host smart-dfb54ba3-8e62-467e-837e-9c24b6030c47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590934818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.590934818
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1760652526
Short name T829
Test name
Test status
Simulation time 1182036614 ps
CPU time 11.04 seconds
Started Apr 23 02:46:53 PM PDT 24
Finished Apr 23 02:47:05 PM PDT 24
Peak memory 218008 kb
Host smart-dfd0920b-fd00-4de7-b4e4-78830b4dfc4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760652526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1760652526
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3902769954
Short name T260
Test name
Test status
Simulation time 173053453 ps
CPU time 2.57 seconds
Started Apr 23 02:46:50 PM PDT 24
Finished Apr 23 02:46:53 PM PDT 24
Peak memory 218032 kb
Host smart-f7b5fbbf-3a44-489e-8d25-ee0c954288f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902769954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3902769954
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1347465668
Short name T797
Test name
Test status
Simulation time 868309892 ps
CPU time 11.59 seconds
Started Apr 23 02:46:50 PM PDT 24
Finished Apr 23 02:47:02 PM PDT 24
Peak memory 213648 kb
Host smart-23ad979d-3f72-43e8-bbc8-c5db1c920c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347465668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1347465668
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1163475313
Short name T848
Test name
Test status
Simulation time 372003085 ps
CPU time 12.18 seconds
Started Apr 23 02:46:54 PM PDT 24
Finished Apr 23 02:47:06 PM PDT 24
Peak memory 226164 kb
Host smart-7e3c1dfc-e277-4155-ab18-0f548236c7ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163475313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1163475313
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1675520561
Short name T474
Test name
Test status
Simulation time 309865059 ps
CPU time 8.68 seconds
Started Apr 23 02:46:53 PM PDT 24
Finished Apr 23 02:47:02 PM PDT 24
Peak memory 217944 kb
Host smart-8c6aa6a7-31f2-4fa3-8dc5-3864c99a50ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675520561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1675520561
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2876217822
Short name T559
Test name
Test status
Simulation time 360950188 ps
CPU time 14.26 seconds
Started Apr 23 02:46:54 PM PDT 24
Finished Apr 23 02:47:09 PM PDT 24
Peak memory 218060 kb
Host smart-d90fa6a0-6a93-4c95-8714-94f0e56d3cf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876217822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
876217822
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2955117494
Short name T340
Test name
Test status
Simulation time 245404820 ps
CPU time 2.46 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:46:52 PM PDT 24
Peak memory 214384 kb
Host smart-7531956a-6d58-49dd-b78d-137f3df69ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955117494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2955117494
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2160115355
Short name T843
Test name
Test status
Simulation time 912588244 ps
CPU time 28.43 seconds
Started Apr 23 02:46:51 PM PDT 24
Finished Apr 23 02:47:20 PM PDT 24
Peak memory 247008 kb
Host smart-53dc7245-174a-4e49-8991-e2a9125d3559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160115355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2160115355
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2137714423
Short name T714
Test name
Test status
Simulation time 190540036 ps
CPU time 3.36 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:46:53 PM PDT 24
Peak memory 221960 kb
Host smart-f5dc5f3d-4492-417f-be9d-39c1c5ca97b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137714423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2137714423
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3519758383
Short name T481
Test name
Test status
Simulation time 1945794509 ps
CPU time 78 seconds
Started Apr 23 02:46:53 PM PDT 24
Finished Apr 23 02:48:12 PM PDT 24
Peak memory 250348 kb
Host smart-0bdc8479-68a5-4a89-b894-b5d89b6c7d04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519758383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3519758383
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3827270127
Short name T393
Test name
Test status
Simulation time 24752275 ps
CPU time 1.01 seconds
Started Apr 23 02:46:50 PM PDT 24
Finished Apr 23 02:46:52 PM PDT 24
Peak memory 211568 kb
Host smart-21358cf4-e48c-4f36-a9ca-d95df6753d87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827270127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3827270127
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2894395293
Short name T297
Test name
Test status
Simulation time 16388479 ps
CPU time 0.97 seconds
Started Apr 23 02:47:46 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 209512 kb
Host smart-7ad24800-658e-4adb-9a8a-086dc51a96b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894395293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2894395293
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.520788491
Short name T751
Test name
Test status
Simulation time 201493528 ps
CPU time 10.52 seconds
Started Apr 23 02:47:39 PM PDT 24
Finished Apr 23 02:47:50 PM PDT 24
Peak memory 217980 kb
Host smart-94337139-11f2-459f-b50e-0131f1b19462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520788491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.520788491
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3256971614
Short name T5
Test name
Test status
Simulation time 2007868539 ps
CPU time 12.08 seconds
Started Apr 23 02:47:42 PM PDT 24
Finished Apr 23 02:47:54 PM PDT 24
Peak memory 209596 kb
Host smart-6b0ad055-f9a8-435e-9515-39ff67962aea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256971614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3256971614
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1186907187
Short name T81
Test name
Test status
Simulation time 7507624461 ps
CPU time 35 seconds
Started Apr 23 02:47:45 PM PDT 24
Finished Apr 23 02:48:20 PM PDT 24
Peak memory 218980 kb
Host smart-0f2b1b16-0296-4fd7-a68b-92d112bc6212
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186907187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1186907187
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.237604548
Short name T577
Test name
Test status
Simulation time 946312871 ps
CPU time 4.84 seconds
Started Apr 23 02:47:42 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 218032 kb
Host smart-f612783f-ed0f-4fb0-a119-2e01836c4d25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237604548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.237604548
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4120725605
Short name T52
Test name
Test status
Simulation time 622881491 ps
CPU time 15.01 seconds
Started Apr 23 02:47:42 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 213764 kb
Host smart-26b1d091-b531-4f73-9728-21029463df1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120725605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.4120725605
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2079137729
Short name T310
Test name
Test status
Simulation time 2218689940 ps
CPU time 30.52 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:48:20 PM PDT 24
Peak memory 251284 kb
Host smart-c05f466a-1bec-4a90-ae73-807930603ddf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079137729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2079137729
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1819073229
Short name T613
Test name
Test status
Simulation time 558697107 ps
CPU time 12.46 seconds
Started Apr 23 02:47:43 PM PDT 24
Finished Apr 23 02:47:56 PM PDT 24
Peak memory 224088 kb
Host smart-738c20c3-18c2-4b9a-a479-564945e92af0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819073229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1819073229
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.110579144
Short name T228
Test name
Test status
Simulation time 308885057 ps
CPU time 3.78 seconds
Started Apr 23 02:47:37 PM PDT 24
Finished Apr 23 02:47:41 PM PDT 24
Peak memory 218016 kb
Host smart-565f638b-e68e-4274-a32d-2dbb57bd79a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110579144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.110579144
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1514875851
Short name T620
Test name
Test status
Simulation time 3056633270 ps
CPU time 15.82 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:48:06 PM PDT 24
Peak memory 219092 kb
Host smart-50cef57a-a5f6-43c9-b060-b11b03dfa555
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514875851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1514875851
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1532479510
Short name T159
Test name
Test status
Simulation time 4728284834 ps
CPU time 11.63 seconds
Started Apr 23 02:47:43 PM PDT 24
Finished Apr 23 02:47:55 PM PDT 24
Peak memory 218080 kb
Host smart-25e0b93e-69f0-4072-89b3-9db1b9ef61eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532479510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1532479510
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1026202296
Short name T382
Test name
Test status
Simulation time 505902690 ps
CPU time 14.87 seconds
Started Apr 23 02:47:41 PM PDT 24
Finished Apr 23 02:47:56 PM PDT 24
Peak memory 217968 kb
Host smart-da8c4d6c-f198-496a-95d7-dc571def5dcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026202296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1026202296
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4182511251
Short name T513
Test name
Test status
Simulation time 685659959 ps
CPU time 12.82 seconds
Started Apr 23 02:47:39 PM PDT 24
Finished Apr 23 02:47:52 PM PDT 24
Peak memory 218036 kb
Host smart-fa085cdb-a587-48a6-a71b-126af5c78c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182511251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4182511251
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3586891155
Short name T813
Test name
Test status
Simulation time 203630893 ps
CPU time 1.73 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:47:40 PM PDT 24
Peak memory 213784 kb
Host smart-7905cd3e-b529-47a3-8972-78342e2d9230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586891155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3586891155
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1699567716
Short name T764
Test name
Test status
Simulation time 349973426 ps
CPU time 17.53 seconds
Started Apr 23 02:47:39 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 251004 kb
Host smart-c7c89367-2bcd-40a8-a01b-fbc06e1a60ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699567716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1699567716
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1029598242
Short name T498
Test name
Test status
Simulation time 307084127 ps
CPU time 7.18 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:47:46 PM PDT 24
Peak memory 246824 kb
Host smart-7faf20e0-fe53-4730-b064-e9552ec62981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029598242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1029598242
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2183183958
Short name T278
Test name
Test status
Simulation time 72175387910 ps
CPU time 510.11 seconds
Started Apr 23 02:47:42 PM PDT 24
Finished Apr 23 02:56:13 PM PDT 24
Peak memory 224976 kb
Host smart-8fe05960-a448-48b1-b558-39dbc98c66e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183183958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2183183958
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3334205645
Short name T132
Test name
Test status
Simulation time 18760308153 ps
CPU time 319.79 seconds
Started Apr 23 02:47:43 PM PDT 24
Finished Apr 23 02:53:03 PM PDT 24
Peak memory 267516 kb
Host smart-33819bbd-fbc0-4b8d-b5f0-bb6569ddcb23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3334205645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3334205645
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2593993041
Short name T702
Test name
Test status
Simulation time 26189126 ps
CPU time 0.86 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:47:40 PM PDT 24
Peak memory 211584 kb
Host smart-b2ef9726-dcab-4ec2-969c-85d738962a78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593993041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2593993041
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.817453489
Short name T683
Test name
Test status
Simulation time 34231130 ps
CPU time 1.07 seconds
Started Apr 23 02:47:45 PM PDT 24
Finished Apr 23 02:47:46 PM PDT 24
Peak memory 209560 kb
Host smart-750c98d7-a68e-457d-bde0-1fafe3ba8396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817453489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.817453489
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3331828568
Short name T402
Test name
Test status
Simulation time 251139911 ps
CPU time 8.5 seconds
Started Apr 23 02:47:45 PM PDT 24
Finished Apr 23 02:47:54 PM PDT 24
Peak memory 217964 kb
Host smart-ced6850b-4371-4a1d-a8a1-522ffff1e0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331828568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3331828568
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.4150275671
Short name T26
Test name
Test status
Simulation time 898618362 ps
CPU time 3.27 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:47:52 PM PDT 24
Peak memory 209560 kb
Host smart-e49bfa1f-0883-4b10-b7c6-384eb0c6bd3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150275671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.4150275671
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2196195475
Short name T583
Test name
Test status
Simulation time 52135393 ps
CPU time 1.88 seconds
Started Apr 23 02:47:45 PM PDT 24
Finished Apr 23 02:47:48 PM PDT 24
Peak memory 217968 kb
Host smart-985d55d1-5f6d-499c-9e90-18c7938b0027
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196195475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2196195475
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3438416219
Short name T287
Test name
Test status
Simulation time 6293474652 ps
CPU time 9.91 seconds
Started Apr 23 02:47:47 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 214180 kb
Host smart-7f8b744e-dc26-40f8-99b1-054bd6d8e1c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438416219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3438416219
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3694255827
Short name T743
Test name
Test status
Simulation time 2201524405 ps
CPU time 59.32 seconds
Started Apr 23 02:47:46 PM PDT 24
Finished Apr 23 02:48:46 PM PDT 24
Peak memory 276736 kb
Host smart-5b6f439b-e059-4ab8-ad68-1064b653b5a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694255827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3694255827
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.963170431
Short name T87
Test name
Test status
Simulation time 926572070 ps
CPU time 31.47 seconds
Started Apr 23 02:47:47 PM PDT 24
Finished Apr 23 02:48:19 PM PDT 24
Peak memory 251028 kb
Host smart-3f5e2524-27ac-4eef-9fac-91a9f1e98234
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963170431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.963170431
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2267137457
Short name T341
Test name
Test status
Simulation time 159124812 ps
CPU time 3.97 seconds
Started Apr 23 02:47:43 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 218012 kb
Host smart-0f1aaf7a-ced3-406c-9377-b443d115d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267137457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2267137457
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2042898511
Short name T769
Test name
Test status
Simulation time 369700846 ps
CPU time 11.57 seconds
Started Apr 23 02:47:48 PM PDT 24
Finished Apr 23 02:48:00 PM PDT 24
Peak memory 226048 kb
Host smart-dbd40b99-b13d-4a92-b8d3-2804f4fa941e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042898511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2042898511
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3312094156
Short name T210
Test name
Test status
Simulation time 864980283 ps
CPU time 12.49 seconds
Started Apr 23 02:47:50 PM PDT 24
Finished Apr 23 02:48:03 PM PDT 24
Peak memory 217992 kb
Host smart-a5bb2e12-f15d-4f68-a3c4-f56034a784ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312094156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3312094156
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.548585585
Short name T667
Test name
Test status
Simulation time 4909137969 ps
CPU time 9.75 seconds
Started Apr 23 02:47:47 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 218036 kb
Host smart-d4686baa-aa0d-439b-a231-c5ebdf88b419
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548585585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.548585585
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.21164109
Short name T518
Test name
Test status
Simulation time 1397538045 ps
CPU time 11.92 seconds
Started Apr 23 02:47:48 PM PDT 24
Finished Apr 23 02:48:00 PM PDT 24
Peak memory 218028 kb
Host smart-c6da2d32-d949-4e80-9c61-b28f0077ed2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21164109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.21164109
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3394452676
Short name T593
Test name
Test status
Simulation time 121012702 ps
CPU time 5.11 seconds
Started Apr 23 02:47:42 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 217756 kb
Host smart-9a0d1491-b1b8-4028-af46-8eb3100eeb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394452676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3394452676
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3602563063
Short name T322
Test name
Test status
Simulation time 262592849 ps
CPU time 24.52 seconds
Started Apr 23 02:47:42 PM PDT 24
Finished Apr 23 02:48:07 PM PDT 24
Peak memory 251124 kb
Host smart-f8461f08-111b-4564-b0ba-c9041939270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602563063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3602563063
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3587533660
Short name T629
Test name
Test status
Simulation time 251583120 ps
CPU time 6.91 seconds
Started Apr 23 02:47:42 PM PDT 24
Finished Apr 23 02:47:49 PM PDT 24
Peak memory 250756 kb
Host smart-8f80c789-7c40-4474-ab4e-9235e14c29a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587533660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3587533660
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4058315697
Short name T531
Test name
Test status
Simulation time 3298717330 ps
CPU time 93.39 seconds
Started Apr 23 02:47:50 PM PDT 24
Finished Apr 23 02:49:24 PM PDT 24
Peak memory 252124 kb
Host smart-66e79850-2b9c-4d45-986b-7a5d567f23e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058315697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4058315697
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3445854004
Short name T131
Test name
Test status
Simulation time 13473865965 ps
CPU time 337.16 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 275740 kb
Host smart-f6068daa-288a-444c-88e8-af6042f1b62b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3445854004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3445854004
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3515423848
Short name T246
Test name
Test status
Simulation time 17671247 ps
CPU time 0.89 seconds
Started Apr 23 02:47:43 PM PDT 24
Finished Apr 23 02:47:44 PM PDT 24
Peak memory 211620 kb
Host smart-94fe7fae-b29a-44c9-b66f-204a7b0d07c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515423848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3515423848
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2352946396
Short name T355
Test name
Test status
Simulation time 484654086 ps
CPU time 1.13 seconds
Started Apr 23 02:47:54 PM PDT 24
Finished Apr 23 02:47:56 PM PDT 24
Peak memory 209576 kb
Host smart-c1862d85-8e31-4116-9678-de4998509e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352946396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2352946396
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.632276399
Short name T303
Test name
Test status
Simulation time 2338061943 ps
CPU time 13.28 seconds
Started Apr 23 02:47:50 PM PDT 24
Finished Apr 23 02:48:03 PM PDT 24
Peak memory 218008 kb
Host smart-dbba3e43-9dc6-42d2-95e5-244bee028163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632276399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.632276399
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3146946352
Short name T527
Test name
Test status
Simulation time 502660699 ps
CPU time 3.75 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:47:53 PM PDT 24
Peak memory 209628 kb
Host smart-405782f1-0b4c-4ecb-a3ef-1e96c2aaf755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146946352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3146946352
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2126193345
Short name T766
Test name
Test status
Simulation time 3809549964 ps
CPU time 33.09 seconds
Started Apr 23 02:47:51 PM PDT 24
Finished Apr 23 02:48:24 PM PDT 24
Peak memory 218580 kb
Host smart-1f50e655-68f4-4ccf-8058-432112a8d534
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126193345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2126193345
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1559909216
Short name T212
Test name
Test status
Simulation time 1722672672 ps
CPU time 13.8 seconds
Started Apr 23 02:47:48 PM PDT 24
Finished Apr 23 02:48:02 PM PDT 24
Peak memory 217976 kb
Host smart-87781a29-5cab-49e9-bc3a-049fbf91ba4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559909216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1559909216
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2786417516
Short name T536
Test name
Test status
Simulation time 502620560 ps
CPU time 4.34 seconds
Started Apr 23 02:47:48 PM PDT 24
Finished Apr 23 02:47:53 PM PDT 24
Peak memory 213572 kb
Host smart-3a960bd5-562c-46e8-8f87-b87859211381
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786417516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2786417516
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.228969850
Short name T456
Test name
Test status
Simulation time 2370185179 ps
CPU time 39.78 seconds
Started Apr 23 02:47:48 PM PDT 24
Finished Apr 23 02:48:28 PM PDT 24
Peak memory 283840 kb
Host smart-3c047039-9f31-4104-ad84-5c71954f13ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228969850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.228969850
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1526661934
Short name T554
Test name
Test status
Simulation time 2911640144 ps
CPU time 15.31 seconds
Started Apr 23 02:47:51 PM PDT 24
Finished Apr 23 02:48:07 PM PDT 24
Peak memory 251048 kb
Host smart-2e5ec8b3-201b-42fc-a639-e695d0f0616a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526661934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1526661934
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2180198102
Short name T637
Test name
Test status
Simulation time 97591166 ps
CPU time 3.2 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:47:52 PM PDT 24
Peak memory 217960 kb
Host smart-37edc4f2-7765-4fec-aa54-b69e15586271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180198102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2180198102
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.670951989
Short name T475
Test name
Test status
Simulation time 397057769 ps
CPU time 13.69 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:48:03 PM PDT 24
Peak memory 226080 kb
Host smart-279f2a13-d5e7-4a0d-89a5-27109fe5f6e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670951989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.670951989
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3897464574
Short name T762
Test name
Test status
Simulation time 406946312 ps
CPU time 11.91 seconds
Started Apr 23 02:47:56 PM PDT 24
Finished Apr 23 02:48:09 PM PDT 24
Peak memory 217996 kb
Host smart-4f4150fd-ae4a-4ccc-a94a-9a36e2c279b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897464574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3897464574
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.811199986
Short name T794
Test name
Test status
Simulation time 601058008 ps
CPU time 7.36 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 218040 kb
Host smart-f98ab41a-6835-485f-9ae5-8c934e2ae661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811199986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.811199986
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.111045912
Short name T777
Test name
Test status
Simulation time 246876547 ps
CPU time 9.86 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:48:00 PM PDT 24
Peak memory 218012 kb
Host smart-47db8aa9-9853-4d32-afd8-a1bf92892d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111045912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.111045912
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2565570256
Short name T562
Test name
Test status
Simulation time 172035664 ps
CPU time 2.78 seconds
Started Apr 23 02:47:46 PM PDT 24
Finished Apr 23 02:47:49 PM PDT 24
Peak memory 217940 kb
Host smart-686edcf6-1660-4491-8fd8-134f4410d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565570256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2565570256
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1905810716
Short name T448
Test name
Test status
Simulation time 467146693 ps
CPU time 24.1 seconds
Started Apr 23 02:47:49 PM PDT 24
Finished Apr 23 02:48:13 PM PDT 24
Peak memory 251084 kb
Host smart-5f0076c6-acfa-45c0-ab31-fc4065800945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905810716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1905810716
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1901011011
Short name T165
Test name
Test status
Simulation time 149874110 ps
CPU time 6.96 seconds
Started Apr 23 02:47:48 PM PDT 24
Finished Apr 23 02:47:55 PM PDT 24
Peak memory 251036 kb
Host smart-21ace8c8-3952-4f19-bcca-10b6c198df45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901011011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1901011011
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2742988321
Short name T231
Test name
Test status
Simulation time 12529781888 ps
CPU time 47.72 seconds
Started Apr 23 02:47:56 PM PDT 24
Finished Apr 23 02:48:44 PM PDT 24
Peak memory 226164 kb
Host smart-3ac164d9-6520-4fee-a0b4-3e0e0ca86b0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742988321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2742988321
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1491172726
Short name T801
Test name
Test status
Simulation time 862519244 ps
CPU time 9.69 seconds
Started Apr 23 02:47:54 PM PDT 24
Finished Apr 23 02:48:04 PM PDT 24
Peak memory 217988 kb
Host smart-85898df0-d3d6-465e-abfe-feb206be61f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491172726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1491172726
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3520329179
Short name T29
Test name
Test status
Simulation time 1789751073 ps
CPU time 5.04 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:48:02 PM PDT 24
Peak memory 217008 kb
Host smart-267547c2-780c-480e-b244-dd70b4bda18b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520329179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3520329179
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.396545040
Short name T621
Test name
Test status
Simulation time 11622348325 ps
CPU time 62.8 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:49:01 PM PDT 24
Peak memory 218988 kb
Host smart-523228ab-6d74-4bf3-a00c-534780f8e769
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396545040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.396545040
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2764976327
Short name T398
Test name
Test status
Simulation time 144902615 ps
CPU time 2.95 seconds
Started Apr 23 02:47:54 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 218048 kb
Host smart-e0350c31-1c44-4f44-84de-1f79bfa919c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764976327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2764976327
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3694241889
Short name T345
Test name
Test status
Simulation time 94954425 ps
CPU time 1.85 seconds
Started Apr 23 02:47:51 PM PDT 24
Finished Apr 23 02:47:53 PM PDT 24
Peak memory 212972 kb
Host smart-b13a6a4b-3d13-4f2e-af2b-a241752adf1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694241889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3694241889
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1265382187
Short name T331
Test name
Test status
Simulation time 1656234437 ps
CPU time 59.6 seconds
Started Apr 23 02:47:53 PM PDT 24
Finished Apr 23 02:48:53 PM PDT 24
Peak memory 256048 kb
Host smart-90e16e55-67f2-4a9c-849b-f2ec72c91ae5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265382187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1265382187
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.980524056
Short name T144
Test name
Test status
Simulation time 522009801 ps
CPU time 12.18 seconds
Started Apr 23 02:47:56 PM PDT 24
Finished Apr 23 02:48:09 PM PDT 24
Peak memory 250492 kb
Host smart-ad09aa0e-adc2-43c1-a7c8-d4dc50b2b7c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980524056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.980524056
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1665254916
Short name T387
Test name
Test status
Simulation time 286627291 ps
CPU time 1.91 seconds
Started Apr 23 02:47:59 PM PDT 24
Finished Apr 23 02:48:02 PM PDT 24
Peak memory 217936 kb
Host smart-edaec2bd-9059-4194-8a65-c7900eb1e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665254916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1665254916
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3373734407
Short name T487
Test name
Test status
Simulation time 396281874 ps
CPU time 8.43 seconds
Started Apr 23 02:47:54 PM PDT 24
Finished Apr 23 02:48:03 PM PDT 24
Peak memory 218488 kb
Host smart-113c6c97-f22a-4ec7-b615-271378844637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373734407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3373734407
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2349688622
Short name T272
Test name
Test status
Simulation time 1151938462 ps
CPU time 9.04 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:48:06 PM PDT 24
Peak memory 218060 kb
Host smart-07f8a1b7-2082-4cc5-9759-4b61c39bad69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349688622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2349688622
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1095813703
Short name T594
Test name
Test status
Simulation time 512391272 ps
CPU time 7.25 seconds
Started Apr 23 02:47:56 PM PDT 24
Finished Apr 23 02:48:03 PM PDT 24
Peak memory 218012 kb
Host smart-892889f6-7963-43e1-be77-1ece0bb78c0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095813703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1095813703
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1395205872
Short name T41
Test name
Test status
Simulation time 269244308 ps
CPU time 7.22 seconds
Started Apr 23 02:47:52 PM PDT 24
Finished Apr 23 02:48:00 PM PDT 24
Peak memory 218120 kb
Host smart-f3ce3a83-eebd-4b34-869e-84c12fe59d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395205872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1395205872
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2874533045
Short name T785
Test name
Test status
Simulation time 44265236 ps
CPU time 0.94 seconds
Started Apr 23 02:47:51 PM PDT 24
Finished Apr 23 02:47:52 PM PDT 24
Peak memory 217920 kb
Host smart-1d5b606b-f1df-412e-bbe3-0bf481d267f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874533045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2874533045
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2813279266
Short name T639
Test name
Test status
Simulation time 933800326 ps
CPU time 34.66 seconds
Started Apr 23 02:47:59 PM PDT 24
Finished Apr 23 02:48:34 PM PDT 24
Peak memory 251040 kb
Host smart-78be274f-4e2e-4c9d-8505-71ebff45752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813279266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2813279266
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.135630130
Short name T501
Test name
Test status
Simulation time 75068838 ps
CPU time 6.48 seconds
Started Apr 23 02:47:54 PM PDT 24
Finished Apr 23 02:48:01 PM PDT 24
Peak memory 247072 kb
Host smart-39fd6e0b-67d5-45d2-8105-58fdaa7fb8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135630130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.135630130
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3490583986
Short name T504
Test name
Test status
Simulation time 14762868259 ps
CPU time 386.38 seconds
Started Apr 23 02:47:55 PM PDT 24
Finished Apr 23 02:54:22 PM PDT 24
Peak memory 222796 kb
Host smart-31ec8499-6d54-4292-b3c2-45794f558773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490583986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3490583986
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.946132684
Short name T167
Test name
Test status
Simulation time 15665846145 ps
CPU time 535.53 seconds
Started Apr 23 02:47:56 PM PDT 24
Finished Apr 23 02:56:53 PM PDT 24
Peak memory 308744 kb
Host smart-944a3a51-1900-4b9a-9f04-f8049b9e4428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=946132684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.946132684
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4102458536
Short name T420
Test name
Test status
Simulation time 33883903 ps
CPU time 0.96 seconds
Started Apr 23 02:47:53 PM PDT 24
Finished Apr 23 02:47:54 PM PDT 24
Peak memory 212752 kb
Host smart-50024991-9848-4f04-9ca5-e597e8817447
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102458536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.4102458536
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1013872952
Short name T596
Test name
Test status
Simulation time 51273179 ps
CPU time 1.01 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:47:59 PM PDT 24
Peak memory 209560 kb
Host smart-5d1b6236-dc53-474c-9127-bbfff9c2451e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013872952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1013872952
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.83851274
Short name T635
Test name
Test status
Simulation time 2536214709 ps
CPU time 18.21 seconds
Started Apr 23 02:47:55 PM PDT 24
Finished Apr 23 02:48:14 PM PDT 24
Peak memory 217984 kb
Host smart-0dec0750-13d0-41b6-bf06-e654c60863e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83851274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.83851274
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2845193805
Short name T686
Test name
Test status
Simulation time 10574553736 ps
CPU time 12.77 seconds
Started Apr 23 02:47:59 PM PDT 24
Finished Apr 23 02:48:13 PM PDT 24
Peak memory 217580 kb
Host smart-8c5427ba-5b34-4abf-9efa-84d1c3f0280f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845193805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2845193805
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1669635249
Short name T651
Test name
Test status
Simulation time 33683793944 ps
CPU time 36.17 seconds
Started Apr 23 02:47:59 PM PDT 24
Finished Apr 23 02:48:36 PM PDT 24
Peak memory 218048 kb
Host smart-bb159d5a-1d56-4ffc-9829-61d56210f3ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669635249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1669635249
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1864100224
Short name T364
Test name
Test status
Simulation time 54609496 ps
CPU time 2.59 seconds
Started Apr 23 02:47:58 PM PDT 24
Finished Apr 23 02:48:01 PM PDT 24
Peak memory 217960 kb
Host smart-5808cf08-39bd-4fc3-b127-8b2ebbfd47db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864100224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1864100224
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.555026229
Short name T802
Test name
Test status
Simulation time 361092511 ps
CPU time 7.52 seconds
Started Apr 23 02:47:58 PM PDT 24
Finished Apr 23 02:48:06 PM PDT 24
Peak memory 213844 kb
Host smart-748a8bc8-f0aa-4940-abc4-bc9b94cc73a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555026229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
555026229
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3147134324
Short name T441
Test name
Test status
Simulation time 17176997833 ps
CPU time 66.66 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 283020 kb
Host smart-411e730b-68a3-4c41-8cf0-0b81dea1afd4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147134324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3147134324
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1454077130
Short name T463
Test name
Test status
Simulation time 12473566295 ps
CPU time 16.52 seconds
Started Apr 23 02:48:00 PM PDT 24
Finished Apr 23 02:48:17 PM PDT 24
Peak memory 251196 kb
Host smart-88c91d95-2ecb-4b2e-a295-ef714acf749c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454077130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1454077130
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.194533419
Short name T523
Test name
Test status
Simulation time 116817861 ps
CPU time 4.62 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:48:02 PM PDT 24
Peak memory 218000 kb
Host smart-3a46d515-96ea-46bd-8dab-294fc65198c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194533419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.194533419
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.455974249
Short name T438
Test name
Test status
Simulation time 564390346 ps
CPU time 14.44 seconds
Started Apr 23 02:47:58 PM PDT 24
Finished Apr 23 02:48:13 PM PDT 24
Peak memory 226020 kb
Host smart-dc59acbe-8949-4cc1-a79f-60750490cca3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455974249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.455974249
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1164603731
Short name T818
Test name
Test status
Simulation time 337296782 ps
CPU time 12.99 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:48:11 PM PDT 24
Peak memory 218048 kb
Host smart-d96459f2-ccd3-497c-8968-3016d8fdd5c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164603731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1164603731
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.783549333
Short name T763
Test name
Test status
Simulation time 386603610 ps
CPU time 8.34 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:48:06 PM PDT 24
Peak memory 217992 kb
Host smart-e247b484-be6b-4ac1-9bed-a258fece6ea6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783549333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.783549333
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.664114635
Short name T270
Test name
Test status
Simulation time 826933736 ps
CPU time 14.96 seconds
Started Apr 23 02:47:59 PM PDT 24
Finished Apr 23 02:48:15 PM PDT 24
Peak memory 218012 kb
Host smart-bffeb186-f788-4250-85f4-f7ae7212cd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664114635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.664114635
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1645098018
Short name T834
Test name
Test status
Simulation time 17943384 ps
CPU time 1.46 seconds
Started Apr 23 02:47:56 PM PDT 24
Finished Apr 23 02:47:58 PM PDT 24
Peak memory 213312 kb
Host smart-6c510867-912f-46ea-9ca6-c7585ac5220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645098018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1645098018
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3511517034
Short name T514
Test name
Test status
Simulation time 340771809 ps
CPU time 29.97 seconds
Started Apr 23 02:47:59 PM PDT 24
Finished Apr 23 02:48:29 PM PDT 24
Peak memory 250952 kb
Host smart-d0faf1f0-0c40-4331-bb88-9b7f0635d9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511517034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3511517034
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2401078591
Short name T830
Test name
Test status
Simulation time 229759201 ps
CPU time 6.05 seconds
Started Apr 23 02:47:55 PM PDT 24
Finished Apr 23 02:48:01 PM PDT 24
Peak memory 247040 kb
Host smart-edb141a0-a20d-4222-89e8-2363f39c45fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401078591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2401078591
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.919143983
Short name T335
Test name
Test status
Simulation time 3093274148 ps
CPU time 66.17 seconds
Started Apr 23 02:47:58 PM PDT 24
Finished Apr 23 02:49:05 PM PDT 24
Peak memory 283816 kb
Host smart-734b8ef0-8cbe-4f5e-9ebf-9508100e0f3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919143983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.919143983
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.634573115
Short name T687
Test name
Test status
Simulation time 25731930 ps
CPU time 0.9 seconds
Started Apr 23 02:47:56 PM PDT 24
Finished Apr 23 02:47:57 PM PDT 24
Peak memory 211732 kb
Host smart-fecb31c3-7eb4-4917-8426-197a82f6f295
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634573115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.634573115
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.840318904
Short name T617
Test name
Test status
Simulation time 22465561 ps
CPU time 1.22 seconds
Started Apr 23 02:48:05 PM PDT 24
Finished Apr 23 02:48:07 PM PDT 24
Peak memory 209576 kb
Host smart-35f698fc-fa90-4a7e-a9e1-a107c5d00e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840318904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.840318904
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.206525949
Short name T36
Test name
Test status
Simulation time 4338491302 ps
CPU time 16.4 seconds
Started Apr 23 02:48:07 PM PDT 24
Finished Apr 23 02:48:24 PM PDT 24
Peak memory 219104 kb
Host smart-a109d127-ad51-4c84-b19e-bdc0ae608012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206525949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.206525949
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3575163551
Short name T758
Test name
Test status
Simulation time 937704200 ps
CPU time 6.41 seconds
Started Apr 23 02:48:05 PM PDT 24
Finished Apr 23 02:48:12 PM PDT 24
Peak memory 209584 kb
Host smart-46e42adb-ae30-44e2-bc91-8e1b0f92fa82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575163551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3575163551
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.447720406
Short name T556
Test name
Test status
Simulation time 2990417713 ps
CPU time 41.47 seconds
Started Apr 23 02:48:08 PM PDT 24
Finished Apr 23 02:48:50 PM PDT 24
Peak memory 219496 kb
Host smart-c8c8b6fd-9a07-421d-be10-55a8c6f97fc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447720406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.447720406
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3795577301
Short name T82
Test name
Test status
Simulation time 1531899753 ps
CPU time 9.42 seconds
Started Apr 23 02:48:03 PM PDT 24
Finished Apr 23 02:48:13 PM PDT 24
Peak memory 217972 kb
Host smart-e4668dc4-775a-47fa-aeb3-214cae0e0e54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795577301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3795577301
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1910700141
Short name T737
Test name
Test status
Simulation time 1739449154 ps
CPU time 7.81 seconds
Started Apr 23 02:48:01 PM PDT 24
Finished Apr 23 02:48:10 PM PDT 24
Peak memory 213684 kb
Host smart-7aa00a3a-7e32-4025-95bd-f0c1c2adf3b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910700141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1910700141
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2686375480
Short name T488
Test name
Test status
Simulation time 4514857654 ps
CPU time 74.88 seconds
Started Apr 23 02:48:03 PM PDT 24
Finished Apr 23 02:49:18 PM PDT 24
Peak memory 267460 kb
Host smart-07d3832f-f074-4a26-b551-b6049ae2a9bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686375480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2686375480
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3669693346
Short name T775
Test name
Test status
Simulation time 1628646697 ps
CPU time 13.89 seconds
Started Apr 23 02:48:02 PM PDT 24
Finished Apr 23 02:48:16 PM PDT 24
Peak memory 251016 kb
Host smart-2edbf669-21fb-4ac1-a777-c950a0ed6ab0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669693346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3669693346
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3154137053
Short name T658
Test name
Test status
Simulation time 74544640 ps
CPU time 3.71 seconds
Started Apr 23 02:48:01 PM PDT 24
Finished Apr 23 02:48:05 PM PDT 24
Peak memory 218040 kb
Host smart-0360a463-eb43-4917-80de-2f56509fc2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154137053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3154137053
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2685767020
Short name T426
Test name
Test status
Simulation time 389176476 ps
CPU time 10.01 seconds
Started Apr 23 02:48:04 PM PDT 24
Finished Apr 23 02:48:14 PM PDT 24
Peak memory 225764 kb
Host smart-cb9b5d36-44c4-4c54-9a17-d17fa58ea548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685767020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2685767020
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.250586370
Short name T752
Test name
Test status
Simulation time 1064807361 ps
CPU time 10.38 seconds
Started Apr 23 02:48:06 PM PDT 24
Finished Apr 23 02:48:17 PM PDT 24
Peak memory 218000 kb
Host smart-deaa5546-623c-4fd8-b173-a0552611160a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250586370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.250586370
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3601632343
Short name T623
Test name
Test status
Simulation time 227615225 ps
CPU time 9.63 seconds
Started Apr 23 02:48:08 PM PDT 24
Finished Apr 23 02:48:18 PM PDT 24
Peak memory 217972 kb
Host smart-811f2ea3-cab2-49ee-a1c2-1b7a22020446
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601632343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3601632343
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2954490316
Short name T207
Test name
Test status
Simulation time 2152318779 ps
CPU time 18.83 seconds
Started Apr 23 02:48:01 PM PDT 24
Finished Apr 23 02:48:21 PM PDT 24
Peak memory 218096 kb
Host smart-bc78d758-d87b-4adf-b63b-f684fb635dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954490316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2954490316
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3528895124
Short name T771
Test name
Test status
Simulation time 26716290 ps
CPU time 1.62 seconds
Started Apr 23 02:47:57 PM PDT 24
Finished Apr 23 02:47:59 PM PDT 24
Peak memory 217776 kb
Host smart-e9ccee6f-9d1b-475d-8fd6-0b7f36423a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528895124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3528895124
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1363591638
Short name T323
Test name
Test status
Simulation time 800211604 ps
CPU time 22.13 seconds
Started Apr 23 02:47:59 PM PDT 24
Finished Apr 23 02:48:22 PM PDT 24
Peak memory 251112 kb
Host smart-0620cc59-a426-401c-af81-f812191bb09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363591638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1363591638
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4059700133
Short name T419
Test name
Test status
Simulation time 123343534 ps
CPU time 10.15 seconds
Started Apr 23 02:48:00 PM PDT 24
Finished Apr 23 02:48:11 PM PDT 24
Peak memory 251032 kb
Host smart-9cb9e1fb-7021-4a65-a226-a5af6f920a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059700133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4059700133
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.704930228
Short name T69
Test name
Test status
Simulation time 3191243837 ps
CPU time 46.18 seconds
Started Apr 23 02:48:07 PM PDT 24
Finished Apr 23 02:48:54 PM PDT 24
Peak memory 226184 kb
Host smart-b78a4813-19c3-4a00-adef-aac17c977411
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704930228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.704930228
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2024280681
Short name T153
Test name
Test status
Simulation time 126745691850 ps
CPU time 1698.99 seconds
Started Apr 23 02:48:08 PM PDT 24
Finished Apr 23 03:16:28 PM PDT 24
Peak memory 672276 kb
Host smart-de29fc1f-8cb2-40ae-bcda-f16a24ecc26a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2024280681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2024280681
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3006990140
Short name T171
Test name
Test status
Simulation time 37921067 ps
CPU time 0.94 seconds
Started Apr 23 02:47:58 PM PDT 24
Finished Apr 23 02:47:59 PM PDT 24
Peak memory 211696 kb
Host smart-de6b21dd-90dc-4e30-9b57-f130c0f5762e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006990140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3006990140
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1590815579
Short name T631
Test name
Test status
Simulation time 42797351 ps
CPU time 1.01 seconds
Started Apr 23 02:48:12 PM PDT 24
Finished Apr 23 02:48:14 PM PDT 24
Peak memory 209588 kb
Host smart-69c31ebf-191c-4703-8207-9aca1ba5651b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590815579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1590815579
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1622842382
Short name T709
Test name
Test status
Simulation time 323167034 ps
CPU time 15.62 seconds
Started Apr 23 02:48:09 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 217940 kb
Host smart-9db4ec5a-0c1b-4269-bfd7-fd57766ed889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622842382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1622842382
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3814012206
Short name T179
Test name
Test status
Simulation time 1639903938 ps
CPU time 18.44 seconds
Started Apr 23 02:48:09 PM PDT 24
Finished Apr 23 02:48:28 PM PDT 24
Peak memory 209572 kb
Host smart-b3e9c22f-02fd-4af4-a4c3-64e81eebcfd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814012206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3814012206
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2151348265
Short name T85
Test name
Test status
Simulation time 10368127347 ps
CPU time 71.13 seconds
Started Apr 23 02:48:09 PM PDT 24
Finished Apr 23 02:49:20 PM PDT 24
Peak memory 219012 kb
Host smart-e4f10763-24f9-4881-8407-1e8b9ebefcac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151348265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2151348265
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.721077792
Short name T353
Test name
Test status
Simulation time 662877991 ps
CPU time 10.79 seconds
Started Apr 23 02:48:08 PM PDT 24
Finished Apr 23 02:48:19 PM PDT 24
Peak memory 217992 kb
Host smart-1ab6f2da-1f00-427f-845c-2be084338bb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721077792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.721077792
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2052455243
Short name T385
Test name
Test status
Simulation time 220607261 ps
CPU time 4.36 seconds
Started Apr 23 02:48:09 PM PDT 24
Finished Apr 23 02:48:14 PM PDT 24
Peak memory 213648 kb
Host smart-c425ccc2-8114-4b71-9f23-4b9a748fe1e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052455243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2052455243
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2640183651
Short name T849
Test name
Test status
Simulation time 1227195247 ps
CPU time 58.58 seconds
Started Apr 23 02:48:08 PM PDT 24
Finished Apr 23 02:49:07 PM PDT 24
Peak memory 275644 kb
Host smart-20125524-eb4a-4dc0-853c-b83e45403a2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640183651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2640183651
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1786133808
Short name T510
Test name
Test status
Simulation time 326966957 ps
CPU time 14.21 seconds
Started Apr 23 02:48:10 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 246436 kb
Host smart-2c177557-0aa0-4bfd-99fc-431a73bb3b9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786133808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1786133808
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2557036914
Short name T760
Test name
Test status
Simulation time 35260631 ps
CPU time 2.34 seconds
Started Apr 23 02:48:07 PM PDT 24
Finished Apr 23 02:48:09 PM PDT 24
Peak memory 217964 kb
Host smart-12177b8f-ccad-4676-b9a9-d9934142406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557036914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2557036914
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.4230787537
Short name T400
Test name
Test status
Simulation time 1508036464 ps
CPU time 18.82 seconds
Started Apr 23 02:48:07 PM PDT 24
Finished Apr 23 02:48:26 PM PDT 24
Peak memory 226000 kb
Host smart-891ee682-577a-49d4-befb-f22be9400b6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230787537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.4230787537
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3372116007
Short name T410
Test name
Test status
Simulation time 967349805 ps
CPU time 13.07 seconds
Started Apr 23 02:48:24 PM PDT 24
Finished Apr 23 02:48:38 PM PDT 24
Peak memory 218004 kb
Host smart-7337f913-5171-4e3d-8a8e-d63423d12d41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372116007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3372116007
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3416018019
Short name T295
Test name
Test status
Simulation time 186158961 ps
CPU time 6.67 seconds
Started Apr 23 02:48:12 PM PDT 24
Finished Apr 23 02:48:19 PM PDT 24
Peak memory 217960 kb
Host smart-23c944be-af7c-4b82-a8ee-eccc1177b824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416018019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3416018019
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2474478971
Short name T161
Test name
Test status
Simulation time 900419833 ps
CPU time 8.79 seconds
Started Apr 23 02:48:07 PM PDT 24
Finished Apr 23 02:48:16 PM PDT 24
Peak memory 224320 kb
Host smart-3573c67d-ec0b-4b6a-aed5-828133d0ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474478971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2474478971
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.833190354
Short name T483
Test name
Test status
Simulation time 62373363 ps
CPU time 2.7 seconds
Started Apr 23 02:48:05 PM PDT 24
Finished Apr 23 02:48:08 PM PDT 24
Peak memory 217716 kb
Host smart-17199bea-ab58-4b76-aa2c-bae807471156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833190354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.833190354
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3807264223
Short name T254
Test name
Test status
Simulation time 697322326 ps
CPU time 27.13 seconds
Started Apr 23 02:48:07 PM PDT 24
Finished Apr 23 02:48:35 PM PDT 24
Peak memory 250512 kb
Host smart-08d64edf-4575-475a-bdfc-bb4ab780ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807264223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3807264223
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3615056532
Short name T511
Test name
Test status
Simulation time 39851345 ps
CPU time 7.67 seconds
Started Apr 23 02:48:05 PM PDT 24
Finished Apr 23 02:48:13 PM PDT 24
Peak memory 251048 kb
Host smart-2e082f6a-c7be-4d5b-bd3b-291e29f24d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615056532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3615056532
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3232960601
Short name T640
Test name
Test status
Simulation time 61228341941 ps
CPU time 283.69 seconds
Started Apr 23 02:48:12 PM PDT 24
Finished Apr 23 02:52:56 PM PDT 24
Peak memory 268224 kb
Host smart-bc12044c-da14-4112-a275-b7ce9782fc38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232960601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3232960601
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3145236459
Short name T786
Test name
Test status
Simulation time 6185932765 ps
CPU time 238.41 seconds
Started Apr 23 02:48:11 PM PDT 24
Finished Apr 23 02:52:11 PM PDT 24
Peak memory 275896 kb
Host smart-d05b3e6a-cadd-4a75-a277-ae38e56cdbf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3145236459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3145236459
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.667818464
Short name T316
Test name
Test status
Simulation time 14065495 ps
CPU time 1.04 seconds
Started Apr 23 02:48:05 PM PDT 24
Finished Apr 23 02:48:07 PM PDT 24
Peak memory 211588 kb
Host smart-6537145a-5f8d-42f1-b34c-f861ac1d5b95
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667818464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.667818464
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4207362512
Short name T580
Test name
Test status
Simulation time 57059488 ps
CPU time 1.49 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:27 PM PDT 24
Peak memory 209548 kb
Host smart-f5403948-4dec-4fd8-b7f2-184dc0194fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207362512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4207362512
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1091735227
Short name T601
Test name
Test status
Simulation time 227104347 ps
CPU time 9.59 seconds
Started Apr 23 02:48:11 PM PDT 24
Finished Apr 23 02:48:22 PM PDT 24
Peak memory 217988 kb
Host smart-6d0dcdaa-5177-4e25-8a1e-137cfbb075a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091735227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1091735227
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3874012455
Short name T143
Test name
Test status
Simulation time 392610342 ps
CPU time 4.53 seconds
Started Apr 23 02:48:16 PM PDT 24
Finished Apr 23 02:48:21 PM PDT 24
Peak memory 209592 kb
Host smart-a2c2723c-48a1-4ce5-a313-9689ece17ac1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874012455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3874012455
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2626023864
Short name T404
Test name
Test status
Simulation time 39644748681 ps
CPU time 29.73 seconds
Started Apr 23 02:48:13 PM PDT 24
Finished Apr 23 02:48:43 PM PDT 24
Peak memory 218536 kb
Host smart-d37d39da-0fcc-439b-9bdb-78990f0b8507
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626023864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2626023864
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1108257715
Short name T819
Test name
Test status
Simulation time 538869468 ps
CPU time 10.89 seconds
Started Apr 23 02:48:14 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 217968 kb
Host smart-a2281991-c9dc-4fbd-ab7b-863e5a99179a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108257715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1108257715
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2066402070
Short name T846
Test name
Test status
Simulation time 426800258 ps
CPU time 2.08 seconds
Started Apr 23 02:48:16 PM PDT 24
Finished Apr 23 02:48:19 PM PDT 24
Peak memory 213020 kb
Host smart-ba6add39-65dd-4881-93a0-2f05ac7045c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066402070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2066402070
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2970387995
Short name T742
Test name
Test status
Simulation time 21844273450 ps
CPU time 78.06 seconds
Started Apr 23 02:48:15 PM PDT 24
Finished Apr 23 02:49:33 PM PDT 24
Peak memory 283844 kb
Host smart-1b9dbc82-dcc1-49d0-99ca-5580688e350d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970387995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2970387995
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4002799579
Short name T449
Test name
Test status
Simulation time 3078131784 ps
CPU time 16.07 seconds
Started Apr 23 02:48:17 PM PDT 24
Finished Apr 23 02:48:33 PM PDT 24
Peak memory 250988 kb
Host smart-860c5f5b-7792-43bb-9989-357b8f9e8d66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002799579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.4002799579
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1651844986
Short name T807
Test name
Test status
Simulation time 160038644 ps
CPU time 2.5 seconds
Started Apr 23 02:48:11 PM PDT 24
Finished Apr 23 02:48:14 PM PDT 24
Peak memory 218008 kb
Host smart-e1ff8117-8a5c-4fc6-bef3-0d88d36166d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651844986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1651844986
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4157348421
Short name T609
Test name
Test status
Simulation time 2022008447 ps
CPU time 14.17 seconds
Started Apr 23 02:48:16 PM PDT 24
Finished Apr 23 02:48:31 PM PDT 24
Peak memory 226096 kb
Host smart-951592a4-09e9-465e-b44a-8268fa7a6e8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157348421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4157348421
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1554089434
Short name T591
Test name
Test status
Simulation time 275184780 ps
CPU time 8.27 seconds
Started Apr 23 02:48:17 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 218008 kb
Host smart-78a0ff93-f147-4625-93c2-c920dce0a78c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554089434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1554089434
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1229289725
Short name T657
Test name
Test status
Simulation time 856946884 ps
CPU time 9.43 seconds
Started Apr 23 02:48:14 PM PDT 24
Finished Apr 23 02:48:24 PM PDT 24
Peak memory 218028 kb
Host smart-61a47cb5-29d1-4698-a851-58808245b26c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229289725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1229289725
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1204448091
Short name T491
Test name
Test status
Simulation time 1525075134 ps
CPU time 9.16 seconds
Started Apr 23 02:48:15 PM PDT 24
Finished Apr 23 02:48:24 PM PDT 24
Peak memory 218004 kb
Host smart-7c9a8f40-dc17-4fce-8e0f-237497ec15d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204448091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1204448091
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2864462885
Short name T59
Test name
Test status
Simulation time 66822872 ps
CPU time 2.45 seconds
Started Apr 23 02:48:12 PM PDT 24
Finished Apr 23 02:48:15 PM PDT 24
Peak memory 214004 kb
Host smart-5e3674a8-837e-442e-b05d-8d4b7cc19d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864462885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2864462885
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2143934728
Short name T761
Test name
Test status
Simulation time 368358974 ps
CPU time 23.29 seconds
Started Apr 23 02:48:09 PM PDT 24
Finished Apr 23 02:48:33 PM PDT 24
Peak memory 251024 kb
Host smart-b1d2c253-ca28-405f-bea4-e051ae782187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143934728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2143934728
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.378410910
Short name T625
Test name
Test status
Simulation time 114390515 ps
CPU time 7.44 seconds
Started Apr 23 02:48:11 PM PDT 24
Finished Apr 23 02:48:20 PM PDT 24
Peak memory 251016 kb
Host smart-08095300-303a-4607-be1d-2a93b3f932c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378410910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.378410910
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1355081151
Short name T73
Test name
Test status
Simulation time 10712461451 ps
CPU time 159.22 seconds
Started Apr 23 02:48:17 PM PDT 24
Finished Apr 23 02:50:56 PM PDT 24
Peak memory 291168 kb
Host smart-8225fdd9-3da9-46ce-a702-18c15de842fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355081151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1355081151
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.442919707
Short name T693
Test name
Test status
Simulation time 12008832398 ps
CPU time 198.14 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:51:42 PM PDT 24
Peak memory 291300 kb
Host smart-e7f806f5-5a00-4430-9759-33bd011d5176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=442919707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.442919707
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.202928507
Short name T704
Test name
Test status
Simulation time 41316947 ps
CPU time 0.83 seconds
Started Apr 23 02:48:11 PM PDT 24
Finished Apr 23 02:48:12 PM PDT 24
Peak memory 211664 kb
Host smart-a4c19d89-d4b1-4791-a896-5e8df05f6e2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202928507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.202928507
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3860059173
Short name T440
Test name
Test status
Simulation time 12874157 ps
CPU time 0.85 seconds
Started Apr 23 02:48:21 PM PDT 24
Finished Apr 23 02:48:23 PM PDT 24
Peak memory 209352 kb
Host smart-112a22da-92b2-4d11-83ca-caedc1ca5b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860059173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3860059173
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1584669314
Short name T776
Test name
Test status
Simulation time 2599936936 ps
CPU time 11.33 seconds
Started Apr 23 02:48:16 PM PDT 24
Finished Apr 23 02:48:28 PM PDT 24
Peak memory 218016 kb
Host smart-0a7aecee-3022-4b4c-a42c-b22257938a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584669314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1584669314
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3792011828
Short name T178
Test name
Test status
Simulation time 1512886224 ps
CPU time 5.74 seconds
Started Apr 23 02:48:17 PM PDT 24
Finished Apr 23 02:48:23 PM PDT 24
Peak memory 209560 kb
Host smart-28484d13-1f4c-4ad5-a24c-eb347cc8758f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792011828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3792011828
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2444229303
Short name T679
Test name
Test status
Simulation time 1371165413 ps
CPU time 22.86 seconds
Started Apr 23 02:48:22 PM PDT 24
Finished Apr 23 02:48:45 PM PDT 24
Peak memory 217964 kb
Host smart-6fc1c7ca-d976-472b-b2fa-37fa1e08247d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444229303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2444229303
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.543394132
Short name T863
Test name
Test status
Simulation time 2354331810 ps
CPU time 7.95 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:34 PM PDT 24
Peak memory 217872 kb
Host smart-83aa2775-527d-47a6-af6e-db931985419d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543394132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.543394132
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3389280999
Short name T233
Test name
Test status
Simulation time 176013457 ps
CPU time 5.19 seconds
Started Apr 23 02:48:18 PM PDT 24
Finished Apr 23 02:48:24 PM PDT 24
Peak memory 213348 kb
Host smart-85fd6cbd-b3a4-4b83-9a58-42722d7cf39d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389280999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3389280999
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2625853743
Short name T502
Test name
Test status
Simulation time 1878110117 ps
CPU time 46.96 seconds
Started Apr 23 02:48:17 PM PDT 24
Finished Apr 23 02:49:05 PM PDT 24
Peak memory 251028 kb
Host smart-7f27e8b1-e9d1-4519-a1fa-a1378a497ce0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625853743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2625853743
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1800000163
Short name T454
Test name
Test status
Simulation time 3944007937 ps
CPU time 31.59 seconds
Started Apr 23 02:48:16 PM PDT 24
Finished Apr 23 02:48:48 PM PDT 24
Peak memory 251052 kb
Host smart-dd80d00b-fabf-4ea9-95a6-a89bcfdf269c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800000163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1800000163
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2065384452
Short name T264
Test name
Test status
Simulation time 31432260 ps
CPU time 2.14 seconds
Started Apr 23 02:48:22 PM PDT 24
Finished Apr 23 02:48:24 PM PDT 24
Peak memory 217964 kb
Host smart-8f56939b-dcb7-4411-b5f7-28052c508a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065384452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2065384452
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1204857052
Short name T833
Test name
Test status
Simulation time 757869741 ps
CPU time 11.3 seconds
Started Apr 23 02:48:20 PM PDT 24
Finished Apr 23 02:48:32 PM PDT 24
Peak memory 217984 kb
Host smart-92bcf96b-a167-47ff-a31d-b16776d17fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204857052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1204857052
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1211858684
Short name T168
Test name
Test status
Simulation time 986961449 ps
CPU time 13.16 seconds
Started Apr 23 02:48:20 PM PDT 24
Finished Apr 23 02:48:34 PM PDT 24
Peak memory 217560 kb
Host smart-34096a06-6233-4205-8a22-80e1463c523b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211858684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1211858684
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2966645638
Short name T154
Test name
Test status
Simulation time 1807055658 ps
CPU time 7.82 seconds
Started Apr 23 02:48:17 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 218000 kb
Host smart-60b8e692-e135-4d9d-ab3d-bbcdff07425e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966645638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2966645638
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.775973003
Short name T428
Test name
Test status
Simulation time 1439634268 ps
CPU time 13.57 seconds
Started Apr 23 02:48:18 PM PDT 24
Finished Apr 23 02:48:32 PM PDT 24
Peak memory 218020 kb
Host smart-b1a76b95-967b-4ffa-b418-77113acd728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775973003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.775973003
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.621618790
Short name T163
Test name
Test status
Simulation time 46813226 ps
CPU time 2.6 seconds
Started Apr 23 02:48:18 PM PDT 24
Finished Apr 23 02:48:21 PM PDT 24
Peak memory 213964 kb
Host smart-4251979c-b739-4b35-8ff3-3299c3453121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621618790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.621618790
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1272758454
Short name T11
Test name
Test status
Simulation time 471898266 ps
CPU time 19.19 seconds
Started Apr 23 02:48:21 PM PDT 24
Finished Apr 23 02:48:41 PM PDT 24
Peak memory 250752 kb
Host smart-3db7cbe3-f2a0-4ec8-831e-18c3852bac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272758454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1272758454
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1115581826
Short name T299
Test name
Test status
Simulation time 150148224 ps
CPU time 6.95 seconds
Started Apr 23 02:48:18 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 246988 kb
Host smart-c0982e60-86ea-45de-86fb-51260dcd3a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115581826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1115581826
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3485559716
Short name T170
Test name
Test status
Simulation time 22112717458 ps
CPU time 175.8 seconds
Started Apr 23 02:48:18 PM PDT 24
Finished Apr 23 02:51:15 PM PDT 24
Peak memory 316640 kb
Host smart-115068f7-86ff-4ea1-b264-04bfb2b1689d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485559716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3485559716
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3134013096
Short name T332
Test name
Test status
Simulation time 49080406 ps
CPU time 0.86 seconds
Started Apr 23 02:48:15 PM PDT 24
Finished Apr 23 02:48:17 PM PDT 24
Peak memory 211588 kb
Host smart-05567995-821d-453f-b854-304c484c00a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134013096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3134013096
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2785041349
Short name T224
Test name
Test status
Simulation time 122086444 ps
CPU time 0.82 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 209520 kb
Host smart-fbc5b9c7-32f9-484d-ad8f-8092abb65c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785041349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2785041349
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3020569850
Short name T656
Test name
Test status
Simulation time 1807102142 ps
CPU time 15.26 seconds
Started Apr 23 02:48:20 PM PDT 24
Finished Apr 23 02:48:36 PM PDT 24
Peak memory 217956 kb
Host smart-55eb3eb9-5117-4e9b-84c5-d331c5b01c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020569850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3020569850
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2699573369
Short name T4
Test name
Test status
Simulation time 462127825 ps
CPU time 4.99 seconds
Started Apr 23 02:48:31 PM PDT 24
Finished Apr 23 02:48:37 PM PDT 24
Peak memory 209584 kb
Host smart-4ab549be-89ce-4907-ac8c-0c8af8652978
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699573369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2699573369
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3042837782
Short name T862
Test name
Test status
Simulation time 1607900707 ps
CPU time 47.35 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:49:11 PM PDT 24
Peak memory 217940 kb
Host smart-46a64dd1-1bf9-4ae5-8a20-b73839bcc682
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042837782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3042837782
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2373702314
Short name T451
Test name
Test status
Simulation time 152050113 ps
CPU time 3.17 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:48:27 PM PDT 24
Peak memory 217960 kb
Host smart-9d7413c1-4d07-425e-922b-9732c410557d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373702314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2373702314
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2625339294
Short name T329
Test name
Test status
Simulation time 2450307402 ps
CPU time 2.86 seconds
Started Apr 23 02:48:24 PM PDT 24
Finished Apr 23 02:48:27 PM PDT 24
Peak memory 213020 kb
Host smart-da330ddf-9641-476e-a8a1-0596dbb076ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625339294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2625339294
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2005650414
Short name T209
Test name
Test status
Simulation time 3251531550 ps
CPU time 65.21 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:49:29 PM PDT 24
Peak memory 283776 kb
Host smart-49a2ffc4-fab9-4699-aaee-64499a73e113
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005650414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2005650414
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1458081193
Short name T668
Test name
Test status
Simulation time 1040860832 ps
CPU time 12.02 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:38 PM PDT 24
Peak memory 247280 kb
Host smart-6ed143c5-e0bc-43e5-9800-6adc4395e9ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458081193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1458081193
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3765925606
Short name T10
Test name
Test status
Simulation time 49916742 ps
CPU time 2.6 seconds
Started Apr 23 02:48:21 PM PDT 24
Finished Apr 23 02:48:24 PM PDT 24
Peak memory 218080 kb
Host smart-d0428cc7-8861-47dc-990e-74c0738c0298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765925606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3765925606
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.434280781
Short name T227
Test name
Test status
Simulation time 1534128428 ps
CPU time 11.92 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:38 PM PDT 24
Peak memory 226088 kb
Host smart-9cc3e80b-6ba6-4372-92e2-ab0649e74f31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434280781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.434280781
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3628505237
Short name T283
Test name
Test status
Simulation time 277735698 ps
CPU time 11.23 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:48:35 PM PDT 24
Peak memory 218012 kb
Host smart-81d24f1d-dcc1-4d4e-b675-c007111c4949
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628505237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3628505237
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.455186835
Short name T526
Test name
Test status
Simulation time 529706169 ps
CPU time 12 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:48:36 PM PDT 24
Peak memory 218024 kb
Host smart-61a1e19e-4341-4ce4-9661-ede7c704f394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455186835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.455186835
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3624100003
Short name T71
Test name
Test status
Simulation time 1254255934 ps
CPU time 12.77 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:48:36 PM PDT 24
Peak memory 218004 kb
Host smart-669a5c1f-dbbb-4877-9d35-69de34ded629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624100003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3624100003
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2012291199
Short name T792
Test name
Test status
Simulation time 75708936 ps
CPU time 1.49 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:27 PM PDT 24
Peak memory 217604 kb
Host smart-f239b5eb-48a3-4c0c-bece-175cdd016d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012291199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2012291199
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3598595126
Short name T595
Test name
Test status
Simulation time 873578488 ps
CPU time 23.7 seconds
Started Apr 23 02:48:20 PM PDT 24
Finished Apr 23 02:48:44 PM PDT 24
Peak memory 251008 kb
Host smart-2768e616-bb93-43dd-86e8-f4a34a8a0afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598595126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3598595126
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1497918314
Short name T689
Test name
Test status
Simulation time 96919360 ps
CPU time 3.08 seconds
Started Apr 23 02:48:20 PM PDT 24
Finished Apr 23 02:48:23 PM PDT 24
Peak memory 222076 kb
Host smart-8a2d8f53-9e45-4b13-beb0-f4603783a5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497918314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1497918314
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.270486679
Short name T713
Test name
Test status
Simulation time 13949942536 ps
CPU time 269.45 seconds
Started Apr 23 02:48:23 PM PDT 24
Finished Apr 23 02:52:53 PM PDT 24
Peak memory 283892 kb
Host smart-2f7416d2-03d9-4c6e-b07a-451b77abcb53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270486679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.270486679
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.294020379
Short name T654
Test name
Test status
Simulation time 29653543 ps
CPU time 1.01 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:27 PM PDT 24
Peak memory 211592 kb
Host smart-b783ee1d-68cc-4df9-b4d4-617c9727e90e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294020379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.294020379
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3667446767
Short name T705
Test name
Test status
Simulation time 17982643 ps
CPU time 0.92 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:07 PM PDT 24
Peak memory 209512 kb
Host smart-b459ef1d-55e8-49ae-b539-ac3a9b504567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667446767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3667446767
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2913461647
Short name T765
Test name
Test status
Simulation time 13383428 ps
CPU time 0.86 seconds
Started Apr 23 02:46:55 PM PDT 24
Finished Apr 23 02:46:56 PM PDT 24
Peak memory 209352 kb
Host smart-0be3e3f6-9dda-4f49-8da1-6c2d9b3d7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913461647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2913461647
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1434817340
Short name T790
Test name
Test status
Simulation time 691274611 ps
CPU time 11.82 seconds
Started Apr 23 02:46:57 PM PDT 24
Finished Apr 23 02:47:09 PM PDT 24
Peak memory 217960 kb
Host smart-5940a04a-80f9-4376-9daa-64ffba91af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434817340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1434817340
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2504050960
Short name T175
Test name
Test status
Simulation time 1512317586 ps
CPU time 11.16 seconds
Started Apr 23 02:47:01 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 209584 kb
Host smart-693e49c3-a192-4185-b45a-36ad90fee49a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504050960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2504050960
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2931812734
Short name T844
Test name
Test status
Simulation time 1413231799 ps
CPU time 24.04 seconds
Started Apr 23 02:46:58 PM PDT 24
Finished Apr 23 02:47:23 PM PDT 24
Peak memory 217924 kb
Host smart-2e04bc11-2a49-48bc-8ff3-bded47bd0af4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931812734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2931812734
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1241459725
Short name T745
Test name
Test status
Simulation time 290498294 ps
CPU time 4 seconds
Started Apr 23 02:47:01 PM PDT 24
Finished Apr 23 02:47:06 PM PDT 24
Peak memory 217300 kb
Host smart-ad813f96-23fc-4fdd-8ff2-980adfb6d203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241459725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
241459725
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3554655526
Short name T20
Test name
Test status
Simulation time 112175976 ps
CPU time 4.12 seconds
Started Apr 23 02:46:57 PM PDT 24
Finished Apr 23 02:47:01 PM PDT 24
Peak memory 217984 kb
Host smart-8d9c5828-ba43-4e5c-bb9c-818bb44470e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554655526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3554655526
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4081836380
Short name T12
Test name
Test status
Simulation time 941472571 ps
CPU time 10.17 seconds
Started Apr 23 02:47:01 PM PDT 24
Finished Apr 23 02:47:12 PM PDT 24
Peak memory 213080 kb
Host smart-089f6341-7f72-41b9-a2f4-e422620e80a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081836380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4081836380
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.218679583
Short name T754
Test name
Test status
Simulation time 1082349424 ps
CPU time 2.36 seconds
Started Apr 23 02:46:56 PM PDT 24
Finished Apr 23 02:46:58 PM PDT 24
Peak memory 213064 kb
Host smart-50228161-4534-4c94-ac0c-c2d407b4d0b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218679583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.218679583
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.762268263
Short name T217
Test name
Test status
Simulation time 6019647672 ps
CPU time 54.67 seconds
Started Apr 23 02:47:00 PM PDT 24
Finished Apr 23 02:47:55 PM PDT 24
Peak memory 269708 kb
Host smart-2ede819a-b087-456b-8e2a-ed2f33a173ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762268263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.762268263
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.814840825
Short name T772
Test name
Test status
Simulation time 1712403762 ps
CPU time 18.75 seconds
Started Apr 23 02:46:59 PM PDT 24
Finished Apr 23 02:47:18 PM PDT 24
Peak memory 251056 kb
Host smart-bd92276d-c6c3-47f3-b5fd-dd00caef3aa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814840825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.814840825
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.4236023046
Short name T158
Test name
Test status
Simulation time 289630302 ps
CPU time 3.67 seconds
Started Apr 23 02:46:56 PM PDT 24
Finished Apr 23 02:47:00 PM PDT 24
Peak memory 218036 kb
Host smart-fe6cb6f3-bcc9-437a-98ff-958dbc8c0fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236023046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.4236023046
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3628998941
Short name T832
Test name
Test status
Simulation time 590484751 ps
CPU time 8.23 seconds
Started Apr 23 02:46:56 PM PDT 24
Finished Apr 23 02:47:04 PM PDT 24
Peak memory 214380 kb
Host smart-3f119d43-7d50-46b1-aa34-327c8e881e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628998941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3628998941
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3127828733
Short name T43
Test name
Test status
Simulation time 122613647 ps
CPU time 23.71 seconds
Started Apr 23 02:47:00 PM PDT 24
Finished Apr 23 02:47:24 PM PDT 24
Peak memory 284404 kb
Host smart-073dea71-631c-4603-80ef-9a992be27ecd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127828733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3127828733
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.489281859
Short name T614
Test name
Test status
Simulation time 1308778258 ps
CPU time 15.84 seconds
Started Apr 23 02:46:58 PM PDT 24
Finished Apr 23 02:47:14 PM PDT 24
Peak memory 218060 kb
Host smart-3dbd41e2-50e2-4490-8300-80fa884e3347
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489281859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.489281859
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2367771501
Short name T530
Test name
Test status
Simulation time 1503685879 ps
CPU time 11.16 seconds
Started Apr 23 02:47:01 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 218000 kb
Host smart-30d3fbb4-77d5-4eb1-bb3c-c33b00b53ff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367771501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2367771501
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1972494082
Short name T827
Test name
Test status
Simulation time 607780951 ps
CPU time 11.77 seconds
Started Apr 23 02:47:05 PM PDT 24
Finished Apr 23 02:47:17 PM PDT 24
Peak memory 218008 kb
Host smart-184f6405-d41a-45b6-ba8d-ffd386ad194c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972494082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
972494082
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2778020442
Short name T870
Test name
Test status
Simulation time 931830104 ps
CPU time 7.21 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:14 PM PDT 24
Peak memory 224948 kb
Host smart-f1433897-fac1-4f3b-98ea-88aeacb6fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778020442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2778020442
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2253285397
Short name T520
Test name
Test status
Simulation time 36740632 ps
CPU time 2.35 seconds
Started Apr 23 02:46:56 PM PDT 24
Finished Apr 23 02:46:58 PM PDT 24
Peak memory 217716 kb
Host smart-0d1aab25-3002-4fca-829c-809bd45a1e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253285397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2253285397
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.436490059
Short name T610
Test name
Test status
Simulation time 1009150752 ps
CPU time 30.78 seconds
Started Apr 23 02:46:57 PM PDT 24
Finished Apr 23 02:47:28 PM PDT 24
Peak memory 251008 kb
Host smart-f6bcd943-79b8-4515-a604-f4785ec0ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436490059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.436490059
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2468350761
Short name T470
Test name
Test status
Simulation time 976098471 ps
CPU time 6.75 seconds
Started Apr 23 02:46:56 PM PDT 24
Finished Apr 23 02:47:03 PM PDT 24
Peak memory 247428 kb
Host smart-1364e931-3d89-4d26-8c4f-88ba3834c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468350761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2468350761
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.669572911
Short name T569
Test name
Test status
Simulation time 10287690987 ps
CPU time 180.81 seconds
Started Apr 23 02:46:58 PM PDT 24
Finished Apr 23 02:50:00 PM PDT 24
Peak memory 316672 kb
Host smart-91e392ba-db55-4d66-97e3-c4ff001c83f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669572911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.669572911
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.77398933
Short name T79
Test name
Test status
Simulation time 82122247749 ps
CPU time 750.31 seconds
Started Apr 23 02:47:01 PM PDT 24
Finished Apr 23 02:59:32 PM PDT 24
Peak memory 332980 kb
Host smart-b5755642-0563-4b11-ab7d-554abf1e007d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=77398933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.77398933
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.546133005
Short name T788
Test name
Test status
Simulation time 39681736 ps
CPU time 0.98 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:08 PM PDT 24
Peak memory 211600 kb
Host smart-e7deacc8-9108-4708-b9a4-86f7d4f676ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546133005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.546133005
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1347583698
Short name T831
Test name
Test status
Simulation time 27327810 ps
CPU time 0.99 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:29 PM PDT 24
Peak memory 209540 kb
Host smart-6d3f100d-2faa-4848-be0f-0b9aed0bd1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347583698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1347583698
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.4069980756
Short name T710
Test name
Test status
Simulation time 710034733 ps
CPU time 15.71 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:44 PM PDT 24
Peak memory 218060 kb
Host smart-399d67a4-5e03-4314-991c-38ea4f0af145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069980756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.4069980756
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3041083905
Short name T24
Test name
Test status
Simulation time 972160260 ps
CPU time 11.86 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:41 PM PDT 24
Peak memory 209584 kb
Host smart-5a3c505b-03ec-4bcf-bf90-ec0a4a29f547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041083905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3041083905
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3779177769
Short name T672
Test name
Test status
Simulation time 53254913 ps
CPU time 2.54 seconds
Started Apr 23 02:48:27 PM PDT 24
Finished Apr 23 02:48:30 PM PDT 24
Peak memory 217912 kb
Host smart-307ddc3b-f317-410f-a96e-4702aefc6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779177769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3779177769
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1176793240
Short name T568
Test name
Test status
Simulation time 2757502521 ps
CPU time 10.67 seconds
Started Apr 23 02:48:27 PM PDT 24
Finished Apr 23 02:48:38 PM PDT 24
Peak memory 226124 kb
Host smart-2dd22124-82a3-41fc-af8f-a16ebc3f13d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176793240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1176793240
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.387704079
Short name T812
Test name
Test status
Simulation time 632354303 ps
CPU time 9.88 seconds
Started Apr 23 02:48:29 PM PDT 24
Finished Apr 23 02:48:39 PM PDT 24
Peak memory 218008 kb
Host smart-6097f53f-82e1-4556-83e4-be528b65c9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387704079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.387704079
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1242589797
Short name T650
Test name
Test status
Simulation time 2186872259 ps
CPU time 13.44 seconds
Started Apr 23 02:48:26 PM PDT 24
Finished Apr 23 02:48:40 PM PDT 24
Peak memory 218128 kb
Host smart-986bc2a7-b8ab-4d3a-8766-9cca241e78eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242589797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1242589797
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4061372891
Short name T660
Test name
Test status
Simulation time 1070786921 ps
CPU time 6.9 seconds
Started Apr 23 02:48:29 PM PDT 24
Finished Apr 23 02:48:37 PM PDT 24
Peak memory 224268 kb
Host smart-ab88cbb1-76ec-427e-b65e-2638c21160cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061372891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4061372891
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1900151393
Short name T695
Test name
Test status
Simulation time 224531722 ps
CPU time 1.53 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:27 PM PDT 24
Peak memory 213820 kb
Host smart-f68a2dc6-5d9a-4d2a-bd65-1bf07ba753e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900151393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1900151393
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1029879599
Short name T472
Test name
Test status
Simulation time 1038534660 ps
CPU time 31.19 seconds
Started Apr 23 02:48:24 PM PDT 24
Finished Apr 23 02:48:56 PM PDT 24
Peak memory 250956 kb
Host smart-d5302321-f447-465e-b570-669c1f9c8bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029879599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1029879599
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.292564473
Short name T836
Test name
Test status
Simulation time 213425202 ps
CPU time 9.75 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:36 PM PDT 24
Peak memory 251012 kb
Host smart-e73ad767-3561-475d-b58c-753a09098ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292564473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.292564473
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3299942606
Short name T688
Test name
Test status
Simulation time 5762453493 ps
CPU time 140.36 seconds
Started Apr 23 02:48:29 PM PDT 24
Finished Apr 23 02:50:50 PM PDT 24
Peak memory 272316 kb
Host smart-1f35d50a-e8e3-4540-b395-8f7b528ff344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299942606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3299942606
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1840009712
Short name T139
Test name
Test status
Simulation time 93998823 ps
CPU time 0.96 seconds
Started Apr 23 02:48:27 PM PDT 24
Finished Apr 23 02:48:28 PM PDT 24
Peak memory 211764 kb
Host smart-a1b11351-7db8-49a4-a1ad-f115c3d344f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840009712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1840009712
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3940648782
Short name T446
Test name
Test status
Simulation time 24851414 ps
CPU time 0.93 seconds
Started Apr 23 02:48:31 PM PDT 24
Finished Apr 23 02:48:32 PM PDT 24
Peak memory 209572 kb
Host smart-94c5185a-04ce-4ec7-b64d-1fad832b8f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940648782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3940648782
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.265124238
Short name T838
Test name
Test status
Simulation time 321205840 ps
CPU time 14.36 seconds
Started Apr 23 02:48:26 PM PDT 24
Finished Apr 23 02:48:41 PM PDT 24
Peak memory 217888 kb
Host smart-665461b4-0ada-4df2-a307-8cb07a968b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265124238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.265124238
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2704128602
Short name T401
Test name
Test status
Simulation time 432214145 ps
CPU time 8.12 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:37 PM PDT 24
Peak memory 209492 kb
Host smart-a0335357-196b-497b-9928-83c730f18252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704128602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2704128602
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2912892525
Short name T619
Test name
Test status
Simulation time 65020073 ps
CPU time 3.25 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:32 PM PDT 24
Peak memory 217964 kb
Host smart-135ca744-48f2-4782-b48d-5ae14d4865dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912892525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2912892525
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2964005033
Short name T529
Test name
Test status
Simulation time 360365622 ps
CPU time 12.65 seconds
Started Apr 23 02:48:29 PM PDT 24
Finished Apr 23 02:48:43 PM PDT 24
Peak memory 226084 kb
Host smart-d3e1d77f-1df5-4a23-9437-9273a3093f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964005033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2964005033
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2841216172
Short name T285
Test name
Test status
Simulation time 3057687511 ps
CPU time 9.14 seconds
Started Apr 23 02:48:30 PM PDT 24
Finished Apr 23 02:48:40 PM PDT 24
Peak memory 218096 kb
Host smart-94f54b98-8fc1-4bc3-a6d1-d623bf6f4f61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841216172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2841216172
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1386550874
Short name T241
Test name
Test status
Simulation time 1397158282 ps
CPU time 8.92 seconds
Started Apr 23 02:48:31 PM PDT 24
Finished Apr 23 02:48:41 PM PDT 24
Peak memory 218008 kb
Host smart-881cd00d-467f-4816-8159-cda7402a5b52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386550874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1386550874
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.838863545
Short name T685
Test name
Test status
Simulation time 258107542 ps
CPU time 8.27 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:37 PM PDT 24
Peak memory 218080 kb
Host smart-c1d533a6-91ff-49c8-a16f-4ad3e1178641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838863545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.838863545
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.391067261
Short name T699
Test name
Test status
Simulation time 135167668 ps
CPU time 2.52 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:28 PM PDT 24
Peak memory 214524 kb
Host smart-78abf612-33a7-4890-97aa-2734a58d4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391067261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.391067261
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1310630849
Short name T268
Test name
Test status
Simulation time 323259087 ps
CPU time 17.74 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:46 PM PDT 24
Peak memory 251012 kb
Host smart-2d58b262-7f56-4f93-9711-2e341e2fd148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310630849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1310630849
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.338637805
Short name T605
Test name
Test status
Simulation time 98315560 ps
CPU time 7.28 seconds
Started Apr 23 02:48:25 PM PDT 24
Finished Apr 23 02:48:33 PM PDT 24
Peak memory 250572 kb
Host smart-38439575-05b2-437e-afb5-d7d395987404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338637805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.338637805
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.847355217
Short name T753
Test name
Test status
Simulation time 17025189137 ps
CPU time 102.67 seconds
Started Apr 23 02:48:30 PM PDT 24
Finished Apr 23 02:50:13 PM PDT 24
Peak memory 283892 kb
Host smart-7b570052-4ced-481b-a45e-34856d585f17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847355217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.847355217
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3438874011
Short name T130
Test name
Test status
Simulation time 76655310158 ps
CPU time 436.25 seconds
Started Apr 23 02:48:32 PM PDT 24
Finished Apr 23 02:55:49 PM PDT 24
Peak memory 333132 kb
Host smart-7cd1b6d6-da91-44af-911d-79932dfb577d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3438874011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3438874011
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4014367717
Short name T720
Test name
Test status
Simulation time 33489570 ps
CPU time 0.83 seconds
Started Apr 23 02:48:28 PM PDT 24
Finished Apr 23 02:48:29 PM PDT 24
Peak memory 211640 kb
Host smart-dbe55bcc-353e-4fe4-896d-4c220e7bcff8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014367717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4014367717
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4103589440
Short name T692
Test name
Test status
Simulation time 21550589 ps
CPU time 1.06 seconds
Started Apr 23 02:48:33 PM PDT 24
Finished Apr 23 02:48:34 PM PDT 24
Peak memory 209512 kb
Host smart-c09ec24a-8d2a-4b7c-842c-a40f161a18af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103589440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4103589440
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2707568669
Short name T379
Test name
Test status
Simulation time 927117719 ps
CPU time 14.52 seconds
Started Apr 23 02:48:30 PM PDT 24
Finished Apr 23 02:48:45 PM PDT 24
Peak memory 217984 kb
Host smart-2ae5bd00-ac71-4bdc-a722-632596742f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707568669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2707568669
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1678935486
Short name T642
Test name
Test status
Simulation time 348239512 ps
CPU time 1.69 seconds
Started Apr 23 02:48:30 PM PDT 24
Finished Apr 23 02:48:32 PM PDT 24
Peak memory 216900 kb
Host smart-3ae68bee-9955-4ffd-ab63-e79ab7bb165a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678935486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1678935486
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2793835153
Short name T768
Test name
Test status
Simulation time 77200157 ps
CPU time 3.01 seconds
Started Apr 23 02:48:31 PM PDT 24
Finished Apr 23 02:48:35 PM PDT 24
Peak memory 217968 kb
Host smart-59183356-e43e-4497-a0af-a6f96ce5ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793835153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2793835153
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.887754288
Short name T450
Test name
Test status
Simulation time 799733928 ps
CPU time 9.8 seconds
Started Apr 23 02:48:32 PM PDT 24
Finished Apr 23 02:48:42 PM PDT 24
Peak memory 226032 kb
Host smart-b1e96d46-1a47-40fa-aa5f-cea96f497b74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887754288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.887754288
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1259708327
Short name T499
Test name
Test status
Simulation time 444320015 ps
CPU time 18.57 seconds
Started Apr 23 02:48:33 PM PDT 24
Finished Apr 23 02:48:52 PM PDT 24
Peak memory 218020 kb
Host smart-952bce69-cd93-44dd-b0f7-1a8e92a5d016
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259708327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1259708327
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.300721526
Short name T442
Test name
Test status
Simulation time 1203819360 ps
CPU time 7.4 seconds
Started Apr 23 02:48:29 PM PDT 24
Finished Apr 23 02:48:37 PM PDT 24
Peak memory 218004 kb
Host smart-2b11eda4-1300-46c5-955b-03bf4a6139e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300721526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.300721526
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2284603275
Short name T380
Test name
Test status
Simulation time 928683736 ps
CPU time 10.34 seconds
Started Apr 23 02:48:32 PM PDT 24
Finished Apr 23 02:48:43 PM PDT 24
Peak memory 218084 kb
Host smart-5a5abb90-b93d-4214-bdb0-b8e35497c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284603275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2284603275
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3111977554
Short name T565
Test name
Test status
Simulation time 15494722 ps
CPU time 1.21 seconds
Started Apr 23 02:48:29 PM PDT 24
Finished Apr 23 02:48:30 PM PDT 24
Peak memory 212072 kb
Host smart-85857d49-f7d9-4f18-99d0-b821fe514a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111977554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3111977554
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2613020
Short name T490
Test name
Test status
Simulation time 239112388 ps
CPU time 28.94 seconds
Started Apr 23 02:48:29 PM PDT 24
Finished Apr 23 02:48:59 PM PDT 24
Peak memory 245908 kb
Host smart-23867ff4-493e-4737-abd1-c544d8c7a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2613020
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3314214165
Short name T645
Test name
Test status
Simulation time 84494410 ps
CPU time 9.95 seconds
Started Apr 23 02:48:30 PM PDT 24
Finished Apr 23 02:48:40 PM PDT 24
Peak memory 251004 kb
Host smart-cb8a3ba9-da29-406b-8bbd-80975951e48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314214165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3314214165
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.12325117
Short name T22
Test name
Test status
Simulation time 694515685 ps
CPU time 12.96 seconds
Started Apr 23 02:48:33 PM PDT 24
Finished Apr 23 02:48:47 PM PDT 24
Peak memory 226832 kb
Host smart-694f034d-b9f4-4476-b896-8719124223f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12325117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.lc_ctrl_stress_all.12325117
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1291159661
Short name T780
Test name
Test status
Simulation time 24194567 ps
CPU time 0.83 seconds
Started Apr 23 02:48:32 PM PDT 24
Finished Apr 23 02:48:33 PM PDT 24
Peak memory 211720 kb
Host smart-6e9f792d-40a9-4c3c-b5d9-084225871c26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291159661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1291159661
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1102823138
Short name T327
Test name
Test status
Simulation time 22222878 ps
CPU time 1.11 seconds
Started Apr 23 02:48:38 PM PDT 24
Finished Apr 23 02:48:40 PM PDT 24
Peak memory 209576 kb
Host smart-3c9a43b2-f2b6-4896-96d6-2d573d451334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102823138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1102823138
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3587885111
Short name T289
Test name
Test status
Simulation time 291933960 ps
CPU time 12.29 seconds
Started Apr 23 02:48:33 PM PDT 24
Finished Apr 23 02:48:46 PM PDT 24
Peak memory 217996 kb
Host smart-b141a850-c247-40c3-8aea-042e5d56278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587885111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3587885111
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.180330715
Short name T663
Test name
Test status
Simulation time 355724943 ps
CPU time 1.75 seconds
Started Apr 23 02:48:33 PM PDT 24
Finished Apr 23 02:48:35 PM PDT 24
Peak memory 209552 kb
Host smart-ca69ba36-6f01-49c1-8a1c-512d7a4f748e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180330715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.180330715
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.41898342
Short name T589
Test name
Test status
Simulation time 183066160 ps
CPU time 3.28 seconds
Started Apr 23 02:48:36 PM PDT 24
Finished Apr 23 02:48:41 PM PDT 24
Peak memory 217964 kb
Host smart-c58208ed-6a3c-420c-a7b8-8a54c6bc6a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41898342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.41898342
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2272422381
Short name T244
Test name
Test status
Simulation time 268040576 ps
CPU time 13.9 seconds
Started Apr 23 02:48:36 PM PDT 24
Finished Apr 23 02:48:51 PM PDT 24
Peak memory 217972 kb
Host smart-f1b7302e-ef62-4496-a5b4-9ba63b58731e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272422381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2272422381
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2997231348
Short name T172
Test name
Test status
Simulation time 1247777389 ps
CPU time 12.01 seconds
Started Apr 23 02:48:38 PM PDT 24
Finished Apr 23 02:48:51 PM PDT 24
Peak memory 218016 kb
Host smart-a0316e7f-b132-4ca9-b307-0f74203cb357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997231348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2997231348
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.641858846
Short name T738
Test name
Test status
Simulation time 1359337258 ps
CPU time 13.12 seconds
Started Apr 23 02:48:34 PM PDT 24
Finished Apr 23 02:48:47 PM PDT 24
Peak memory 218040 kb
Host smart-c5da4a50-881d-473e-a983-a72bdff175d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641858846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.641858846
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2239667918
Short name T608
Test name
Test status
Simulation time 662326376 ps
CPU time 10.38 seconds
Started Apr 23 02:48:38 PM PDT 24
Finished Apr 23 02:48:49 PM PDT 24
Peak memory 226012 kb
Host smart-88a157ce-a2ea-4ff2-8182-1e0ef53c09f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239667918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2239667918
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2571834301
Short name T733
Test name
Test status
Simulation time 93645331 ps
CPU time 3.15 seconds
Started Apr 23 02:48:36 PM PDT 24
Finished Apr 23 02:48:40 PM PDT 24
Peak memory 214568 kb
Host smart-9c9a29ae-1aa0-4e44-83f8-42d5c26c2f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571834301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2571834301
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3874822201
Short name T715
Test name
Test status
Simulation time 602962087 ps
CPU time 20.7 seconds
Started Apr 23 02:48:35 PM PDT 24
Finished Apr 23 02:48:56 PM PDT 24
Peak memory 251080 kb
Host smart-13957c76-2fea-4165-aca3-5029548053ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874822201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3874822201
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.943771234
Short name T602
Test name
Test status
Simulation time 212007399 ps
CPU time 3.85 seconds
Started Apr 23 02:48:34 PM PDT 24
Finished Apr 23 02:48:38 PM PDT 24
Peak memory 226356 kb
Host smart-f74d5c66-3fb4-4d0c-98a2-5f3aec021e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943771234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.943771234
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3154264714
Short name T237
Test name
Test status
Simulation time 14893437918 ps
CPU time 82.3 seconds
Started Apr 23 02:48:35 PM PDT 24
Finished Apr 23 02:49:58 PM PDT 24
Peak memory 250680 kb
Host smart-61a050ce-fdd2-4340-bb9e-c7baf09dada6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154264714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3154264714
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2517990419
Short name T325
Test name
Test status
Simulation time 17514063 ps
CPU time 1.16 seconds
Started Apr 23 02:48:33 PM PDT 24
Finished Apr 23 02:48:35 PM PDT 24
Peak memory 212776 kb
Host smart-05d631b5-c3a7-4442-9326-ed39dbb0a26f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517990419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2517990419
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3329081288
Short name T359
Test name
Test status
Simulation time 108829954 ps
CPU time 1.4 seconds
Started Apr 23 02:48:41 PM PDT 24
Finished Apr 23 02:48:45 PM PDT 24
Peak memory 209552 kb
Host smart-e106a4da-efec-4dac-9e7e-b7e935a961c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329081288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3329081288
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2963356802
Short name T275
Test name
Test status
Simulation time 526914887 ps
CPU time 12.83 seconds
Started Apr 23 02:48:38 PM PDT 24
Finished Apr 23 02:48:52 PM PDT 24
Peak memory 217980 kb
Host smart-b7b5a430-46c7-4290-b8db-68e62996470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963356802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2963356802
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2837312772
Short name T691
Test name
Test status
Simulation time 2290413006 ps
CPU time 8.35 seconds
Started Apr 23 02:48:36 PM PDT 24
Finished Apr 23 02:48:46 PM PDT 24
Peak memory 209744 kb
Host smart-1e4bf5d3-a219-49ea-bea1-e7e7165a65ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837312772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2837312772
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.101252315
Short name T618
Test name
Test status
Simulation time 262241728 ps
CPU time 2.95 seconds
Started Apr 23 02:48:39 PM PDT 24
Finished Apr 23 02:48:44 PM PDT 24
Peak memory 217964 kb
Host smart-0dedfec1-bbb1-4e12-8a31-2e22e2bac0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101252315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.101252315
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.788294454
Short name T860
Test name
Test status
Simulation time 521799049 ps
CPU time 15.27 seconds
Started Apr 23 02:48:36 PM PDT 24
Finished Apr 23 02:48:52 PM PDT 24
Peak memory 226048 kb
Host smart-14137e4d-e547-464e-849d-50c69c7d299a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788294454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.788294454
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1718767254
Short name T746
Test name
Test status
Simulation time 226586930 ps
CPU time 8.74 seconds
Started Apr 23 02:48:39 PM PDT 24
Finished Apr 23 02:48:49 PM PDT 24
Peak memory 218052 kb
Host smart-974f7b50-d741-440b-aca3-9f6eed0ab99d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718767254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1718767254
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3312584286
Short name T433
Test name
Test status
Simulation time 275444076 ps
CPU time 10.83 seconds
Started Apr 23 02:48:37 PM PDT 24
Finished Apr 23 02:48:49 PM PDT 24
Peak memory 217980 kb
Host smart-b8744e70-1b98-42e7-ba67-5a95d615c819
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312584286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3312584286
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3448911910
Short name T411
Test name
Test status
Simulation time 539928474 ps
CPU time 9.26 seconds
Started Apr 23 02:48:38 PM PDT 24
Finished Apr 23 02:48:49 PM PDT 24
Peak memory 218112 kb
Host smart-3e4f1964-ed0e-4a3a-8103-68cee78f7ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448911910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3448911910
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2038886817
Short name T308
Test name
Test status
Simulation time 35928950 ps
CPU time 2.74 seconds
Started Apr 23 02:48:38 PM PDT 24
Finished Apr 23 02:48:43 PM PDT 24
Peak memory 213888 kb
Host smart-c1d73eaa-aead-4a23-bfc9-9e2e4dc84b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038886817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2038886817
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1333860840
Short name T89
Test name
Test status
Simulation time 206598711 ps
CPU time 19.29 seconds
Started Apr 23 02:48:39 PM PDT 24
Finished Apr 23 02:48:59 PM PDT 24
Peak memory 251024 kb
Host smart-387d3cca-9e3c-4862-9d1e-bd36c32495c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333860840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1333860840
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4154240706
Short name T868
Test name
Test status
Simulation time 76405988 ps
CPU time 3.17 seconds
Started Apr 23 02:48:37 PM PDT 24
Finished Apr 23 02:48:42 PM PDT 24
Peak memory 222016 kb
Host smart-0757dddf-8e54-4839-8803-ddb179049ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154240706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4154240706
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.935904041
Short name T391
Test name
Test status
Simulation time 1193093211 ps
CPU time 26.01 seconds
Started Apr 23 02:48:37 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 228496 kb
Host smart-0e5824a1-2fa2-409d-a8d7-d08278e6ca33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935904041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.935904041
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2419628077
Short name T255
Test name
Test status
Simulation time 19780965 ps
CPU time 0.99 seconds
Started Apr 23 02:48:37 PM PDT 24
Finished Apr 23 02:48:39 PM PDT 24
Peak memory 212732 kb
Host smart-76643e77-d7a6-49fe-af50-c0350e8ac945
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419628077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2419628077
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1427771802
Short name T615
Test name
Test status
Simulation time 25593786 ps
CPU time 1.28 seconds
Started Apr 23 02:48:44 PM PDT 24
Finished Apr 23 02:48:47 PM PDT 24
Peak memory 209668 kb
Host smart-da3d7546-81f3-4450-a911-7fab49922139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427771802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1427771802
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3948796945
Short name T489
Test name
Test status
Simulation time 492415624 ps
CPU time 17.89 seconds
Started Apr 23 02:48:43 PM PDT 24
Finished Apr 23 02:49:03 PM PDT 24
Peak memory 217932 kb
Host smart-6eab81b1-c65e-4417-8930-c8a388612236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948796945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3948796945
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.168467001
Short name T555
Test name
Test status
Simulation time 688221536 ps
CPU time 9.56 seconds
Started Apr 23 02:48:42 PM PDT 24
Finished Apr 23 02:48:54 PM PDT 24
Peak memory 209556 kb
Host smart-9833a710-465f-485b-a4d4-082e54414605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168467001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.168467001
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2558109410
Short name T234
Test name
Test status
Simulation time 434799854 ps
CPU time 3.95 seconds
Started Apr 23 02:48:42 PM PDT 24
Finished Apr 23 02:48:48 PM PDT 24
Peak memory 218072 kb
Host smart-e5ca7e9b-9cf4-4a4b-9ef7-e811d3175920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558109410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2558109410
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1786651691
Short name T770
Test name
Test status
Simulation time 219490680 ps
CPU time 11.02 seconds
Started Apr 23 02:48:43 PM PDT 24
Finished Apr 23 02:48:56 PM PDT 24
Peak memory 226072 kb
Host smart-fa78d881-fdc3-478d-89da-3e485bad62d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786651691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1786651691
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3252433365
Short name T222
Test name
Test status
Simulation time 1819172794 ps
CPU time 12.96 seconds
Started Apr 23 02:48:45 PM PDT 24
Finished Apr 23 02:48:59 PM PDT 24
Peak memory 218008 kb
Host smart-8c9b3e99-addc-44c5-b705-3f5bbf358bcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252433365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3252433365
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2872947371
Short name T405
Test name
Test status
Simulation time 1703533572 ps
CPU time 17.95 seconds
Started Apr 23 02:48:43 PM PDT 24
Finished Apr 23 02:49:03 PM PDT 24
Peak memory 218004 kb
Host smart-e853b5c9-6e02-46ab-a2bb-a7d2fc77b80a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872947371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2872947371
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4280204257
Short name T248
Test name
Test status
Simulation time 225622443 ps
CPU time 9.68 seconds
Started Apr 23 02:48:42 PM PDT 24
Finished Apr 23 02:48:54 PM PDT 24
Peak memory 226080 kb
Host smart-a2035cfb-a6aa-4412-abbb-b98269d53aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280204257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4280204257
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3213322661
Short name T313
Test name
Test status
Simulation time 80359612 ps
CPU time 1.44 seconds
Started Apr 23 02:48:41 PM PDT 24
Finished Apr 23 02:48:45 PM PDT 24
Peak memory 217760 kb
Host smart-59e26921-a7b6-450f-9507-17137ed6919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213322661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3213322661
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1774809166
Short name T598
Test name
Test status
Simulation time 717762868 ps
CPU time 35.23 seconds
Started Apr 23 02:48:41 PM PDT 24
Finished Apr 23 02:49:19 PM PDT 24
Peak memory 251052 kb
Host smart-675c286f-ae4a-4157-bb40-ae8b5cc093e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774809166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1774809166
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3360199856
Short name T798
Test name
Test status
Simulation time 54084265 ps
CPU time 7.23 seconds
Started Apr 23 02:48:40 PM PDT 24
Finished Apr 23 02:48:50 PM PDT 24
Peak memory 251008 kb
Host smart-9b4240f1-f0c9-442a-a726-495afed529ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360199856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3360199856
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3659716505
Short name T291
Test name
Test status
Simulation time 23478116747 ps
CPU time 362.11 seconds
Started Apr 23 02:48:44 PM PDT 24
Finished Apr 23 02:54:47 PM PDT 24
Peak memory 275712 kb
Host smart-5dfb121d-c87d-4e59-9de2-44653ae8c712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659716505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3659716505
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2175813369
Short name T206
Test name
Test status
Simulation time 64272362 ps
CPU time 0.9 seconds
Started Apr 23 02:48:40 PM PDT 24
Finished Apr 23 02:48:44 PM PDT 24
Peak memory 211612 kb
Host smart-b12a3d73-2462-42cc-953b-f38f4da6f227
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175813369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2175813369
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2840200913
Short name T249
Test name
Test status
Simulation time 26667224 ps
CPU time 1.09 seconds
Started Apr 23 02:48:53 PM PDT 24
Finished Apr 23 02:48:54 PM PDT 24
Peak memory 209584 kb
Host smart-aed45cda-f70e-4890-b879-65c16edd61db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840200913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2840200913
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2387705317
Short name T673
Test name
Test status
Simulation time 1365050894 ps
CPU time 15.86 seconds
Started Apr 23 02:48:47 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 218080 kb
Host smart-da6d198f-60f2-45e5-b79e-0f4885a1936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387705317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2387705317
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.434292762
Short name T6
Test name
Test status
Simulation time 37254940 ps
CPU time 1.71 seconds
Started Apr 23 02:48:47 PM PDT 24
Finished Apr 23 02:48:49 PM PDT 24
Peak memory 209560 kb
Host smart-d66bfc02-2fe2-487c-902c-65ffc5d837bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434292762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.434292762
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.502747603
Short name T576
Test name
Test status
Simulation time 30198894 ps
CPU time 1.85 seconds
Started Apr 23 02:48:47 PM PDT 24
Finished Apr 23 02:48:50 PM PDT 24
Peak memory 217968 kb
Host smart-9921c7e6-b2af-46d7-b3ea-efa4a0861bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502747603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.502747603
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3590194371
Short name T239
Test name
Test status
Simulation time 488547280 ps
CPU time 20.35 seconds
Started Apr 23 02:48:47 PM PDT 24
Finished Apr 23 02:49:08 PM PDT 24
Peak memory 226084 kb
Host smart-dd848c5b-9ac6-4108-b1df-12cc04c52a3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590194371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3590194371
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2870061025
Short name T782
Test name
Test status
Simulation time 245988284 ps
CPU time 11.19 seconds
Started Apr 23 02:48:48 PM PDT 24
Finished Apr 23 02:49:00 PM PDT 24
Peak memory 217956 kb
Host smart-c5714f41-b0db-47a6-9ed0-6a26dfcc1e6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870061025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2870061025
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3354944758
Short name T581
Test name
Test status
Simulation time 840292965 ps
CPU time 6.21 seconds
Started Apr 23 02:48:46 PM PDT 24
Finished Apr 23 02:48:53 PM PDT 24
Peak memory 217980 kb
Host smart-642e449e-66bb-4bda-ac89-30cd217d40e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354944758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3354944758
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3982137354
Short name T46
Test name
Test status
Simulation time 377783908 ps
CPU time 10.68 seconds
Started Apr 23 02:48:46 PM PDT 24
Finished Apr 23 02:48:58 PM PDT 24
Peak memory 218012 kb
Host smart-661a0867-2558-46bb-a593-47f3d3bafb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982137354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3982137354
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3442743267
Short name T611
Test name
Test status
Simulation time 51747921 ps
CPU time 2.45 seconds
Started Apr 23 02:48:43 PM PDT 24
Finished Apr 23 02:48:47 PM PDT 24
Peak memory 217792 kb
Host smart-d8da496d-23c4-4731-a362-58e221b2bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442743267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3442743267
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1941423721
Short name T545
Test name
Test status
Simulation time 325113282 ps
CPU time 30.5 seconds
Started Apr 23 02:48:44 PM PDT 24
Finished Apr 23 02:49:16 PM PDT 24
Peak memory 250920 kb
Host smart-cadd6e48-b4de-49ba-9fb2-089d3edc5aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941423721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1941423721
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2141493334
Short name T543
Test name
Test status
Simulation time 196045992 ps
CPU time 3.02 seconds
Started Apr 23 02:48:49 PM PDT 24
Finished Apr 23 02:48:53 PM PDT 24
Peak memory 226404 kb
Host smart-2e6bf3f5-9551-49ba-a573-58e102b2f40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141493334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2141493334
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.512066551
Short name T301
Test name
Test status
Simulation time 23541067 ps
CPU time 1.29 seconds
Started Apr 23 02:48:44 PM PDT 24
Finished Apr 23 02:48:47 PM PDT 24
Peak memory 213072 kb
Host smart-6a707fb0-59ba-40eb-9c59-fc7dcdcddd36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512066551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.512066551
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2042618321
Short name T57
Test name
Test status
Simulation time 100396224 ps
CPU time 0.92 seconds
Started Apr 23 02:48:55 PM PDT 24
Finished Apr 23 02:48:56 PM PDT 24
Peak memory 209608 kb
Host smart-f465454d-f972-4d09-befc-7e412f2a4355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042618321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2042618321
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2299729064
Short name T548
Test name
Test status
Simulation time 2805197498 ps
CPU time 18.1 seconds
Started Apr 23 02:48:51 PM PDT 24
Finished Apr 23 02:49:09 PM PDT 24
Peak memory 217920 kb
Host smart-f89d7170-75f6-4d7d-bd40-08f3fce156c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299729064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2299729064
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.4269731470
Short name T604
Test name
Test status
Simulation time 4425376286 ps
CPU time 11.13 seconds
Started Apr 23 02:48:50 PM PDT 24
Finished Apr 23 02:49:02 PM PDT 24
Peak memory 209652 kb
Host smart-3afe0418-6aa3-4376-acf9-679858d494c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269731470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.4269731470
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3072879880
Short name T250
Test name
Test status
Simulation time 388382900 ps
CPU time 3.31 seconds
Started Apr 23 02:48:50 PM PDT 24
Finished Apr 23 02:48:54 PM PDT 24
Peak memory 218004 kb
Host smart-0985e9b2-b3b1-4d3d-9a28-07a6914622c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072879880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3072879880
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4049559792
Short name T644
Test name
Test status
Simulation time 731422461 ps
CPU time 10.3 seconds
Started Apr 23 02:48:51 PM PDT 24
Finished Apr 23 02:49:02 PM PDT 24
Peak memory 218936 kb
Host smart-45f8afb3-8b8d-4c36-a843-7b1e82f8b3f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049559792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4049559792
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4002204930
Short name T592
Test name
Test status
Simulation time 1395690667 ps
CPU time 13.04 seconds
Started Apr 23 02:48:50 PM PDT 24
Finished Apr 23 02:49:03 PM PDT 24
Peak memory 218016 kb
Host smart-8df20bb4-fc1c-42b9-968a-75a1febd5be0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002204930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4002204930
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2150533832
Short name T49
Test name
Test status
Simulation time 422376578 ps
CPU time 11.33 seconds
Started Apr 23 02:48:55 PM PDT 24
Finished Apr 23 02:49:06 PM PDT 24
Peak memory 217960 kb
Host smart-f6734ec1-638c-4810-b572-a48df4ae58c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150533832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2150533832
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.526678671
Short name T586
Test name
Test status
Simulation time 4829798282 ps
CPU time 13.88 seconds
Started Apr 23 02:48:50 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 218028 kb
Host smart-807bd871-2872-49d3-8f7f-3e46480053b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526678671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.526678671
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2861864133
Short name T842
Test name
Test status
Simulation time 352140297 ps
CPU time 3.73 seconds
Started Apr 23 02:48:53 PM PDT 24
Finished Apr 23 02:48:57 PM PDT 24
Peak memory 214104 kb
Host smart-138e05f9-32d8-4456-9f90-9483d94eeca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861864133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2861864133
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3455977108
Short name T717
Test name
Test status
Simulation time 749227785 ps
CPU time 34.97 seconds
Started Apr 23 02:48:53 PM PDT 24
Finished Apr 23 02:49:28 PM PDT 24
Peak memory 250860 kb
Host smart-1d72d129-92e9-4d56-b7b4-9c5b0ddf862e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455977108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3455977108
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1257481072
Short name T174
Test name
Test status
Simulation time 119479460 ps
CPU time 6.38 seconds
Started Apr 23 02:48:47 PM PDT 24
Finished Apr 23 02:48:54 PM PDT 24
Peak memory 250792 kb
Host smart-24f9d863-eeec-4c90-abd7-ce861281e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257481072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1257481072
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2632303444
Short name T560
Test name
Test status
Simulation time 2861693023 ps
CPU time 103.02 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:50:40 PM PDT 24
Peak memory 227020 kb
Host smart-7911b8e0-58ae-45cc-8167-50aabb73af7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632303444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2632303444
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3352466451
Short name T793
Test name
Test status
Simulation time 12147457 ps
CPU time 0.75 seconds
Started Apr 23 02:48:48 PM PDT 24
Finished Apr 23 02:48:50 PM PDT 24
Peak memory 207896 kb
Host smart-114fd4c2-aae5-48cd-9b6c-7730185eab9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352466451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3352466451
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2815234165
Short name T381
Test name
Test status
Simulation time 28820440 ps
CPU time 1 seconds
Started Apr 23 02:48:57 PM PDT 24
Finished Apr 23 02:48:58 PM PDT 24
Peak memory 209568 kb
Host smart-7031bfe4-5cff-4179-bb78-d61dfbb6e458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815234165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2815234165
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2164219937
Short name T636
Test name
Test status
Simulation time 356841530 ps
CPU time 15.76 seconds
Started Apr 23 02:48:54 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 218068 kb
Host smart-a98519b4-a041-49e5-9bc5-6f8a06def567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164219937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2164219937
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3332750473
Short name T725
Test name
Test status
Simulation time 721433660 ps
CPU time 9.45 seconds
Started Apr 23 02:48:55 PM PDT 24
Finished Apr 23 02:49:05 PM PDT 24
Peak memory 209564 kb
Host smart-f362d6da-78c8-45b7-94da-6fb9dae5d014
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332750473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3332750473
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.4249507197
Short name T315
Test name
Test status
Simulation time 258116319 ps
CPU time 3.3 seconds
Started Apr 23 02:48:55 PM PDT 24
Finished Apr 23 02:48:59 PM PDT 24
Peak memory 218004 kb
Host smart-02685946-b3fb-45da-b384-1c593693d97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249507197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.4249507197
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.271285516
Short name T346
Test name
Test status
Simulation time 688320314 ps
CPU time 11.31 seconds
Started Apr 23 02:48:54 PM PDT 24
Finished Apr 23 02:49:06 PM PDT 24
Peak memory 226064 kb
Host smart-1f6a42f0-c69a-4bd1-8c90-28c5e0fc73cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271285516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.271285516
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1290655234
Short name T681
Test name
Test status
Simulation time 631819087 ps
CPU time 14.03 seconds
Started Apr 23 02:48:53 PM PDT 24
Finished Apr 23 02:49:07 PM PDT 24
Peak memory 217984 kb
Host smart-e58033cd-6c03-473d-a11a-b05ac08cf4a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290655234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1290655234
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1046790670
Short name T804
Test name
Test status
Simulation time 274158843 ps
CPU time 12.07 seconds
Started Apr 23 02:48:53 PM PDT 24
Finished Apr 23 02:49:06 PM PDT 24
Peak memory 218020 kb
Host smart-df9a34b5-b461-4066-b8b3-a46773d6953a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046790670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1046790670
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3043119733
Short name T357
Test name
Test status
Simulation time 1033902144 ps
CPU time 12.42 seconds
Started Apr 23 02:48:54 PM PDT 24
Finished Apr 23 02:49:07 PM PDT 24
Peak memory 218060 kb
Host smart-8e2c1fe0-4fe9-4a46-a57a-947b1cb35545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043119733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3043119733
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3715421878
Short name T66
Test name
Test status
Simulation time 63371031 ps
CPU time 3.43 seconds
Started Apr 23 02:48:54 PM PDT 24
Finished Apr 23 02:48:58 PM PDT 24
Peak memory 217956 kb
Host smart-90254b9a-9670-4bdb-8400-382bb575f2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715421878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3715421878
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2550404288
Short name T300
Test name
Test status
Simulation time 348167920 ps
CPU time 21.2 seconds
Started Apr 23 02:48:50 PM PDT 24
Finished Apr 23 02:49:12 PM PDT 24
Peak memory 250720 kb
Host smart-439d0e81-2fa4-4468-8e78-3eb010e97232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550404288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2550404288
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3548955048
Short name T208
Test name
Test status
Simulation time 50056194 ps
CPU time 7.18 seconds
Started Apr 23 02:48:54 PM PDT 24
Finished Apr 23 02:49:02 PM PDT 24
Peak memory 246212 kb
Host smart-6bab696d-d703-4ef5-9239-511e0eb94386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548955048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3548955048
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3814125399
Short name T866
Test name
Test status
Simulation time 11580184870 ps
CPU time 244.55 seconds
Started Apr 23 02:48:57 PM PDT 24
Finished Apr 23 02:53:02 PM PDT 24
Peak memory 320824 kb
Host smart-48bebc76-54f0-4452-a16f-71af10809a8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814125399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3814125399
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2822669822
Short name T337
Test name
Test status
Simulation time 31085912 ps
CPU time 0.8 seconds
Started Apr 23 02:48:52 PM PDT 24
Finished Apr 23 02:48:53 PM PDT 24
Peak memory 211724 kb
Host smart-ababc760-1982-435c-ba3f-495c68987215
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822669822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2822669822
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4168790035
Short name T515
Test name
Test status
Simulation time 47161658 ps
CPU time 0.94 seconds
Started Apr 23 02:48:55 PM PDT 24
Finished Apr 23 02:48:57 PM PDT 24
Peak memory 209516 kb
Host smart-a69b2f33-5659-40f9-86e4-88826b6fdd10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168790035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4168790035
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3970655269
Short name T383
Test name
Test status
Simulation time 688724633 ps
CPU time 12.01 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:49:08 PM PDT 24
Peak memory 217992 kb
Host smart-85a19b21-1203-4e8f-93c9-7e034fdcc3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970655269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3970655269
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.456645243
Short name T408
Test name
Test status
Simulation time 287560038 ps
CPU time 3.94 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:49:01 PM PDT 24
Peak memory 209556 kb
Host smart-8a129605-ed92-4361-9d44-47e424151b23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456645243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.456645243
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2168148949
Short name T277
Test name
Test status
Simulation time 91431694 ps
CPU time 1.91 seconds
Started Apr 23 02:49:03 PM PDT 24
Finished Apr 23 02:49:05 PM PDT 24
Peak memory 218012 kb
Host smart-27a91022-46ea-4db4-9aa5-910b6a3a9311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168148949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2168148949
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2892959345
Short name T319
Test name
Test status
Simulation time 857233527 ps
CPU time 12.7 seconds
Started Apr 23 02:48:55 PM PDT 24
Finished Apr 23 02:49:08 PM PDT 24
Peak memory 226060 kb
Host smart-b9c7e635-21d8-450e-8bcf-643205c27e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892959345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2892959345
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.401401679
Short name T847
Test name
Test status
Simulation time 2634296514 ps
CPU time 13.23 seconds
Started Apr 23 02:48:57 PM PDT 24
Finished Apr 23 02:49:11 PM PDT 24
Peak memory 218068 kb
Host smart-dad3c72f-e8fc-4676-b641-199ed8d4840d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401401679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.401401679
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2729323339
Short name T718
Test name
Test status
Simulation time 1022723705 ps
CPU time 7.58 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 218048 kb
Host smart-4ab47ddb-4a3e-4536-bd45-75fc848c0150
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729323339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2729323339
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4186722250
Short name T371
Test name
Test status
Simulation time 1912579675 ps
CPU time 12.65 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 226108 kb
Host smart-38aad5d2-20e9-49d8-b2e7-fce310bd0f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186722250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4186722250
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3821651125
Short name T9
Test name
Test status
Simulation time 88330352 ps
CPU time 1.36 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:48:58 PM PDT 24
Peak memory 213428 kb
Host smart-28b9f081-f78d-4157-ac5d-bf28fb830735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821651125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3821651125
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2273635619
Short name T756
Test name
Test status
Simulation time 343040608 ps
CPU time 38.62 seconds
Started Apr 23 02:48:57 PM PDT 24
Finished Apr 23 02:49:36 PM PDT 24
Peak memory 251080 kb
Host smart-46e740f6-59ac-44e1-9f0a-21ffaf9efe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273635619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2273635619
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3524003659
Short name T627
Test name
Test status
Simulation time 97397758 ps
CPU time 3.32 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:49:00 PM PDT 24
Peak memory 222092 kb
Host smart-03852a2e-408e-4c33-a523-9674d09f6abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524003659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3524003659
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1582751340
Short name T781
Test name
Test status
Simulation time 42446549197 ps
CPU time 357.94 seconds
Started Apr 23 02:48:57 PM PDT 24
Finished Apr 23 02:54:56 PM PDT 24
Peak memory 259152 kb
Host smart-cbcf11b3-c7cb-4f2f-b697-d79b140d805b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582751340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1582751340
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2281283750
Short name T80
Test name
Test status
Simulation time 38403381 ps
CPU time 0.89 seconds
Started Apr 23 02:48:56 PM PDT 24
Finished Apr 23 02:48:57 PM PDT 24
Peak memory 212996 kb
Host smart-b72119e6-20d1-49a2-9767-91959b637ab4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281283750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2281283750
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2317195458
Short name T251
Test name
Test status
Simulation time 15785252 ps
CPU time 1.04 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:04 PM PDT 24
Peak memory 209576 kb
Host smart-b08dd969-0254-44e5-b38c-458177730656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317195458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2317195458
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2365335289
Short name T412
Test name
Test status
Simulation time 20410993 ps
CPU time 0.92 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:04 PM PDT 24
Peak memory 209580 kb
Host smart-9fee95dd-c8bf-443d-a204-a84c96158021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365335289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2365335289
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2045147240
Short name T597
Test name
Test status
Simulation time 697526943 ps
CPU time 18.5 seconds
Started Apr 23 02:47:02 PM PDT 24
Finished Apr 23 02:47:21 PM PDT 24
Peak memory 217992 kb
Host smart-c8d0b6ba-7099-4f94-81ac-0e5eb7c95f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045147240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2045147240
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4111994164
Short name T25
Test name
Test status
Simulation time 2952962280 ps
CPU time 17.01 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:20 PM PDT 24
Peak memory 209728 kb
Host smart-a2b2793d-2ed0-4715-9bca-5e560f84ad51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111994164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4111994164
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2773023884
Short name T302
Test name
Test status
Simulation time 1836448077 ps
CPU time 21.78 seconds
Started Apr 23 02:47:02 PM PDT 24
Finished Apr 23 02:47:25 PM PDT 24
Peak memory 217984 kb
Host smart-9b0a4c0c-f1b5-4a3c-b9a9-55150588fc56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773023884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2773023884
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.53638424
Short name T873
Test name
Test status
Simulation time 178887552 ps
CPU time 2.89 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:07 PM PDT 24
Peak memory 217104 kb
Host smart-2375c9f7-b6bd-4a78-9126-dfaaccae189a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53638424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.53638424
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1742520196
Short name T478
Test name
Test status
Simulation time 597978715 ps
CPU time 8.2 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:12 PM PDT 24
Peak memory 217976 kb
Host smart-be42e7a8-76c8-4b2f-baed-ec0a528ce057
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742520196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1742520196
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1361624381
Short name T62
Test name
Test status
Simulation time 2671074138 ps
CPU time 18.06 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:21 PM PDT 24
Peak memory 213620 kb
Host smart-14e1f760-f62b-4c04-898b-bbacbfdd5358
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361624381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1361624381
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4036100678
Short name T418
Test name
Test status
Simulation time 644796649 ps
CPU time 6.95 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:10 PM PDT 24
Peak memory 213832 kb
Host smart-adb258f5-aeac-487c-a3b9-6fb8f7bc8846
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036100678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4036100678
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1738339436
Short name T716
Test name
Test status
Simulation time 1875548123 ps
CPU time 50.33 seconds
Started Apr 23 02:47:02 PM PDT 24
Finished Apr 23 02:47:53 PM PDT 24
Peak memory 275600 kb
Host smart-0d2ec7d9-65a0-4bfa-802d-43a8f0566ee2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738339436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1738339436
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1493196531
Short name T166
Test name
Test status
Simulation time 491441632 ps
CPU time 9.21 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 223188 kb
Host smart-cb664148-e1df-41e9-a25a-16842e86508c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493196531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1493196531
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4233270119
Short name T311
Test name
Test status
Simulation time 131659743 ps
CPU time 2.59 seconds
Started Apr 23 02:46:58 PM PDT 24
Finished Apr 23 02:47:01 PM PDT 24
Peak memory 217964 kb
Host smart-324c365f-dbf8-406d-804c-ab3e54beaec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233270119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4233270119
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1527676101
Short name T68
Test name
Test status
Simulation time 1358266675 ps
CPU time 18.02 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:22 PM PDT 24
Peak memory 218036 kb
Host smart-47fd738d-df23-4ad2-9085-9e4db42af23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527676101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1527676101
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2077458480
Short name T44
Test name
Test status
Simulation time 794650549 ps
CPU time 33.32 seconds
Started Apr 23 02:47:04 PM PDT 24
Finished Apr 23 02:47:38 PM PDT 24
Peak memory 284460 kb
Host smart-21880d2b-559c-4aa6-8e71-74010dff2d70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077458480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2077458480
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.679368318
Short name T774
Test name
Test status
Simulation time 682698609 ps
CPU time 9.28 seconds
Started Apr 23 02:47:02 PM PDT 24
Finished Apr 23 02:47:12 PM PDT 24
Peak memory 225584 kb
Host smart-cc44278a-3d35-4951-9fd6-e263577b99b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679368318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.679368318
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1721096007
Short name T822
Test name
Test status
Simulation time 371272769 ps
CPU time 9.88 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 217968 kb
Host smart-78bfe600-2900-4510-9084-20a187b52663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721096007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1721096007
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1672924146
Short name T386
Test name
Test status
Simulation time 2047566527 ps
CPU time 17.67 seconds
Started Apr 23 02:47:01 PM PDT 24
Finished Apr 23 02:47:20 PM PDT 24
Peak memory 217952 kb
Host smart-cd8e82f2-448c-45ce-b9da-8ce7685e91b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672924146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
672924146
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.145897510
Short name T712
Test name
Test status
Simulation time 462160605 ps
CPU time 9.51 seconds
Started Apr 23 02:47:03 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 218028 kb
Host smart-e95fdb27-9a21-4d4c-94f8-61d8b02d25f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145897510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.145897510
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.466442673
Short name T427
Test name
Test status
Simulation time 21585490 ps
CPU time 1.88 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:08 PM PDT 24
Peak memory 213864 kb
Host smart-f0a1da90-d31e-4173-a422-29a736219860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466442673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.466442673
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1330165085
Short name T388
Test name
Test status
Simulation time 191272388 ps
CPU time 22.03 seconds
Started Apr 23 02:46:58 PM PDT 24
Finished Apr 23 02:47:21 PM PDT 24
Peak memory 251020 kb
Host smart-8d71adfb-cc2b-4c93-a2d0-dcab5d1fab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330165085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1330165085
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1928214238
Short name T236
Test name
Test status
Simulation time 222799211 ps
CPU time 2.71 seconds
Started Apr 23 02:47:01 PM PDT 24
Finished Apr 23 02:47:04 PM PDT 24
Peak memory 224484 kb
Host smart-ab38fb1a-7e75-4972-9104-22d828d82de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928214238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1928214238
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3443431363
Short name T160
Test name
Test status
Simulation time 38948358111 ps
CPU time 180.91 seconds
Started Apr 23 02:47:04 PM PDT 24
Finished Apr 23 02:50:06 PM PDT 24
Peak memory 251084 kb
Host smart-d0aad432-e9db-4a9f-bbe8-9e9518bffe0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443431363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3443431363
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1622925898
Short name T525
Test name
Test status
Simulation time 29848434 ps
CPU time 0.96 seconds
Started Apr 23 02:46:59 PM PDT 24
Finished Apr 23 02:47:00 PM PDT 24
Peak memory 211528 kb
Host smart-3a0b7571-697b-4469-b461-43d45bfb9f54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622925898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1622925898
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2601163719
Short name T783
Test name
Test status
Simulation time 58000300 ps
CPU time 1.06 seconds
Started Apr 23 02:48:59 PM PDT 24
Finished Apr 23 02:49:00 PM PDT 24
Peak memory 209532 kb
Host smart-0ed3203f-6789-4bc9-b1cd-23afccc25f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601163719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2601163719
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4186630220
Short name T653
Test name
Test status
Simulation time 1161355941 ps
CPU time 7.97 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:09 PM PDT 24
Peak memory 218032 kb
Host smart-d059517f-53cd-407e-91af-1a9d72fef2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186630220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4186630220
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1678033843
Short name T564
Test name
Test status
Simulation time 355452147 ps
CPU time 2.98 seconds
Started Apr 23 02:48:59 PM PDT 24
Finished Apr 23 02:49:02 PM PDT 24
Peak memory 209552 kb
Host smart-a29913b0-b59b-4764-976d-519bb96c946c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678033843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1678033843
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3566207584
Short name T378
Test name
Test status
Simulation time 53931586 ps
CPU time 2.96 seconds
Started Apr 23 02:49:08 PM PDT 24
Finished Apr 23 02:49:11 PM PDT 24
Peak memory 217984 kb
Host smart-5504ea12-c8c3-4882-8e20-93e9770ce1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566207584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3566207584
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1042165474
Short name T423
Test name
Test status
Simulation time 1592558052 ps
CPU time 14.81 seconds
Started Apr 23 02:49:01 PM PDT 24
Finished Apr 23 02:49:16 PM PDT 24
Peak memory 226088 kb
Host smart-c2b32617-44d6-4231-b63f-3c66d1bac00f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042165474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1042165474
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2794752080
Short name T789
Test name
Test status
Simulation time 1349502560 ps
CPU time 10.77 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:11 PM PDT 24
Peak memory 217972 kb
Host smart-a9fb1697-fc36-471e-8d8b-1bcba430e7a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794752080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2794752080
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3815977639
Short name T338
Test name
Test status
Simulation time 743121500 ps
CPU time 10.01 seconds
Started Apr 23 02:48:59 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 217996 kb
Host smart-3c4716e2-4b9c-4920-bf1e-a0a16fd5205a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815977639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3815977639
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.448068398
Short name T859
Test name
Test status
Simulation time 556203652 ps
CPU time 10.17 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:11 PM PDT 24
Peak memory 218080 kb
Host smart-c593ff18-d53e-4696-89a3-df185c5043f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448068398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.448068398
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3338197705
Short name T748
Test name
Test status
Simulation time 70058322 ps
CPU time 2.71 seconds
Started Apr 23 02:48:59 PM PDT 24
Finished Apr 23 02:49:02 PM PDT 24
Peak memory 214388 kb
Host smart-2c0e56cc-d77d-49d8-8e25-85a83cb83181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338197705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3338197705
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.240308178
Short name T465
Test name
Test status
Simulation time 233036453 ps
CPU time 8.48 seconds
Started Apr 23 02:48:59 PM PDT 24
Finished Apr 23 02:49:08 PM PDT 24
Peak memory 250992 kb
Host smart-174264ae-ed35-447a-a17c-b50afc768147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240308178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.240308178
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.135139481
Short name T809
Test name
Test status
Simulation time 746976655 ps
CPU time 21.63 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:22 PM PDT 24
Peak memory 250736 kb
Host smart-9db9b302-2b93-4240-b147-3d9ea4174ac4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135139481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.135139481
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3750675968
Short name T129
Test name
Test status
Simulation time 16685661459 ps
CPU time 728.43 seconds
Started Apr 23 02:49:03 PM PDT 24
Finished Apr 23 03:01:12 PM PDT 24
Peak memory 496936 kb
Host smart-f73d07f3-e0e8-46ac-9ff8-d7e047c23298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3750675968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3750675968
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1978798283
Short name T821
Test name
Test status
Simulation time 32129230 ps
CPU time 0.82 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:01 PM PDT 24
Peak memory 211664 kb
Host smart-87bea725-486b-432b-ae54-1eb77fc124a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978798283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1978798283
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1847767982
Short name T252
Test name
Test status
Simulation time 100529468 ps
CPU time 0.88 seconds
Started Apr 23 02:49:09 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 209372 kb
Host smart-d73c292f-4334-4626-924e-c61b73266780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847767982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1847767982
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2032904467
Short name T476
Test name
Test status
Simulation time 238275483 ps
CPU time 10.26 seconds
Started Apr 23 02:49:09 PM PDT 24
Finished Apr 23 02:49:20 PM PDT 24
Peak memory 218032 kb
Host smart-5cf78b1b-ca7d-4396-85b9-86e1e638a2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032904467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2032904467
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2410198604
Short name T181
Test name
Test status
Simulation time 1456347396 ps
CPU time 6.07 seconds
Started Apr 23 02:49:04 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 209592 kb
Host smart-9c7f78a0-35b8-4e6a-9804-23a32245d2de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410198604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2410198604
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3900133750
Short name T817
Test name
Test status
Simulation time 413834797 ps
CPU time 3.44 seconds
Started Apr 23 02:49:05 PM PDT 24
Finished Apr 23 02:49:09 PM PDT 24
Peak memory 217964 kb
Host smart-bcc05277-ed16-44e0-bfee-eead0f13a249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900133750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3900133750
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2495876032
Short name T51
Test name
Test status
Simulation time 394422201 ps
CPU time 13.67 seconds
Started Apr 23 02:49:10 PM PDT 24
Finished Apr 23 02:49:24 PM PDT 24
Peak memory 226084 kb
Host smart-52d2c0bc-5290-469c-b55a-35be14e8ae11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495876032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2495876032
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3340302043
Short name T477
Test name
Test status
Simulation time 1004394118 ps
CPU time 11.96 seconds
Started Apr 23 02:49:05 PM PDT 24
Finished Apr 23 02:49:17 PM PDT 24
Peak memory 217972 kb
Host smart-50c4e8c4-69a3-44b5-a13c-1533bfa3c520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340302043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3340302043
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2171449767
Short name T865
Test name
Test status
Simulation time 228313936 ps
CPU time 7.73 seconds
Started Apr 23 02:49:03 PM PDT 24
Finished Apr 23 02:49:11 PM PDT 24
Peak memory 217972 kb
Host smart-be3c1720-9f68-4b36-9786-109a96e76402
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171449767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2171449767
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3632856519
Short name T503
Test name
Test status
Simulation time 76868946 ps
CPU time 3.01 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 214572 kb
Host smart-d21cba12-cf4f-4a72-a90e-27e786edbff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632856519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3632856519
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2889583529
Short name T850
Test name
Test status
Simulation time 218534600 ps
CPU time 27.3 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:28 PM PDT 24
Peak memory 251008 kb
Host smart-409a5aa7-b975-496c-85a5-a8bdaf6b7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889583529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2889583529
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2621115372
Short name T240
Test name
Test status
Simulation time 111155697 ps
CPU time 8.54 seconds
Started Apr 23 02:49:00 PM PDT 24
Finished Apr 23 02:49:09 PM PDT 24
Peak memory 250384 kb
Host smart-be59f668-f9d1-48ed-8601-9dca4a4aa5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621115372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2621115372
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3338389545
Short name T146
Test name
Test status
Simulation time 36328058578 ps
CPU time 141.06 seconds
Started Apr 23 02:49:04 PM PDT 24
Finished Apr 23 02:51:25 PM PDT 24
Peak memory 270660 kb
Host smart-f126f5a7-b6fe-44cb-b452-84c3a3871336
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338389545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3338389545
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3211128340
Short name T407
Test name
Test status
Simulation time 63024550 ps
CPU time 1.33 seconds
Started Apr 23 02:49:01 PM PDT 24
Finished Apr 23 02:49:03 PM PDT 24
Peak memory 213040 kb
Host smart-cf5bbfb8-8dfa-48a9-8419-597130da5c7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211128340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3211128340
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3674751737
Short name T700
Test name
Test status
Simulation time 64869176 ps
CPU time 0.85 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:14 PM PDT 24
Peak memory 209572 kb
Host smart-18a447ab-d561-4d41-a709-67b2634978c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674751737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3674751737
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3960509691
Short name T150
Test name
Test status
Simulation time 312092391 ps
CPU time 9.06 seconds
Started Apr 23 02:49:11 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 217988 kb
Host smart-f022531d-80ec-46cc-8f20-f97a451667e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960509691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3960509691
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.4252658120
Short name T837
Test name
Test status
Simulation time 1585958640 ps
CPU time 6.82 seconds
Started Apr 23 02:49:07 PM PDT 24
Finished Apr 23 02:49:15 PM PDT 24
Peak memory 209620 kb
Host smart-575e0364-d534-4df7-b0e2-2d2c9dcbdf9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252658120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.4252658120
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3765868716
Short name T280
Test name
Test status
Simulation time 471637462 ps
CPU time 2.73 seconds
Started Apr 23 02:49:09 PM PDT 24
Finished Apr 23 02:49:12 PM PDT 24
Peak memory 217936 kb
Host smart-cbb135a5-ad49-402d-bc4d-dbaeb0968d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765868716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3765868716
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1873447861
Short name T628
Test name
Test status
Simulation time 1991324513 ps
CPU time 12.37 seconds
Started Apr 23 02:49:08 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 226080 kb
Host smart-6a360b4b-66e9-4110-b29d-923b024ea2fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873447861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1873447861
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.730103188
Short name T439
Test name
Test status
Simulation time 303477967 ps
CPU time 9.6 seconds
Started Apr 23 02:49:11 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 218008 kb
Host smart-260b2c0b-ebba-421f-a289-0aa768a65193
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730103188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.730103188
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2883850556
Short name T389
Test name
Test status
Simulation time 1146177300 ps
CPU time 6.34 seconds
Started Apr 23 02:49:06 PM PDT 24
Finished Apr 23 02:49:13 PM PDT 24
Peak memory 217984 kb
Host smart-0ddbd908-c808-4a67-9467-9b3d50aa2e7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883850556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2883850556
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2389897512
Short name T828
Test name
Test status
Simulation time 6055833002 ps
CPU time 11.47 seconds
Started Apr 23 02:49:08 PM PDT 24
Finished Apr 23 02:49:20 PM PDT 24
Peak memory 218128 kb
Host smart-a7be665d-70bf-4c82-81da-f504b5d62c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389897512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2389897512
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2853797750
Short name T600
Test name
Test status
Simulation time 43666516 ps
CPU time 1.35 seconds
Started Apr 23 02:49:02 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 213432 kb
Host smart-ca05e904-3f58-4538-8cb8-b610a5f6afe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853797750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2853797750
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3426017477
Short name T229
Test name
Test status
Simulation time 1183238414 ps
CPU time 23.85 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:37 PM PDT 24
Peak memory 250568 kb
Host smart-35c4facc-8cad-436f-9f21-385f865178ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426017477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3426017477
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1827656952
Short name T839
Test name
Test status
Simulation time 363031862 ps
CPU time 8.96 seconds
Started Apr 23 02:49:09 PM PDT 24
Finished Apr 23 02:49:18 PM PDT 24
Peak memory 251016 kb
Host smart-d7a0c429-64e7-4e70-97d1-4098bf074e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827656952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1827656952
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1084347656
Short name T665
Test name
Test status
Simulation time 10094932860 ps
CPU time 229.59 seconds
Started Apr 23 02:49:07 PM PDT 24
Finished Apr 23 02:52:57 PM PDT 24
Peak memory 247132 kb
Host smart-fa5903a2-5105-4af4-976b-2d8670b478df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084347656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1084347656
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.663764465
Short name T232
Test name
Test status
Simulation time 14366701 ps
CPU time 0.98 seconds
Started Apr 23 02:49:06 PM PDT 24
Finished Apr 23 02:49:08 PM PDT 24
Peak memory 211596 kb
Host smart-db59b456-92ee-4e84-a0e6-f1a83b18045d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663764465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.663764465
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3976619073
Short name T372
Test name
Test status
Simulation time 16474247 ps
CPU time 0.89 seconds
Started Apr 23 02:49:11 PM PDT 24
Finished Apr 23 02:49:13 PM PDT 24
Peak memory 209576 kb
Host smart-aa4798fe-2e89-4ce5-95d9-b1e78878419f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976619073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3976619073
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2207620631
Short name T138
Test name
Test status
Simulation time 2379235948 ps
CPU time 15.18 seconds
Started Apr 23 02:49:07 PM PDT 24
Finished Apr 23 02:49:22 PM PDT 24
Peak memory 218036 kb
Host smart-2c3eaf40-8e56-44c8-afa8-9da35fca0bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207620631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2207620631
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.488113826
Short name T537
Test name
Test status
Simulation time 217095534 ps
CPU time 2.89 seconds
Started Apr 23 02:49:07 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 209572 kb
Host smart-93f5e56f-4996-4d3e-87b4-7856e4883af2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488113826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.488113826
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2735279414
Short name T552
Test name
Test status
Simulation time 67216237 ps
CPU time 2.51 seconds
Started Apr 23 02:49:06 PM PDT 24
Finished Apr 23 02:49:09 PM PDT 24
Peak memory 217964 kb
Host smart-dba09d45-7a43-418a-b534-a94d29ef8082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735279414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2735279414
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.141102419
Short name T366
Test name
Test status
Simulation time 280423374 ps
CPU time 9.56 seconds
Started Apr 23 02:49:05 PM PDT 24
Finished Apr 23 02:49:15 PM PDT 24
Peak memory 218968 kb
Host smart-1dbae3ae-7ca0-4356-b0e7-1d025b2197bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141102419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.141102419
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1312604017
Short name T464
Test name
Test status
Simulation time 453679341 ps
CPU time 9.7 seconds
Started Apr 23 02:49:10 PM PDT 24
Finished Apr 23 02:49:20 PM PDT 24
Peak memory 218008 kb
Host smart-b8cfe414-4593-48dc-bd6e-2dfa6a8f1507
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312604017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1312604017
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3598462377
Short name T320
Test name
Test status
Simulation time 343097897 ps
CPU time 8.16 seconds
Started Apr 23 02:49:10 PM PDT 24
Finished Apr 23 02:49:19 PM PDT 24
Peak memory 218000 kb
Host smart-e3041b7f-301c-4b56-87b8-9882ce58cea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598462377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3598462377
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3341822589
Short name T795
Test name
Test status
Simulation time 320744633 ps
CPU time 13.04 seconds
Started Apr 23 02:49:06 PM PDT 24
Finished Apr 23 02:49:20 PM PDT 24
Peak memory 225088 kb
Host smart-0f417195-6c2d-4e5d-8f40-f70bb04cdf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341822589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3341822589
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2993588161
Short name T55
Test name
Test status
Simulation time 16917305 ps
CPU time 1.09 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:15 PM PDT 24
Peak memory 209536 kb
Host smart-4788a98c-47d8-41ca-889c-23d9a6fb93e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993588161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2993588161
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.929990815
Short name T444
Test name
Test status
Simulation time 473324909 ps
CPU time 30.33 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:44 PM PDT 24
Peak memory 245472 kb
Host smart-699dbf99-0d9a-4ba4-896b-9b614ed11541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929990815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.929990815
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1679284571
Short name T258
Test name
Test status
Simulation time 285294559 ps
CPU time 3.26 seconds
Started Apr 23 02:49:09 PM PDT 24
Finished Apr 23 02:49:13 PM PDT 24
Peak memory 222352 kb
Host smart-bd3229fb-2bec-49d5-82e2-7e34bd80608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679284571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1679284571
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.33311849
Short name T101
Test name
Test status
Simulation time 91918404537 ps
CPU time 429.81 seconds
Started Apr 23 02:49:11 PM PDT 24
Finished Apr 23 02:56:21 PM PDT 24
Peak memory 389392 kb
Host smart-c9fc4ab6-0226-4b4c-bf32-96cf8756cb0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=33311849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.33311849
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3440809986
Short name T652
Test name
Test status
Simulation time 45286772 ps
CPU time 0.8 seconds
Started Apr 23 02:49:08 PM PDT 24
Finished Apr 23 02:49:09 PM PDT 24
Peak memory 211612 kb
Host smart-563adbb0-3020-485d-9092-b94f1a593562
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440809986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3440809986
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1199340766
Short name T361
Test name
Test status
Simulation time 40994281 ps
CPU time 0.98 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:49:14 PM PDT 24
Peak memory 209580 kb
Host smart-a0982c7d-8ae2-4bed-be79-4f9a2842684c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199340766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1199340766
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1591773637
Short name T453
Test name
Test status
Simulation time 193035112 ps
CPU time 9.86 seconds
Started Apr 23 02:49:14 PM PDT 24
Finished Apr 23 02:49:25 PM PDT 24
Peak memory 217916 kb
Host smart-390a5ee1-0b5c-40d1-bc01-6293bad76a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591773637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1591773637
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2582606939
Short name T670
Test name
Test status
Simulation time 470729802 ps
CPU time 2.14 seconds
Started Apr 23 02:49:14 PM PDT 24
Finished Apr 23 02:49:17 PM PDT 24
Peak memory 209628 kb
Host smart-49addbd1-430b-4a94-9b5d-869a3f3fbfcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582606939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2582606939
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2698269684
Short name T83
Test name
Test status
Simulation time 21472974 ps
CPU time 1.58 seconds
Started Apr 23 02:49:10 PM PDT 24
Finished Apr 23 02:49:12 PM PDT 24
Peak memory 217924 kb
Host smart-d5f276f3-dc79-416e-acca-b9f47c482c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698269684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2698269684
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3077182879
Short name T666
Test name
Test status
Simulation time 1970240046 ps
CPU time 12.76 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:49:26 PM PDT 24
Peak memory 226144 kb
Host smart-d3a02ad4-336d-4fac-844f-3a359a5b4aeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077182879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3077182879
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1142755312
Short name T803
Test name
Test status
Simulation time 1166977265 ps
CPU time 8.43 seconds
Started Apr 23 02:49:15 PM PDT 24
Finished Apr 23 02:49:23 PM PDT 24
Peak memory 218000 kb
Host smart-501801d5-cab2-40c6-876a-916c7cd9b06f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142755312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1142755312
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1219461896
Short name T852
Test name
Test status
Simulation time 1840959734 ps
CPU time 11.41 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:49:24 PM PDT 24
Peak memory 217912 kb
Host smart-142a65a6-48ba-45fe-98b5-1e4e42b933f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219461896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1219461896
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.930056392
Short name T540
Test name
Test status
Simulation time 327158885 ps
CPU time 9.05 seconds
Started Apr 23 02:49:11 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 218132 kb
Host smart-eda7e5c3-4227-4814-8ea3-5da05226d546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930056392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.930056392
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.968189535
Short name T48
Test name
Test status
Simulation time 323241285 ps
CPU time 7.86 seconds
Started Apr 23 02:49:10 PM PDT 24
Finished Apr 23 02:49:18 PM PDT 24
Peak memory 217800 kb
Host smart-f6209c2a-f807-4047-8d9e-266ab86299ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968189535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.968189535
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.761025972
Short name T369
Test name
Test status
Simulation time 580871673 ps
CPU time 31.08 seconds
Started Apr 23 02:49:10 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 250976 kb
Host smart-869310df-a399-46de-82f7-bcb4e091d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761025972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.761025972
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.377394014
Short name T484
Test name
Test status
Simulation time 231452001 ps
CPU time 9.25 seconds
Started Apr 23 02:49:11 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 250976 kb
Host smart-e3b4c629-966e-482a-b218-b368d9df3975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377394014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.377394014
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2764908220
Short name T558
Test name
Test status
Simulation time 9759291575 ps
CPU time 131.64 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:51:24 PM PDT 24
Peak memory 251076 kb
Host smart-290ac7ac-87ad-4f09-b9c6-77f500877d1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764908220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2764908220
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4024511497
Short name T724
Test name
Test status
Simulation time 19941242 ps
CPU time 0.83 seconds
Started Apr 23 02:49:10 PM PDT 24
Finished Apr 23 02:49:12 PM PDT 24
Peak memory 211620 kb
Host smart-6dfe82ca-90d6-46d6-8d82-9e6055600eac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024511497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4024511497
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.62148422
Short name T722
Test name
Test status
Simulation time 48700516 ps
CPU time 1.05 seconds
Started Apr 23 02:49:16 PM PDT 24
Finished Apr 23 02:49:17 PM PDT 24
Peak memory 209524 kb
Host smart-9c528a7c-9fc8-48d0-92c2-24425dd65dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62148422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.62148422
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.132565702
Short name T155
Test name
Test status
Simulation time 1786835320 ps
CPU time 17.36 seconds
Started Apr 23 02:49:17 PM PDT 24
Finished Apr 23 02:49:35 PM PDT 24
Peak memory 217976 kb
Host smart-d931cd39-0068-49c0-943c-1b34134e9421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132565702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.132565702
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2111685678
Short name T723
Test name
Test status
Simulation time 402366316 ps
CPU time 3.87 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:17 PM PDT 24
Peak memory 209660 kb
Host smart-a9269617-9a96-4508-aee6-6e414030e224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111685678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2111685678
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.182377415
Short name T296
Test name
Test status
Simulation time 91168358 ps
CPU time 2.89 seconds
Started Apr 23 02:49:14 PM PDT 24
Finished Apr 23 02:49:17 PM PDT 24
Peak memory 217976 kb
Host smart-a2b0c350-6d2d-47b3-a9f2-dd6ea7f76c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182377415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.182377415
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.398875678
Short name T682
Test name
Test status
Simulation time 1179539774 ps
CPU time 12.28 seconds
Started Apr 23 02:49:14 PM PDT 24
Finished Apr 23 02:49:27 PM PDT 24
Peak memory 219012 kb
Host smart-fa3b97bf-14aa-432e-8268-ebb68b1f29ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398875678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.398875678
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1883000957
Short name T18
Test name
Test status
Simulation time 349076276 ps
CPU time 13.01 seconds
Started Apr 23 02:49:17 PM PDT 24
Finished Apr 23 02:49:30 PM PDT 24
Peak memory 217916 kb
Host smart-03add3cd-075a-4085-bb46-47b93b6d0ba1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883000957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1883000957
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.934574707
Short name T750
Test name
Test status
Simulation time 669388417 ps
CPU time 9.34 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:23 PM PDT 24
Peak memory 218052 kb
Host smart-48270366-13a8-4a8f-9ebd-6670f4ecc988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934574707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.934574707
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4050691506
Short name T535
Test name
Test status
Simulation time 1365325663 ps
CPU time 7.23 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 218004 kb
Host smart-a90e24a4-ed9b-4f20-a842-6779587bec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050691506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4050691506
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3641692201
Short name T354
Test name
Test status
Simulation time 21523781 ps
CPU time 1.56 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:49:14 PM PDT 24
Peak memory 213788 kb
Host smart-65c08756-eacd-43d1-8af1-f76d51e7f218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641692201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3641692201
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1822697351
Short name T417
Test name
Test status
Simulation time 276613289 ps
CPU time 22.64 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:49:36 PM PDT 24
Peak memory 251044 kb
Host smart-a7628ff6-b7f4-45cc-88da-f3480f42e6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822697351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1822697351
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.50201179
Short name T495
Test name
Test status
Simulation time 613010558 ps
CPU time 11.11 seconds
Started Apr 23 02:49:12 PM PDT 24
Finished Apr 23 02:49:24 PM PDT 24
Peak memory 251044 kb
Host smart-a2a07ccf-0768-4b1b-b993-38e977e0edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50201179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.50201179
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3016069977
Short name T648
Test name
Test status
Simulation time 7660491526 ps
CPU time 73.82 seconds
Started Apr 23 02:49:17 PM PDT 24
Finished Apr 23 02:50:31 PM PDT 24
Peak memory 250844 kb
Host smart-b89947d4-fc00-4ff3-9a5f-a9777a6db264
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016069977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3016069977
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3763410226
Short name T810
Test name
Test status
Simulation time 18318146378 ps
CPU time 631.06 seconds
Started Apr 23 02:49:18 PM PDT 24
Finished Apr 23 02:59:50 PM PDT 24
Peak memory 420148 kb
Host smart-a112f7b1-6130-4025-b091-030346e884da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3763410226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3763410226
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.925098524
Short name T574
Test name
Test status
Simulation time 19461431 ps
CPU time 1.01 seconds
Started Apr 23 02:49:13 PM PDT 24
Finished Apr 23 02:49:15 PM PDT 24
Peak memory 211736 kb
Host smart-9cf28d8f-864f-4b5f-8a9f-45267230e0b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925098524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.925098524
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.748263983
Short name T321
Test name
Test status
Simulation time 80716021 ps
CPU time 1.24 seconds
Started Apr 23 02:49:19 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 209588 kb
Host smart-e737f13c-5a64-495d-a052-513d0125e9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748263983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.748263983
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1728962724
Short name T307
Test name
Test status
Simulation time 1516135136 ps
CPU time 14.22 seconds
Started Apr 23 02:49:15 PM PDT 24
Finished Apr 23 02:49:30 PM PDT 24
Peak memory 218000 kb
Host smart-8c8441e2-28c7-4f4c-8c9f-18bdef67a311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728962724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1728962724
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2792461677
Short name T344
Test name
Test status
Simulation time 545638607 ps
CPU time 4.2 seconds
Started Apr 23 02:49:16 PM PDT 24
Finished Apr 23 02:49:21 PM PDT 24
Peak memory 216900 kb
Host smart-7cbf6fa6-7902-4750-be7c-e48cce6ec95c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792461677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2792461677
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.37593561
Short name T309
Test name
Test status
Simulation time 39507312 ps
CPU time 2.18 seconds
Started Apr 23 02:49:17 PM PDT 24
Finished Apr 23 02:49:19 PM PDT 24
Peak memory 218004 kb
Host smart-fefb3122-8ae0-403a-ac84-e0fe9d9b0854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37593561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.37593561
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.44403958
Short name T659
Test name
Test status
Simulation time 1008667372 ps
CPU time 8.32 seconds
Started Apr 23 02:49:21 PM PDT 24
Finished Apr 23 02:49:30 PM PDT 24
Peak memory 218904 kb
Host smart-0510bca0-4ef7-44ff-8fa9-1fed0bb92c23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44403958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.44403958
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2264260069
Short name T416
Test name
Test status
Simulation time 1334470612 ps
CPU time 13.88 seconds
Started Apr 23 02:49:18 PM PDT 24
Finished Apr 23 02:49:32 PM PDT 24
Peak memory 217920 kb
Host smart-60ccb25d-249b-406a-845d-378ad16175e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264260069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2264260069
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1516332401
Short name T603
Test name
Test status
Simulation time 711503170 ps
CPU time 9.37 seconds
Started Apr 23 02:49:21 PM PDT 24
Finished Apr 23 02:49:31 PM PDT 24
Peak memory 218000 kb
Host smart-01faa205-247f-49b9-8d31-a32eecd98475
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516332401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1516332401
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3377219994
Short name T606
Test name
Test status
Simulation time 462546285 ps
CPU time 9.39 seconds
Started Apr 23 02:49:15 PM PDT 24
Finished Apr 23 02:49:25 PM PDT 24
Peak memory 217980 kb
Host smart-c560eccc-c3df-4828-948d-ae683e159757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377219994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3377219994
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.251075316
Short name T854
Test name
Test status
Simulation time 109859637 ps
CPU time 2.45 seconds
Started Apr 23 02:49:18 PM PDT 24
Finished Apr 23 02:49:20 PM PDT 24
Peak memory 217864 kb
Host smart-d22d9b70-e6d7-487e-a2be-b7ca58c5cbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251075316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.251075316
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3712544156
Short name T2
Test name
Test status
Simulation time 263781132 ps
CPU time 32.28 seconds
Started Apr 23 02:49:15 PM PDT 24
Finished Apr 23 02:49:47 PM PDT 24
Peak memory 251020 kb
Host smart-81d624da-842c-4877-a8ca-e98836b3d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712544156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3712544156
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3272295475
Short name T262
Test name
Test status
Simulation time 72509373 ps
CPU time 7.8 seconds
Started Apr 23 02:49:17 PM PDT 24
Finished Apr 23 02:49:25 PM PDT 24
Peak memory 251044 kb
Host smart-c2dac780-3eb0-4fe6-9332-6e27bfc6195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272295475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3272295475
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2573525666
Short name T806
Test name
Test status
Simulation time 10732449098 ps
CPU time 112.06 seconds
Started Apr 23 02:49:20 PM PDT 24
Finished Apr 23 02:51:12 PM PDT 24
Peak memory 282100 kb
Host smart-f622b290-df9d-40f9-83a6-25aa5b896f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573525666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2573525666
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.945688441
Short name T133
Test name
Test status
Simulation time 60812828456 ps
CPU time 324.89 seconds
Started Apr 23 02:49:20 PM PDT 24
Finished Apr 23 02:54:46 PM PDT 24
Peak memory 275940 kb
Host smart-21211a41-2c46-47fd-b749-1a93799d0d81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=945688441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.945688441
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1250728491
Short name T557
Test name
Test status
Simulation time 18902291 ps
CPU time 0.91 seconds
Started Apr 23 02:49:16 PM PDT 24
Finished Apr 23 02:49:18 PM PDT 24
Peak memory 211600 kb
Host smart-af4e8305-a754-459a-8c2c-ec8e90a197c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250728491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1250728491
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1099542437
Short name T333
Test name
Test status
Simulation time 31672476 ps
CPU time 0.82 seconds
Started Apr 23 02:49:22 PM PDT 24
Finished Apr 23 02:49:23 PM PDT 24
Peak memory 209340 kb
Host smart-57bbdaf7-a5e5-4533-b562-1b5342ef9dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099542437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1099542437
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3147736036
Short name T318
Test name
Test status
Simulation time 344297647 ps
CPU time 14.58 seconds
Started Apr 23 02:49:19 PM PDT 24
Finished Apr 23 02:49:34 PM PDT 24
Peak memory 217964 kb
Host smart-830d3f3b-1b3c-408c-a606-0971882e80a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147736036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3147736036
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2424378360
Short name T509
Test name
Test status
Simulation time 603815655 ps
CPU time 6.17 seconds
Started Apr 23 02:49:20 PM PDT 24
Finished Apr 23 02:49:27 PM PDT 24
Peak memory 217128 kb
Host smart-c5632a19-f140-4612-ae4e-81a4f4e32fb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424378360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2424378360
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.369817672
Short name T214
Test name
Test status
Simulation time 53705643 ps
CPU time 2.7 seconds
Started Apr 23 02:49:18 PM PDT 24
Finished Apr 23 02:49:22 PM PDT 24
Peak memory 217992 kb
Host smart-86c1a643-a14e-4cdd-8696-430786e23b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369817672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.369817672
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.247667614
Short name T261
Test name
Test status
Simulation time 1385722923 ps
CPU time 16.2 seconds
Started Apr 23 02:49:21 PM PDT 24
Finished Apr 23 02:49:38 PM PDT 24
Peak memory 218904 kb
Host smart-fb9e0c8a-d944-49ea-9dd3-a339603b5ebd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247667614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.247667614
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2221740842
Short name T815
Test name
Test status
Simulation time 244597025 ps
CPU time 8.86 seconds
Started Apr 23 02:49:22 PM PDT 24
Finished Apr 23 02:49:31 PM PDT 24
Peak memory 217964 kb
Host smart-23f51853-cdeb-4a0e-a123-1c280fb72420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221740842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2221740842
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1247560883
Short name T390
Test name
Test status
Simulation time 1583068768 ps
CPU time 11.02 seconds
Started Apr 23 02:49:24 PM PDT 24
Finished Apr 23 02:49:36 PM PDT 24
Peak memory 218076 kb
Host smart-74ccf601-b513-4d56-991c-0eeb1482d07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247560883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1247560883
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2665574348
Short name T215
Test name
Test status
Simulation time 34473224 ps
CPU time 2.55 seconds
Started Apr 23 02:49:25 PM PDT 24
Finished Apr 23 02:49:28 PM PDT 24
Peak memory 214316 kb
Host smart-9ad8da6a-d780-4ee4-9036-63b00be62d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665574348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2665574348
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.590971154
Short name T796
Test name
Test status
Simulation time 162004118 ps
CPU time 19.34 seconds
Started Apr 23 02:49:21 PM PDT 24
Finished Apr 23 02:49:40 PM PDT 24
Peak memory 251012 kb
Host smart-2931d506-03ca-4540-bbc5-b6e9ad17b65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590971154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.590971154
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2263600168
Short name T584
Test name
Test status
Simulation time 53742748 ps
CPU time 7.64 seconds
Started Apr 23 02:49:19 PM PDT 24
Finished Apr 23 02:49:28 PM PDT 24
Peak memory 251068 kb
Host smart-3107f2c9-455c-4707-b530-878f8df6b798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263600168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2263600168
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.33891966
Short name T551
Test name
Test status
Simulation time 8149001536 ps
CPU time 114.92 seconds
Started Apr 23 02:49:23 PM PDT 24
Finished Apr 23 02:51:18 PM PDT 24
Peak memory 217868 kb
Host smart-140f9cfd-db4f-48bd-a0c0-534650da82c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33891966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.lc_ctrl_stress_all.33891966
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1502769672
Short name T78
Test name
Test status
Simulation time 9415448409 ps
CPU time 340.19 seconds
Started Apr 23 02:49:23 PM PDT 24
Finished Apr 23 02:55:04 PM PDT 24
Peak memory 289444 kb
Host smart-aafccb4b-43fe-4d51-a583-a4cfd4a32371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1502769672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1502769672
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1512557577
Short name T294
Test name
Test status
Simulation time 55229197 ps
CPU time 1.06 seconds
Started Apr 23 02:49:23 PM PDT 24
Finished Apr 23 02:49:25 PM PDT 24
Peak memory 212912 kb
Host smart-b1bab626-6b95-40c3-8193-b44fc05fed26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512557577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1512557577
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1770682567
Short name T707
Test name
Test status
Simulation time 52279910 ps
CPU time 1.01 seconds
Started Apr 23 02:49:28 PM PDT 24
Finished Apr 23 02:49:29 PM PDT 24
Peak memory 209584 kb
Host smart-975c5cfb-df76-4090-80e0-d5f7507ed65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770682567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1770682567
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3823177392
Short name T33
Test name
Test status
Simulation time 1208356655 ps
CPU time 10.97 seconds
Started Apr 23 02:49:22 PM PDT 24
Finished Apr 23 02:49:33 PM PDT 24
Peak memory 217996 kb
Host smart-1d81f536-83d8-481b-a213-8df73f7b3508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823177392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3823177392
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3366500576
Short name T496
Test name
Test status
Simulation time 283204205 ps
CPU time 4.41 seconds
Started Apr 23 02:49:27 PM PDT 24
Finished Apr 23 02:49:32 PM PDT 24
Peak memory 209564 kb
Host smart-0912f96d-bff6-44fb-bef2-af448132afe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366500576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3366500576
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.100195095
Short name T274
Test name
Test status
Simulation time 187316407 ps
CPU time 4.23 seconds
Started Apr 23 02:49:24 PM PDT 24
Finished Apr 23 02:49:28 PM PDT 24
Peak memory 217900 kb
Host smart-9267101c-c0d7-43d4-bbde-335f30f3a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100195095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.100195095
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2977313316
Short name T855
Test name
Test status
Simulation time 228138503 ps
CPU time 11.16 seconds
Started Apr 23 02:49:26 PM PDT 24
Finished Apr 23 02:49:38 PM PDT 24
Peak memory 225488 kb
Host smart-dbbe80ea-eb30-438c-960e-fdf1f8bf3a73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977313316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2977313316
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2145368071
Short name T669
Test name
Test status
Simulation time 864009949 ps
CPU time 7.31 seconds
Started Apr 23 02:49:29 PM PDT 24
Finished Apr 23 02:49:37 PM PDT 24
Peak memory 218004 kb
Host smart-9c61a069-4aa1-4787-b057-336e1ebfa2ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145368071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2145368071
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.573325576
Short name T435
Test name
Test status
Simulation time 463811160 ps
CPU time 8.85 seconds
Started Apr 23 02:49:28 PM PDT 24
Finished Apr 23 02:49:37 PM PDT 24
Peak memory 218004 kb
Host smart-486a97ed-00a0-4d89-b1a3-185cdba48f71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573325576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.573325576
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2514570564
Short name T824
Test name
Test status
Simulation time 239192377 ps
CPU time 6.6 seconds
Started Apr 23 02:49:26 PM PDT 24
Finished Apr 23 02:49:33 PM PDT 24
Peak memory 218012 kb
Host smart-3be35011-b7d8-4b69-8d3f-4b3a0f528344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514570564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2514570564
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.310936277
Short name T65
Test name
Test status
Simulation time 32487188 ps
CPU time 1.01 seconds
Started Apr 23 02:49:23 PM PDT 24
Finished Apr 23 02:49:24 PM PDT 24
Peak memory 211748 kb
Host smart-191adf48-196d-47ac-8e3b-b255684a0dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310936277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.310936277
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2080666213
Short name T173
Test name
Test status
Simulation time 224920683 ps
CPU time 21.5 seconds
Started Apr 23 02:49:23 PM PDT 24
Finished Apr 23 02:49:45 PM PDT 24
Peak memory 250988 kb
Host smart-a5c46845-be0c-483b-b945-5118be849ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080666213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2080666213
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.544737509
Short name T218
Test name
Test status
Simulation time 84664654 ps
CPU time 4.1 seconds
Started Apr 23 02:49:22 PM PDT 24
Finished Apr 23 02:49:27 PM PDT 24
Peak memory 222260 kb
Host smart-4a8a2623-9382-4b2a-8f60-5bed7e7f60c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544737509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.544737509
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1163924441
Short name T500
Test name
Test status
Simulation time 3398135373 ps
CPU time 103.25 seconds
Started Apr 23 02:49:26 PM PDT 24
Finished Apr 23 02:51:10 PM PDT 24
Peak memory 250588 kb
Host smart-85693556-df77-4d49-91a6-25e18b2e28e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163924441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1163924441
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.730897417
Short name T238
Test name
Test status
Simulation time 41955194 ps
CPU time 0.86 seconds
Started Apr 23 02:49:22 PM PDT 24
Finished Apr 23 02:49:24 PM PDT 24
Peak memory 211680 kb
Host smart-16d58173-3def-4da7-8e5b-f0ae26c9927a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730897417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.730897417
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.163707846
Short name T851
Test name
Test status
Simulation time 16941609 ps
CPU time 1.1 seconds
Started Apr 23 02:49:30 PM PDT 24
Finished Apr 23 02:49:31 PM PDT 24
Peak memory 209544 kb
Host smart-20af9110-6c75-46ec-bb8a-660800b17333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163707846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.163707846
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.502200403
Short name T430
Test name
Test status
Simulation time 159417018 ps
CPU time 8.18 seconds
Started Apr 23 02:49:28 PM PDT 24
Finished Apr 23 02:49:37 PM PDT 24
Peak memory 218028 kb
Host smart-c58dc14b-e361-4a6a-8803-a62a5a619363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502200403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.502200403
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1775138381
Short name T493
Test name
Test status
Simulation time 623068979 ps
CPU time 4.74 seconds
Started Apr 23 02:49:32 PM PDT 24
Finished Apr 23 02:49:37 PM PDT 24
Peak memory 216872 kb
Host smart-56585753-2531-4887-817b-8e666929a036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775138381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1775138381
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2773372076
Short name T314
Test name
Test status
Simulation time 81261035 ps
CPU time 2.03 seconds
Started Apr 23 02:49:27 PM PDT 24
Finished Apr 23 02:49:30 PM PDT 24
Peak memory 218068 kb
Host smart-6f37db72-c2c8-42d5-b37c-7412b14e910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773372076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2773372076
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3852454611
Short name T151
Test name
Test status
Simulation time 1110742386 ps
CPU time 9.27 seconds
Started Apr 23 02:49:29 PM PDT 24
Finished Apr 23 02:49:39 PM PDT 24
Peak memory 226052 kb
Host smart-387b0201-5f1a-4b2c-b553-456a31ff4b42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852454611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3852454611
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.415711480
Short name T284
Test name
Test status
Simulation time 398064385 ps
CPU time 11.79 seconds
Started Apr 23 02:49:30 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 217964 kb
Host smart-49387eab-e043-4c7e-9b2a-81ab0464e055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415711480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.415711480
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.943484902
Short name T643
Test name
Test status
Simulation time 2154652880 ps
CPU time 16.72 seconds
Started Apr 23 02:49:29 PM PDT 24
Finished Apr 23 02:49:46 PM PDT 24
Peak memory 217936 kb
Host smart-b8b74f3d-37a8-4645-a45e-a15005114365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943484902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.943484902
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3383122819
Short name T778
Test name
Test status
Simulation time 1162066357 ps
CPU time 10.57 seconds
Started Apr 23 02:49:31 PM PDT 24
Finished Apr 23 02:49:41 PM PDT 24
Peak memory 225040 kb
Host smart-d5f0d348-914b-46ee-9b26-0a4d252f0551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383122819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3383122819
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3139447136
Short name T265
Test name
Test status
Simulation time 30442093 ps
CPU time 2.14 seconds
Started Apr 23 02:49:26 PM PDT 24
Finished Apr 23 02:49:28 PM PDT 24
Peak memory 214160 kb
Host smart-ce79daa1-ada9-4d1c-92c6-49ce927da158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139447136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3139447136
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3934653536
Short name T479
Test name
Test status
Simulation time 1525010374 ps
CPU time 21.99 seconds
Started Apr 23 02:49:29 PM PDT 24
Finished Apr 23 02:49:51 PM PDT 24
Peak memory 251004 kb
Host smart-c3f95128-452a-4ab0-94eb-ff2032b1fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934653536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3934653536
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.392632849
Short name T634
Test name
Test status
Simulation time 114528530 ps
CPU time 5.29 seconds
Started Apr 23 02:49:27 PM PDT 24
Finished Apr 23 02:49:33 PM PDT 24
Peak memory 222176 kb
Host smart-7e064659-0326-4fe8-acb5-da3ffec4b95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392632849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.392632849
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2364589248
Short name T169
Test name
Test status
Simulation time 15370121207 ps
CPU time 121.45 seconds
Started Apr 23 02:49:30 PM PDT 24
Finished Apr 23 02:51:32 PM PDT 24
Peak memory 251084 kb
Host smart-9130a949-91b0-4937-90f4-8fe6a50d9bab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364589248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2364589248
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3266132070
Short name T585
Test name
Test status
Simulation time 28633470 ps
CPU time 0.91 seconds
Started Apr 23 02:49:29 PM PDT 24
Finished Apr 23 02:49:30 PM PDT 24
Peak memory 211724 kb
Host smart-dd7864da-9091-4fda-aecc-674c71cd762e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266132070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3266132070
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1812485982
Short name T77
Test name
Test status
Simulation time 41124958 ps
CPU time 0.76 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:11 PM PDT 24
Peak memory 209316 kb
Host smart-d37e5227-47f8-4c44-9548-9d42d55eb759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812485982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1812485982
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2040659055
Short name T203
Test name
Test status
Simulation time 13361382 ps
CPU time 1 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:07 PM PDT 24
Peak memory 209516 kb
Host smart-50d1e1ab-5594-4c39-9fd9-420d5a30159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040659055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2040659055
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1237369004
Short name T757
Test name
Test status
Simulation time 236496016 ps
CPU time 9.56 seconds
Started Apr 23 02:47:07 PM PDT 24
Finished Apr 23 02:47:17 PM PDT 24
Peak memory 218032 kb
Host smart-cceed0c6-d6f8-41ee-bda4-0763020a25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237369004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1237369004
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1323833784
Short name T347
Test name
Test status
Simulation time 1688577155 ps
CPU time 5.21 seconds
Started Apr 23 02:47:07 PM PDT 24
Finished Apr 23 02:47:12 PM PDT 24
Peak memory 217228 kb
Host smart-4db1c562-1011-42d2-8cfb-5272cf79fd70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323833784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1323833784
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3555281241
Short name T708
Test name
Test status
Simulation time 28455884754 ps
CPU time 52.62 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:59 PM PDT 24
Peak memory 218040 kb
Host smart-1fd8f1dd-6ee4-4223-876f-8e193e6eab02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555281241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3555281241
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1059970775
Short name T21
Test name
Test status
Simulation time 196167055 ps
CPU time 5.8 seconds
Started Apr 23 02:47:08 PM PDT 24
Finished Apr 23 02:47:15 PM PDT 24
Peak memory 217100 kb
Host smart-3c1b70db-b21a-495c-8e71-db34a0cae00c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059970775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
059970775
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3071949695
Short name T624
Test name
Test status
Simulation time 567013815 ps
CPU time 5.19 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:11 PM PDT 24
Peak memory 217920 kb
Host smart-8b27b82a-4f50-4595-aa2d-7cd051b663e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071949695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3071949695
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.569296384
Short name T339
Test name
Test status
Simulation time 7947756974 ps
CPU time 38.45 seconds
Started Apr 23 02:47:11 PM PDT 24
Finished Apr 23 02:47:50 PM PDT 24
Peak memory 214164 kb
Host smart-50363783-5cae-4a35-983c-ad3c04886ac6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569296384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.569296384
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3521733471
Short name T403
Test name
Test status
Simulation time 222891005 ps
CPU time 6.97 seconds
Started Apr 23 02:47:07 PM PDT 24
Finished Apr 23 02:47:14 PM PDT 24
Peak memory 213652 kb
Host smart-19869c58-7498-43c2-b6cf-4cf857fd6309
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521733471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3521733471
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.55153004
Short name T149
Test name
Test status
Simulation time 1412137867 ps
CPU time 57 seconds
Started Apr 23 02:47:07 PM PDT 24
Finished Apr 23 02:48:04 PM PDT 24
Peak memory 275644 kb
Host smart-4de7c7a3-deb7-4937-bb7f-82f3a7bad4c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55153004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
state_failure.55153004
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2997023286
Short name T599
Test name
Test status
Simulation time 3911649668 ps
CPU time 15.37 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:22 PM PDT 24
Peak memory 218008 kb
Host smart-1997d034-02a9-4e99-ac95-f4f7760a4bea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997023286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2997023286
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3158478981
Short name T675
Test name
Test status
Simulation time 69808672 ps
CPU time 2.31 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:09 PM PDT 24
Peak memory 218036 kb
Host smart-d470df66-a0cd-43b9-bfcc-45f110984311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158478981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3158478981
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.291472450
Short name T437
Test name
Test status
Simulation time 3327899619 ps
CPU time 20.6 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:27 PM PDT 24
Peak memory 214356 kb
Host smart-11c0d4bc-9282-4b70-ab42-8981a2680770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291472450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.291472450
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.927227721
Short name T74
Test name
Test status
Simulation time 105434967 ps
CPU time 23.4 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:34 PM PDT 24
Peak memory 284508 kb
Host smart-fc9f8ea8-1e9c-40a1-b294-8d37146dbb38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927227721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.927227721
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1997961896
Short name T35
Test name
Test status
Simulation time 2346517811 ps
CPU time 15.84 seconds
Started Apr 23 02:47:09 PM PDT 24
Finished Apr 23 02:47:25 PM PDT 24
Peak memory 218916 kb
Host smart-03535563-768a-4721-b130-686688d0a802
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997961896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1997961896
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1423891471
Short name T292
Test name
Test status
Simulation time 330838775 ps
CPU time 11.66 seconds
Started Apr 23 02:47:09 PM PDT 24
Finished Apr 23 02:47:21 PM PDT 24
Peak memory 217972 kb
Host smart-b4aff584-fa7f-4aa6-9479-5aac48890fcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423891471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1423891471
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2312867161
Short name T563
Test name
Test status
Simulation time 2929774658 ps
CPU time 12.94 seconds
Started Apr 23 02:47:08 PM PDT 24
Finished Apr 23 02:47:21 PM PDT 24
Peak memory 218028 kb
Host smart-d227614e-1c46-4cd3-a081-5efeaca01603
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312867161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
312867161
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1479618228
Short name T56
Test name
Test status
Simulation time 34855864 ps
CPU time 1.09 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:07 PM PDT 24
Peak memory 213220 kb
Host smart-6db3b471-1d0f-4127-8934-a39137913222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479618228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1479618228
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.613120580
Short name T432
Test name
Test status
Simulation time 2815663045 ps
CPU time 25.16 seconds
Started Apr 23 02:47:07 PM PDT 24
Finished Apr 23 02:47:33 PM PDT 24
Peak memory 251112 kb
Host smart-657b9e5f-f5a9-4185-886b-24f379962aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613120580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.613120580
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3288987409
Short name T575
Test name
Test status
Simulation time 304751585 ps
CPU time 5.9 seconds
Started Apr 23 02:47:04 PM PDT 24
Finished Apr 23 02:47:11 PM PDT 24
Peak memory 246680 kb
Host smart-6832f130-088b-4df9-9691-e0cab285160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288987409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3288987409
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3131154150
Short name T730
Test name
Test status
Simulation time 4348002199 ps
CPU time 71.02 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:48:22 PM PDT 24
Peak memory 251056 kb
Host smart-adb30e4b-4327-4529-959d-48409550463d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131154150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3131154150
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2123500518
Short name T90
Test name
Test status
Simulation time 13703611325 ps
CPU time 255 seconds
Started Apr 23 02:47:09 PM PDT 24
Finished Apr 23 02:51:24 PM PDT 24
Peak memory 421860 kb
Host smart-8fc4b35f-b657-4a45-8619-f1ecfb8ac3b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2123500518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2123500518
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1391199171
Short name T480
Test name
Test status
Simulation time 19452525 ps
CPU time 0.81 seconds
Started Apr 23 02:47:06 PM PDT 24
Finished Apr 23 02:47:07 PM PDT 24
Peak memory 208128 kb
Host smart-3906d85c-a9d1-489c-a99e-426a24c67444
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391199171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1391199171
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2798331864
Short name T811
Test name
Test status
Simulation time 74556023 ps
CPU time 0.87 seconds
Started Apr 23 02:49:32 PM PDT 24
Finished Apr 23 02:49:34 PM PDT 24
Peak memory 209508 kb
Host smart-30335d14-e126-4804-8d74-ef1b5cab53f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798331864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2798331864
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.80289953
Short name T370
Test name
Test status
Simulation time 2525558219 ps
CPU time 9.6 seconds
Started Apr 23 02:49:32 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 217976 kb
Host smart-129d3904-b70b-45d4-bb72-b8ac024413d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80289953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.80289953
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.330998545
Short name T343
Test name
Test status
Simulation time 1894136374 ps
CPU time 10.79 seconds
Started Apr 23 02:49:31 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 217020 kb
Host smart-2b41d408-a0c5-498c-b397-a360de82b4d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330998545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.330998545
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1689562675
Short name T466
Test name
Test status
Simulation time 73742024 ps
CPU time 2.26 seconds
Started Apr 23 02:49:34 PM PDT 24
Finished Apr 23 02:49:37 PM PDT 24
Peak memory 218044 kb
Host smart-b09b76e2-ba74-45f2-b155-78adb529f4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689562675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1689562675
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3863141978
Short name T729
Test name
Test status
Simulation time 495377291 ps
CPU time 10.97 seconds
Started Apr 23 02:49:33 PM PDT 24
Finished Apr 23 02:49:45 PM PDT 24
Peak memory 217912 kb
Host smart-3a56be36-1069-4690-9f2a-3c4095799f8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863141978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3863141978
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2513122883
Short name T342
Test name
Test status
Simulation time 368692361 ps
CPU time 9.69 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:48 PM PDT 24
Peak memory 218008 kb
Host smart-c74128c6-43d0-42c5-9541-2c7a63d2b730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513122883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2513122883
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2883370735
Short name T376
Test name
Test status
Simulation time 916738006 ps
CPU time 9.63 seconds
Started Apr 23 02:49:37 PM PDT 24
Finished Apr 23 02:49:47 PM PDT 24
Peak memory 224432 kb
Host smart-7b539556-8b15-408f-ae41-9eb421604025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883370735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2883370735
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.69119483
Short name T356
Test name
Test status
Simulation time 84346774 ps
CPU time 1.94 seconds
Started Apr 23 02:49:30 PM PDT 24
Finished Apr 23 02:49:33 PM PDT 24
Peak memory 213284 kb
Host smart-aaee54d2-d50c-47c7-9f6e-be9ecaed600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69119483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.69119483
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3198070356
Short name T415
Test name
Test status
Simulation time 231201297 ps
CPU time 21.02 seconds
Started Apr 23 02:49:30 PM PDT 24
Finished Apr 23 02:49:51 PM PDT 24
Peak memory 251052 kb
Host smart-446451f0-b6d8-4184-aaf0-cbe7c3af10b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198070356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3198070356
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2059586343
Short name T641
Test name
Test status
Simulation time 101661858 ps
CPU time 10.36 seconds
Started Apr 23 02:49:27 PM PDT 24
Finished Apr 23 02:49:38 PM PDT 24
Peak memory 251048 kb
Host smart-6805582e-2ef5-4b1f-9770-2bf5cd256e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059586343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2059586343
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3167384984
Short name T16
Test name
Test status
Simulation time 160762491915 ps
CPU time 656.31 seconds
Started Apr 23 02:49:34 PM PDT 24
Finished Apr 23 03:00:31 PM PDT 24
Peak memory 276156 kb
Host smart-40d2ad54-5c6c-4e3e-bdbe-7722faae34c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167384984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3167384984
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3175756431
Short name T661
Test name
Test status
Simulation time 13590205 ps
CPU time 0.83 seconds
Started Apr 23 02:49:31 PM PDT 24
Finished Apr 23 02:49:32 PM PDT 24
Peak memory 211600 kb
Host smart-5b1874f1-6b5f-44d6-a1d0-1697aba39489
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175756431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3175756431
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.304212073
Short name T75
Test name
Test status
Simulation time 15700569 ps
CPU time 1.05 seconds
Started Apr 23 02:49:35 PM PDT 24
Finished Apr 23 02:49:36 PM PDT 24
Peak memory 209524 kb
Host smart-b4d61040-6399-40cd-ab38-ec0b5cff2200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304212073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.304212073
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1268487261
Short name T37
Test name
Test status
Simulation time 2572769392 ps
CPU time 14.41 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:53 PM PDT 24
Peak memory 217988 kb
Host smart-02413795-aeb0-45e0-810a-9cb37360d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268487261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1268487261
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1237533960
Short name T180
Test name
Test status
Simulation time 248544896 ps
CPU time 7.22 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:46 PM PDT 24
Peak memory 216940 kb
Host smart-cff4eae7-ee19-4cc8-aff8-daf64f5b0215
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237533960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1237533960
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.679298825
Short name T282
Test name
Test status
Simulation time 22302017 ps
CPU time 1.81 seconds
Started Apr 23 02:49:37 PM PDT 24
Finished Apr 23 02:49:39 PM PDT 24
Peak memory 218000 kb
Host smart-5fa5d99d-20fb-4eb6-a242-93d0f72c4097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679298825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.679298825
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2089807778
Short name T773
Test name
Test status
Simulation time 810176514 ps
CPU time 9.83 seconds
Started Apr 23 02:49:34 PM PDT 24
Finished Apr 23 02:49:44 PM PDT 24
Peak memory 226168 kb
Host smart-078b2620-9b75-4aad-9b67-51bc223dd8ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089807778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2089807778
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3248290251
Short name T467
Test name
Test status
Simulation time 1774806332 ps
CPU time 14.87 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:49:51 PM PDT 24
Peak memory 217964 kb
Host smart-839b3c5f-7076-42d1-9dfd-730d2ca76656
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248290251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3248290251
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2407941842
Short name T365
Test name
Test status
Simulation time 229405055 ps
CPU time 9.36 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:48 PM PDT 24
Peak memory 218004 kb
Host smart-580f73ec-6a3d-4e45-8a13-0fc626e3e4f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407941842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2407941842
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2095099793
Short name T375
Test name
Test status
Simulation time 455985409 ps
CPU time 7.03 seconds
Started Apr 23 02:49:35 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 218076 kb
Host smart-ebddbc46-2740-4ed3-8f0d-b52857a347cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095099793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2095099793
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1271371903
Short name T533
Test name
Test status
Simulation time 39264146 ps
CPU time 2.46 seconds
Started Apr 23 02:49:32 PM PDT 24
Finished Apr 23 02:49:35 PM PDT 24
Peak memory 217776 kb
Host smart-137a2a0f-becf-4894-ab15-c65fbd9ebfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271371903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1271371903
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2538077507
Short name T546
Test name
Test status
Simulation time 191777196 ps
CPU time 21.41 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:50:00 PM PDT 24
Peak memory 251028 kb
Host smart-b61c3b71-4290-48a8-b238-dd5a175762da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538077507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2538077507
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1256723276
Short name T460
Test name
Test status
Simulation time 223162653 ps
CPU time 5.8 seconds
Started Apr 23 02:49:35 PM PDT 24
Finished Apr 23 02:49:41 PM PDT 24
Peak memory 246556 kb
Host smart-b281418f-2255-47a2-bcb8-d7e650c34f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256723276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1256723276
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1077398741
Short name T524
Test name
Test status
Simulation time 4721495544 ps
CPU time 93.3 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:51:10 PM PDT 24
Peak memory 273632 kb
Host smart-8ffbc272-635e-4aaf-a89c-fa10d4c24be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077398741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1077398741
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3270484155
Short name T726
Test name
Test status
Simulation time 70376050 ps
CPU time 1.18 seconds
Started Apr 23 02:49:33 PM PDT 24
Finished Apr 23 02:49:35 PM PDT 24
Peak memory 213196 kb
Host smart-aed0f059-4a42-4d91-b01f-9b6537296a18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270484155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3270484155
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1473498087
Short name T486
Test name
Test status
Simulation time 12957681 ps
CPU time 0.97 seconds
Started Apr 23 02:49:37 PM PDT 24
Finished Apr 23 02:49:38 PM PDT 24
Peak memory 209564 kb
Host smart-673065af-d892-42a1-a936-f877487143eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473498087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1473498087
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4234590720
Short name T826
Test name
Test status
Simulation time 291963840 ps
CPU time 10.9 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:49 PM PDT 24
Peak memory 218052 kb
Host smart-fc5a9f92-9ce5-4073-99e3-b376e6914227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234590720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4234590720
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3628133303
Short name T458
Test name
Test status
Simulation time 477960957 ps
CPU time 1.72 seconds
Started Apr 23 02:49:35 PM PDT 24
Finished Apr 23 02:49:37 PM PDT 24
Peak memory 209524 kb
Host smart-1d40dc76-65a4-47ac-b6ae-0912ae331912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628133303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3628133303
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1793572540
Short name T447
Test name
Test status
Simulation time 261378348 ps
CPU time 2.42 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:49:39 PM PDT 24
Peak memory 218036 kb
Host smart-c84e703f-0270-4332-97da-fe01ea533907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793572540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1793572540
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.953202694
Short name T697
Test name
Test status
Simulation time 1250971988 ps
CPU time 12.03 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:50 PM PDT 24
Peak memory 218080 kb
Host smart-f8225c42-8093-4133-9310-f437341e3d3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953202694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.953202694
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.4261986843
Short name T841
Test name
Test status
Simulation time 1626614110 ps
CPU time 11.09 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:49:48 PM PDT 24
Peak memory 217932 kb
Host smart-c41011d3-11be-4c66-8381-7e8109f29950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261986843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.4261986843
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3783654524
Short name T541
Test name
Test status
Simulation time 378577789 ps
CPU time 12.8 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:49:49 PM PDT 24
Peak memory 217948 kb
Host smart-f04c05d5-1e92-45f8-ad4e-c7a7efd0e408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783654524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3783654524
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.502975573
Short name T550
Test name
Test status
Simulation time 903084833 ps
CPU time 6.99 seconds
Started Apr 23 02:49:35 PM PDT 24
Finished Apr 23 02:49:43 PM PDT 24
Peak memory 218004 kb
Host smart-1e2204da-4930-456d-88ec-08b5af5d75c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502975573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.502975573
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1846153120
Short name T542
Test name
Test status
Simulation time 85043012 ps
CPU time 5.04 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:49:41 PM PDT 24
Peak memory 214580 kb
Host smart-51b5d050-75fb-4c42-b6ed-f140ea070065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846153120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1846153120
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3941954743
Short name T647
Test name
Test status
Simulation time 821808621 ps
CPU time 21.72 seconds
Started Apr 23 02:49:37 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 251068 kb
Host smart-9dbd1502-d18a-4ece-8be3-dfb7abcb7636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941954743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3941954743
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3739733699
Short name T573
Test name
Test status
Simulation time 431106250 ps
CPU time 8.02 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:49:45 PM PDT 24
Peak memory 250588 kb
Host smart-a59c9107-f826-4002-a595-1b8f7bfcc173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739733699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3739733699
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.900103664
Short name T253
Test name
Test status
Simulation time 571460219 ps
CPU time 23.03 seconds
Started Apr 23 02:49:41 PM PDT 24
Finished Apr 23 02:50:05 PM PDT 24
Peak memory 251024 kb
Host smart-9f846317-9dcc-422c-948a-83c04baf6849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900103664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.900103664
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.538552424
Short name T164
Test name
Test status
Simulation time 30066760743 ps
CPU time 576.88 seconds
Started Apr 23 02:49:40 PM PDT 24
Finished Apr 23 02:59:17 PM PDT 24
Peak memory 316640 kb
Host smart-77989ef5-6442-4982-b9e4-c1a6f8e7acb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=538552424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.538552424
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.57170134
Short name T696
Test name
Test status
Simulation time 110155809 ps
CPU time 0.89 seconds
Started Apr 23 02:49:36 PM PDT 24
Finished Apr 23 02:49:38 PM PDT 24
Peak memory 211680 kb
Host smart-cf646240-05b4-4b32-949d-577d1d7a8796
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57170134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctr
l_volatile_unlock_smoke.57170134
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2462198155
Short name T351
Test name
Test status
Simulation time 190783785 ps
CPU time 1.19 seconds
Started Apr 23 02:49:40 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 209584 kb
Host smart-b8a5d3df-e7c8-4143-88cc-1be3299ce9c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462198155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2462198155
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4277013115
Short name T561
Test name
Test status
Simulation time 846526137 ps
CPU time 12.22 seconds
Started Apr 23 02:49:40 PM PDT 24
Finished Apr 23 02:49:53 PM PDT 24
Peak memory 218060 kb
Host smart-78aa6a1a-d42d-4ace-8510-5b35b0d035b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277013115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4277013115
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.120259413
Short name T28
Test name
Test status
Simulation time 425764991 ps
CPU time 5.02 seconds
Started Apr 23 02:49:41 PM PDT 24
Finished Apr 23 02:49:47 PM PDT 24
Peak memory 217192 kb
Host smart-08207a1f-1803-4489-804e-bf1e7451ccca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120259413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.120259413
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3831047196
Short name T256
Test name
Test status
Simulation time 67038127 ps
CPU time 3.34 seconds
Started Apr 23 02:49:39 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 218008 kb
Host smart-6d705c29-f201-4c63-9533-2b4fb6144cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831047196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3831047196
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1070344358
Short name T655
Test name
Test status
Simulation time 1442158444 ps
CPU time 18.4 seconds
Started Apr 23 02:49:40 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 226088 kb
Host smart-ef5999e3-f8ce-4e7f-ac72-88877a33c5dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070344358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1070344358
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3207487705
Short name T744
Test name
Test status
Simulation time 782824903 ps
CPU time 9.19 seconds
Started Apr 23 02:49:39 PM PDT 24
Finished Apr 23 02:49:49 PM PDT 24
Peak memory 217976 kb
Host smart-dcc9b6d4-6cf9-4b7b-98cb-5d342a28e64a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207487705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3207487705
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1083516458
Short name T857
Test name
Test status
Simulation time 373950552 ps
CPU time 11.89 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:51 PM PDT 24
Peak memory 217996 kb
Host smart-b1782411-5014-4258-bdbb-8133efbe90f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083516458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1083516458
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.882616527
Short name T519
Test name
Test status
Simulation time 386461505 ps
CPU time 8.19 seconds
Started Apr 23 02:49:39 PM PDT 24
Finished Apr 23 02:49:48 PM PDT 24
Peak memory 218036 kb
Host smart-24b252fc-c9d7-480b-a8b0-824f6d77e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882616527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.882616527
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2941247885
Short name T58
Test name
Test status
Simulation time 33967918 ps
CPU time 2.48 seconds
Started Apr 23 02:49:39 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 213920 kb
Host smart-bd82aabb-a1ab-4cb7-b128-f896f51bfcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941247885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2941247885
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.319715029
Short name T288
Test name
Test status
Simulation time 186090104 ps
CPU time 21.56 seconds
Started Apr 23 02:49:40 PM PDT 24
Finished Apr 23 02:50:01 PM PDT 24
Peak memory 250992 kb
Host smart-a245bdf9-62ed-4a49-9835-3793e07fb425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319715029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.319715029
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.731356810
Short name T787
Test name
Test status
Simulation time 250391100 ps
CPU time 9.8 seconds
Started Apr 23 02:49:38 PM PDT 24
Finished Apr 23 02:49:48 PM PDT 24
Peak memory 251092 kb
Host smart-0ef6c687-7214-432d-9bd1-4cf7e9f6fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731356810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.731356810
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3736907488
Short name T469
Test name
Test status
Simulation time 23354383948 ps
CPU time 167.7 seconds
Started Apr 23 02:49:40 PM PDT 24
Finished Apr 23 02:52:29 PM PDT 24
Peak memory 229320 kb
Host smart-b58df993-78f9-4338-831d-bff74ac44f95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736907488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3736907488
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2788851926
Short name T522
Test name
Test status
Simulation time 51912582 ps
CPU time 0.97 seconds
Started Apr 23 02:49:39 PM PDT 24
Finished Apr 23 02:49:40 PM PDT 24
Peak memory 212876 kb
Host smart-3e2f4213-2077-40f6-8ea0-2813b30bc703
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788851926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2788851926
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1917053648
Short name T304
Test name
Test status
Simulation time 20291299 ps
CPU time 0.94 seconds
Started Apr 23 02:49:43 PM PDT 24
Finished Apr 23 02:49:45 PM PDT 24
Peak memory 209588 kb
Host smart-0e1e7501-ba05-4563-9c1b-03cf3604c50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917053648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1917053648
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.737627277
Short name T871
Test name
Test status
Simulation time 289224870 ps
CPU time 10.89 seconds
Started Apr 23 02:49:42 PM PDT 24
Finished Apr 23 02:49:54 PM PDT 24
Peak memory 217920 kb
Host smart-12651721-bc01-436b-8eab-2f8315540abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737627277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.737627277
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.157691594
Short name T703
Test name
Test status
Simulation time 187625822 ps
CPU time 1.63 seconds
Started Apr 23 02:49:48 PM PDT 24
Finished Apr 23 02:49:51 PM PDT 24
Peak memory 216780 kb
Host smart-3e96ecc6-2647-40c8-ade2-598ee963c430
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157691594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.157691594
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3967175636
Short name T298
Test name
Test status
Simulation time 83177410 ps
CPU time 1.68 seconds
Started Apr 23 02:49:44 PM PDT 24
Finished Apr 23 02:49:46 PM PDT 24
Peak memory 217908 kb
Host smart-44422f0d-9323-494e-bcd9-4d0a1d16d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967175636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3967175636
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3724320751
Short name T835
Test name
Test status
Simulation time 1324761342 ps
CPU time 14.44 seconds
Started Apr 23 02:49:44 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 218908 kb
Host smart-c901dfae-76f6-455e-b012-d54f59abd702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724320751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3724320751
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.634941263
Short name T286
Test name
Test status
Simulation time 224254343 ps
CPU time 10.03 seconds
Started Apr 23 02:49:42 PM PDT 24
Finished Apr 23 02:49:53 PM PDT 24
Peak memory 218024 kb
Host smart-1a79bcdf-d5ef-475f-bc9b-640ed5d59898
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634941263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.634941263
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4036986085
Short name T140
Test name
Test status
Simulation time 462155146 ps
CPU time 8.65 seconds
Started Apr 23 02:49:42 PM PDT 24
Finished Apr 23 02:49:51 PM PDT 24
Peak memory 218072 kb
Host smart-4995fb7c-ac3f-480e-9805-0c56f1a742a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036986085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4036986085
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1140259040
Short name T290
Test name
Test status
Simulation time 2418957406 ps
CPU time 8.54 seconds
Started Apr 23 02:49:43 PM PDT 24
Finished Apr 23 02:49:52 PM PDT 24
Peak memory 218108 kb
Host smart-e206c1f5-a31b-4c6a-bf7c-1fcac4561a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140259040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1140259040
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.647348172
Short name T221
Test name
Test status
Simulation time 51704423 ps
CPU time 1.55 seconds
Started Apr 23 02:49:40 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 213628 kb
Host smart-ff931a8c-d8e5-486d-a7c5-8e0dfcdb3739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647348172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.647348172
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2308897759
Short name T223
Test name
Test status
Simulation time 1109708147 ps
CPU time 26.16 seconds
Started Apr 23 02:49:42 PM PDT 24
Finished Apr 23 02:50:09 PM PDT 24
Peak memory 250992 kb
Host smart-271ff7bb-25f5-441e-9fe2-ae32fdc6de90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308897759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2308897759
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2281312136
Short name T607
Test name
Test status
Simulation time 208560431 ps
CPU time 6.6 seconds
Started Apr 23 02:49:43 PM PDT 24
Finished Apr 23 02:49:50 PM PDT 24
Peak memory 246720 kb
Host smart-8b476ed1-64d0-4dbc-bf56-9a2f04824266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281312136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2281312136
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1474474198
Short name T521
Test name
Test status
Simulation time 17497854182 ps
CPU time 69.94 seconds
Started Apr 23 02:49:48 PM PDT 24
Finished Apr 23 02:50:58 PM PDT 24
Peak memory 226164 kb
Host smart-90d5e6b8-fc22-4098-bf34-4d325f6427b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474474198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1474474198
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4159602586
Short name T468
Test name
Test status
Simulation time 54727584 ps
CPU time 0.88 seconds
Started Apr 23 02:49:43 PM PDT 24
Finished Apr 23 02:49:44 PM PDT 24
Peak memory 212724 kb
Host smart-3e8c28ba-61a8-48dd-a803-0f7d2160bc1c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159602586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.4159602586
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1792303654
Short name T226
Test name
Test status
Simulation time 59139857 ps
CPU time 0.94 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:49:52 PM PDT 24
Peak memory 209596 kb
Host smart-b20e3748-07bf-41e2-bfec-b2ddbd036e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792303654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1792303654
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.310314585
Short name T31
Test name
Test status
Simulation time 2804634204 ps
CPU time 9.76 seconds
Started Apr 23 02:49:46 PM PDT 24
Finished Apr 23 02:49:56 PM PDT 24
Peak memory 218004 kb
Host smart-7b8fb648-7545-497d-a1ff-be71ceb59e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310314585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.310314585
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3228925577
Short name T461
Test name
Test status
Simulation time 1087633278 ps
CPU time 2.77 seconds
Started Apr 23 02:49:45 PM PDT 24
Finished Apr 23 02:49:48 PM PDT 24
Peak memory 209592 kb
Host smart-39cbda11-cff9-4370-b446-a2abe44cbbee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228925577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3228925577
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1157993215
Short name T823
Test name
Test status
Simulation time 282070678 ps
CPU time 3.21 seconds
Started Apr 23 02:49:45 PM PDT 24
Finished Apr 23 02:49:49 PM PDT 24
Peak memory 218036 kb
Host smart-cad9096d-1a5c-4207-8940-632c0db320b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157993215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1157993215
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1793593276
Short name T791
Test name
Test status
Simulation time 416548184 ps
CPU time 15.96 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:50:09 PM PDT 24
Peak memory 226088 kb
Host smart-0753b08b-9320-454e-a151-987d017fb3c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793593276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1793593276
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2397917621
Short name T243
Test name
Test status
Simulation time 462971763 ps
CPU time 12.06 seconds
Started Apr 23 02:49:46 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 218088 kb
Host smart-1c5e4f7c-a00b-48c1-97de-d4770183bfc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397917621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2397917621
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.429945311
Short name T534
Test name
Test status
Simulation time 1177518902 ps
CPU time 6.08 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 217980 kb
Host smart-303900be-e0dc-4b62-8536-6d077b5da39a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429945311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.429945311
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2812788900
Short name T396
Test name
Test status
Simulation time 1122862653 ps
CPU time 10.88 seconds
Started Apr 23 02:49:51 PM PDT 24
Finished Apr 23 02:50:02 PM PDT 24
Peak memory 218044 kb
Host smart-3d83b0b8-4559-4a98-bbd2-2d315dbf1b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812788900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2812788900
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1606799839
Short name T861
Test name
Test status
Simulation time 113805195 ps
CPU time 3.65 seconds
Started Apr 23 02:49:43 PM PDT 24
Finished Apr 23 02:49:47 PM PDT 24
Peak memory 218264 kb
Host smart-744ef551-4f38-4270-adac-e8f67d33d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606799839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1606799839
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.878476306
Short name T266
Test name
Test status
Simulation time 449459971 ps
CPU time 24.05 seconds
Started Apr 23 02:49:43 PM PDT 24
Finished Apr 23 02:50:07 PM PDT 24
Peak memory 250980 kb
Host smart-9845de05-d841-4675-aa69-0a022506c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878476306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.878476306
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.51630184
Short name T698
Test name
Test status
Simulation time 231318313 ps
CPU time 7.98 seconds
Started Apr 23 02:49:45 PM PDT 24
Finished Apr 23 02:49:53 PM PDT 24
Peak memory 251004 kb
Host smart-57bd20c6-fdf5-498d-9952-2d236517f4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51630184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.51630184
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3487811665
Short name T413
Test name
Test status
Simulation time 7611761303 ps
CPU time 172.28 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:52:46 PM PDT 24
Peak memory 276652 kb
Host smart-2d22455d-611c-46af-8b55-d41b5580f14d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487811665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3487811665
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2926819592
Short name T676
Test name
Test status
Simulation time 13158015 ps
CPU time 0.98 seconds
Started Apr 23 02:49:42 PM PDT 24
Finished Apr 23 02:49:44 PM PDT 24
Peak memory 211628 kb
Host smart-9c3531d7-ffa9-470d-818d-bcee89df6249
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926819592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2926819592
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3281351564
Short name T76
Test name
Test status
Simulation time 21313376 ps
CPU time 1.21 seconds
Started Apr 23 02:49:51 PM PDT 24
Finished Apr 23 02:49:53 PM PDT 24
Peak memory 209580 kb
Host smart-2be59590-0326-43aa-8937-5a6ebd99eb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281351564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3281351564
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1325067864
Short name T800
Test name
Test status
Simulation time 1521255123 ps
CPU time 12.14 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:50:05 PM PDT 24
Peak memory 218036 kb
Host smart-6e3852c5-8f6b-4c37-9135-bc304ab53a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325067864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1325067864
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2479906184
Short name T137
Test name
Test status
Simulation time 67761814 ps
CPU time 1.76 seconds
Started Apr 23 02:49:54 PM PDT 24
Finished Apr 23 02:49:56 PM PDT 24
Peak memory 216928 kb
Host smart-b35f33ba-16d4-4bd8-9ecc-0d066d9394fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479906184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2479906184
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1225718550
Short name T324
Test name
Test status
Simulation time 132652193 ps
CPU time 3.77 seconds
Started Apr 23 02:49:46 PM PDT 24
Finished Apr 23 02:49:50 PM PDT 24
Peak memory 218036 kb
Host smart-659103ac-09d7-4c51-9f4a-391648bd740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225718550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1225718550
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2107579081
Short name T662
Test name
Test status
Simulation time 1060070835 ps
CPU time 10.63 seconds
Started Apr 23 02:49:51 PM PDT 24
Finished Apr 23 02:50:02 PM PDT 24
Peak memory 217980 kb
Host smart-c68ec39f-5fca-4683-93be-9d6b8d42fdd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107579081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2107579081
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3409427725
Short name T352
Test name
Test status
Simulation time 672081520 ps
CPU time 11.11 seconds
Started Apr 23 02:49:49 PM PDT 24
Finished Apr 23 02:50:01 PM PDT 24
Peak memory 217972 kb
Host smart-3ff62363-bcd2-4c97-9315-0ad39cb51660
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409427725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3409427725
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1518873365
Short name T414
Test name
Test status
Simulation time 1002718411 ps
CPU time 8.76 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 218044 kb
Host smart-3dbc2f9c-f645-43ff-975f-ae13b5c372fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518873365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1518873365
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.765442596
Short name T152
Test name
Test status
Simulation time 391763350 ps
CPU time 7.64 seconds
Started Apr 23 02:49:49 PM PDT 24
Finished Apr 23 02:49:57 PM PDT 24
Peak memory 218124 kb
Host smart-0c6be202-7c8c-4d41-91db-de609643d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765442596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.765442596
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1829045283
Short name T271
Test name
Test status
Simulation time 347357471 ps
CPU time 4.87 seconds
Started Apr 23 02:49:54 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 217892 kb
Host smart-f6fea17e-45f7-4389-bd0c-e92fcc322834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829045283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1829045283
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3591863360
Short name T622
Test name
Test status
Simulation time 668157815 ps
CPU time 20.95 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:50:12 PM PDT 24
Peak memory 251072 kb
Host smart-643c4ee5-562a-4592-bc47-296677dc5799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591863360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3591863360
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1474602216
Short name T457
Test name
Test status
Simulation time 658551077 ps
CPU time 9.86 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:50:02 PM PDT 24
Peak memory 245248 kb
Host smart-bfbd9630-1813-450c-90dc-920cd4c0957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474602216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1474602216
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3931639182
Short name T281
Test name
Test status
Simulation time 5293576028 ps
CPU time 58.94 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:50:50 PM PDT 24
Peak memory 250980 kb
Host smart-44848d5f-dab7-4b47-8e9f-9958fff508fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931639182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3931639182
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2940250983
Short name T242
Test name
Test status
Simulation time 52545896 ps
CPU time 0.94 seconds
Started Apr 23 02:49:54 PM PDT 24
Finished Apr 23 02:49:56 PM PDT 24
Peak memory 211660 kb
Host smart-e1c7c52d-5b45-45bb-b6d6-e4798e3b5258
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940250983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2940250983
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1919859866
Short name T582
Test name
Test status
Simulation time 120249614 ps
CPU time 0.96 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:49:54 PM PDT 24
Peak memory 209476 kb
Host smart-39039a50-06df-486b-a7a1-ede5857d2bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919859866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1919859866
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1560409712
Short name T30
Test name
Test status
Simulation time 1004964545 ps
CPU time 18.74 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:50:10 PM PDT 24
Peak memory 218068 kb
Host smart-e28596de-3f73-46c8-83e9-3611bfbb73d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560409712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1560409712
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3401921827
Short name T638
Test name
Test status
Simulation time 2573825190 ps
CPU time 7.74 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:49:58 PM PDT 24
Peak memory 217284 kb
Host smart-44e1f688-401d-40e5-8040-d43cf25cdd1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401921827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3401921827
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.156761786
Short name T755
Test name
Test status
Simulation time 241357471 ps
CPU time 2.1 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:49:53 PM PDT 24
Peak memory 217936 kb
Host smart-025091e4-f7f9-43b1-9555-b723705fa034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156761786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.156761786
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3339495090
Short name T157
Test name
Test status
Simulation time 264209156 ps
CPU time 11.73 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:50:07 PM PDT 24
Peak memory 226068 kb
Host smart-95952cf9-6271-40d3-828a-7f97c473a0b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339495090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3339495090
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.820818485
Short name T399
Test name
Test status
Simulation time 283073055 ps
CPU time 12.47 seconds
Started Apr 23 02:49:51 PM PDT 24
Finished Apr 23 02:50:05 PM PDT 24
Peak memory 217948 kb
Host smart-3a84dea2-da75-4824-a4b2-57cb243ea600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820818485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.820818485
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3174115796
Short name T395
Test name
Test status
Simulation time 4401747880 ps
CPU time 17.69 seconds
Started Apr 23 02:49:51 PM PDT 24
Finished Apr 23 02:50:10 PM PDT 24
Peak memory 218068 kb
Host smart-9102f803-9264-4519-b7bf-ad5134914c9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174115796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3174115796
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3549617420
Short name T245
Test name
Test status
Simulation time 3806588376 ps
CPU time 17.95 seconds
Started Apr 23 02:49:51 PM PDT 24
Finished Apr 23 02:50:09 PM PDT 24
Peak memory 218140 kb
Host smart-71911a76-6043-4688-9633-5983a3d469ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549617420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3549617420
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2974045426
Short name T728
Test name
Test status
Simulation time 40397590 ps
CPU time 2.56 seconds
Started Apr 23 02:49:51 PM PDT 24
Finished Apr 23 02:49:55 PM PDT 24
Peak memory 214300 kb
Host smart-8cbaf880-edd8-4e4a-964e-f57de2ac4fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974045426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2974045426
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3763112623
Short name T86
Test name
Test status
Simulation time 855896936 ps
CPU time 19.83 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:50:14 PM PDT 24
Peak memory 250840 kb
Host smart-cc425dcd-b346-4bb7-94bd-f12e8ce6d570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763112623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3763112623
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.527524975
Short name T567
Test name
Test status
Simulation time 261721039 ps
CPU time 11 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:50:04 PM PDT 24
Peak memory 246348 kb
Host smart-931a281b-e689-4872-bbb5-d47c33e8ced0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527524975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.527524975
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2261655507
Short name T3
Test name
Test status
Simulation time 2465040317 ps
CPU time 26.16 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:50:20 PM PDT 24
Peak memory 225900 kb
Host smart-d5d76b4a-d58f-4816-9f80-8e4ddcb7cfd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261655507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2261655507
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1740365473
Short name T156
Test name
Test status
Simulation time 181054158614 ps
CPU time 1198.4 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 03:09:52 PM PDT 24
Peak memory 726120 kb
Host smart-9a301519-5c93-4bbd-be76-f03b509f4ac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1740365473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1740365473
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3324157994
Short name T409
Test name
Test status
Simulation time 14571167 ps
CPU time 0.88 seconds
Started Apr 23 02:49:50 PM PDT 24
Finished Apr 23 02:49:51 PM PDT 24
Peak memory 211640 kb
Host smart-3789345f-f58e-4281-a9ba-02f6b3ebc1a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324157994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3324157994
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2770286124
Short name T706
Test name
Test status
Simulation time 77025103 ps
CPU time 1.26 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:49:54 PM PDT 24
Peak memory 209484 kb
Host smart-c1a36bc1-ede3-4a59-a26c-ae41e17b0b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770286124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2770286124
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3793599698
Short name T616
Test name
Test status
Simulation time 2514496405 ps
CPU time 14.57 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:50:08 PM PDT 24
Peak memory 218060 kb
Host smart-89df99c6-c34d-4850-b3a2-be6e53d73634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793599698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3793599698
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1103258903
Short name T377
Test name
Test status
Simulation time 2013119169 ps
CPU time 11.24 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:50:05 PM PDT 24
Peak memory 216896 kb
Host smart-3abf4c25-4d2a-4d03-bda7-c30d16965ac6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103258903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1103258903
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2017594782
Short name T269
Test name
Test status
Simulation time 186788830 ps
CPU time 2.2 seconds
Started Apr 23 02:49:54 PM PDT 24
Finished Apr 23 02:49:57 PM PDT 24
Peak memory 218076 kb
Host smart-41f207b4-de31-4025-a7f3-397a69e72a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017594782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2017594782
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3774554348
Short name T47
Test name
Test status
Simulation time 1422188557 ps
CPU time 11.87 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:50:06 PM PDT 24
Peak memory 218764 kb
Host smart-3fa729ce-98ac-4394-b153-966ecaebe497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774554348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3774554348
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3557665062
Short name T677
Test name
Test status
Simulation time 2121142940 ps
CPU time 15.77 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:50:10 PM PDT 24
Peak memory 217972 kb
Host smart-764f0427-079f-47fb-83cb-51206c929ac1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557665062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3557665062
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3831548801
Short name T429
Test name
Test status
Simulation time 562517889 ps
CPU time 14.05 seconds
Started Apr 23 02:49:56 PM PDT 24
Finished Apr 23 02:50:11 PM PDT 24
Peak memory 218004 kb
Host smart-f0ac663c-4f13-45f2-8c66-42c51b445046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831548801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3831548801
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2429961710
Short name T747
Test name
Test status
Simulation time 3197713399 ps
CPU time 10.85 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:50:04 PM PDT 24
Peak memory 218128 kb
Host smart-f019129e-c97e-4aad-88b5-f80b0d239465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429961710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2429961710
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2252712412
Short name T630
Test name
Test status
Simulation time 87892942 ps
CPU time 1.68 seconds
Started Apr 23 02:49:57 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 213708 kb
Host smart-321146b1-d935-4645-8cdb-6d8b9d415e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252712412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2252712412
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.526995869
Short name T678
Test name
Test status
Simulation time 806090120 ps
CPU time 30.63 seconds
Started Apr 23 02:49:54 PM PDT 24
Finished Apr 23 02:50:25 PM PDT 24
Peak memory 250976 kb
Host smart-7a5dfd2b-1383-4ea0-855b-e1e55248ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526995869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.526995869
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1942934507
Short name T664
Test name
Test status
Simulation time 253434579 ps
CPU time 6.68 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:50:02 PM PDT 24
Peak memory 251008 kb
Host smart-3f4a8378-c1be-44d4-992d-0df95d377f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942934507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1942934507
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1370127814
Short name T632
Test name
Test status
Simulation time 25334023 ps
CPU time 0.87 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:49:56 PM PDT 24
Peak memory 211668 kb
Host smart-dc56066a-e196-4a1f-ad36-3aeb53e867aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370127814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1370127814
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.608376332
Short name T727
Test name
Test status
Simulation time 50223961 ps
CPU time 1.29 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:49:57 PM PDT 24
Peak memory 209688 kb
Host smart-f3f0171a-82a1-44b7-9e24-7107dae402e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608376332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.608376332
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3388884580
Short name T436
Test name
Test status
Simulation time 1730230277 ps
CPU time 18.84 seconds
Started Apr 23 02:49:56 PM PDT 24
Finished Apr 23 02:50:15 PM PDT 24
Peak memory 217988 kb
Host smart-7b5d3e6f-b52c-4b09-b566-c65c74aad6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388884580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3388884580
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1502191716
Short name T358
Test name
Test status
Simulation time 540332190 ps
CPU time 7.89 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:50:03 PM PDT 24
Peak memory 217000 kb
Host smart-726becd8-a4df-4b86-b796-c2466456e22b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502191716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1502191716
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.407779314
Short name T814
Test name
Test status
Simulation time 67712268 ps
CPU time 1.55 seconds
Started Apr 23 02:49:56 PM PDT 24
Finished Apr 23 02:49:58 PM PDT 24
Peak memory 217996 kb
Host smart-e5eff707-6ca4-48f8-9b0d-31c1b95f5888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407779314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.407779314
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4101734766
Short name T225
Test name
Test status
Simulation time 1168167632 ps
CPU time 11.92 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:50:08 PM PDT 24
Peak memory 226160 kb
Host smart-26ed36e3-50b0-4f04-90d5-e8fb8b10c0bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101734766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4101734766
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.4228256592
Short name T312
Test name
Test status
Simulation time 481265701 ps
CPU time 12.25 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:50:08 PM PDT 24
Peak memory 218036 kb
Host smart-3b37c0da-1c72-4dcf-9598-c6fe1e950dbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228256592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.4228256592
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.676647000
Short name T845
Test name
Test status
Simulation time 555436834 ps
CPU time 11.07 seconds
Started Apr 23 02:49:57 PM PDT 24
Finished Apr 23 02:50:08 PM PDT 24
Peak memory 218072 kb
Host smart-9afb5421-962b-4a3f-a78e-739a31a3289a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676647000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.676647000
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4179864201
Short name T571
Test name
Test status
Simulation time 470200303 ps
CPU time 7.46 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:50:03 PM PDT 24
Peak memory 218060 kb
Host smart-424bc0b7-fcdc-4edb-95c8-68ae9384c27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179864201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4179864201
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1321597951
Short name T799
Test name
Test status
Simulation time 1553420556 ps
CPU time 7.92 seconds
Started Apr 23 02:49:54 PM PDT 24
Finished Apr 23 02:50:02 PM PDT 24
Peak memory 217792 kb
Host smart-820ec957-a299-4fa6-9e1e-708fc43050e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321597951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1321597951
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2253377335
Short name T473
Test name
Test status
Simulation time 163076904 ps
CPU time 20.29 seconds
Started Apr 23 02:49:52 PM PDT 24
Finished Apr 23 02:50:13 PM PDT 24
Peak memory 251032 kb
Host smart-3dfaa38e-a644-4ca3-8d76-3e1bcfb256ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253377335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2253377335
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1278782592
Short name T633
Test name
Test status
Simulation time 38993263 ps
CPU time 7.04 seconds
Started Apr 23 02:49:57 PM PDT 24
Finished Apr 23 02:50:04 PM PDT 24
Peak memory 250924 kb
Host smart-f303606d-99c0-4c8b-94d9-11a78dcb779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278782592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1278782592
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2658541264
Short name T60
Test name
Test status
Simulation time 1812655111 ps
CPU time 36.5 seconds
Started Apr 23 02:49:55 PM PDT 24
Finished Apr 23 02:50:32 PM PDT 24
Peak memory 251048 kb
Host smart-ab98e926-e879-4002-8fc6-f68c6d7f5a1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658541264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2658541264
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3110491313
Short name T506
Test name
Test status
Simulation time 24820865 ps
CPU time 0.83 seconds
Started Apr 23 02:49:53 PM PDT 24
Finished Apr 23 02:49:55 PM PDT 24
Peak memory 211688 kb
Host smart-81ce0e52-5e66-48ab-91e3-3e4c4dfee282
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110491313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3110491313
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1469815526
Short name T612
Test name
Test status
Simulation time 20447220 ps
CPU time 0.94 seconds
Started Apr 23 02:47:13 PM PDT 24
Finished Apr 23 02:47:14 PM PDT 24
Peak memory 209564 kb
Host smart-0f4676cc-149a-4bf2-91a6-33edaa39484a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469815526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1469815526
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3603817880
Short name T213
Test name
Test status
Simulation time 13424185 ps
CPU time 0.8 seconds
Started Apr 23 02:47:12 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 209364 kb
Host smart-33b31e9a-d54a-42da-afaf-303e19087085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603817880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3603817880
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.487121405
Short name T434
Test name
Test status
Simulation time 408710861 ps
CPU time 13.57 seconds
Started Apr 23 02:47:11 PM PDT 24
Finished Apr 23 02:47:25 PM PDT 24
Peak memory 217924 kb
Host smart-e83d79e4-c71d-44ae-b87c-b42d817dedf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487121405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.487121405
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3689188538
Short name T406
Test name
Test status
Simulation time 243998614 ps
CPU time 4.79 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:16 PM PDT 24
Peak memory 209588 kb
Host smart-2e70b91a-48df-4978-918d-02cbf2b46c48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689188538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3689188538
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3462985170
Short name T230
Test name
Test status
Simulation time 1452875331 ps
CPU time 44.13 seconds
Started Apr 23 02:47:11 PM PDT 24
Finished Apr 23 02:47:56 PM PDT 24
Peak memory 217992 kb
Host smart-8360debc-73f4-4d6c-b132-0f85deaeedc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462985170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3462985170
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1740929552
Short name T374
Test name
Test status
Simulation time 5554555773 ps
CPU time 13.26 seconds
Started Apr 23 02:47:12 PM PDT 24
Finished Apr 23 02:47:26 PM PDT 24
Peak memory 217660 kb
Host smart-e65b5856-7492-4d05-8793-a3d5ae8e5ce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740929552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
740929552
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1947662879
Short name T711
Test name
Test status
Simulation time 312109933 ps
CPU time 9.16 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:47:24 PM PDT 24
Peak memory 217972 kb
Host smart-90b8a050-48b5-4fe2-aa9b-b689ae88f131
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947662879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1947662879
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.605897917
Short name T326
Test name
Test status
Simulation time 2501521872 ps
CPU time 34.01 seconds
Started Apr 23 02:47:12 PM PDT 24
Finished Apr 23 02:47:46 PM PDT 24
Peak memory 213304 kb
Host smart-851252eb-0126-44cc-b7d6-384a697e0ea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605897917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.605897917
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.464448421
Short name T671
Test name
Test status
Simulation time 185955122 ps
CPU time 5.27 seconds
Started Apr 23 02:47:11 PM PDT 24
Finished Apr 23 02:47:16 PM PDT 24
Peak memory 213292 kb
Host smart-bbbd992d-2a45-48c7-9784-b9d7ed9dcff2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464448421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.464448421
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2423225482
Short name T445
Test name
Test status
Simulation time 5954395242 ps
CPU time 40.4 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:47:55 PM PDT 24
Peak memory 267524 kb
Host smart-6a27c428-e880-4d1b-884d-0b04440555d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423225482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2423225482
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1812114623
Short name T732
Test name
Test status
Simulation time 3749963238 ps
CPU time 34.16 seconds
Started Apr 23 02:47:11 PM PDT 24
Finished Apr 23 02:47:46 PM PDT 24
Peak memory 251104 kb
Host smart-8942480b-55c1-454a-b570-5a0bf62eb188
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812114623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1812114623
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3799705675
Short name T422
Test name
Test status
Simulation time 85369039 ps
CPU time 3.87 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:15 PM PDT 24
Peak memory 218016 kb
Host smart-8a257390-2e79-4225-8112-254d8bdd7b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799705675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3799705675
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3490008502
Short name T471
Test name
Test status
Simulation time 826762869 ps
CPU time 24.64 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:36 PM PDT 24
Peak memory 217812 kb
Host smart-c527e9b5-27b8-4eda-b947-dd4ca3d8db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490008502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3490008502
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2772914480
Short name T443
Test name
Test status
Simulation time 6039744209 ps
CPU time 13.88 seconds
Started Apr 23 02:47:16 PM PDT 24
Finished Apr 23 02:47:30 PM PDT 24
Peak memory 220060 kb
Host smart-7c6d602a-49fa-4754-8dab-6e7daab2e43a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772914480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2772914480
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3359581546
Short name T690
Test name
Test status
Simulation time 545023047 ps
CPU time 13.51 seconds
Started Apr 23 02:47:12 PM PDT 24
Finished Apr 23 02:47:26 PM PDT 24
Peak memory 218012 kb
Host smart-830a8d61-10a8-4a59-91b9-284c24a9e237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359581546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3359581546
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.79991187
Short name T141
Test name
Test status
Simulation time 282049332 ps
CPU time 12.2 seconds
Started Apr 23 02:47:11 PM PDT 24
Finished Apr 23 02:47:24 PM PDT 24
Peak memory 217972 kb
Host smart-4f8c0f66-d6a2-43a7-b5a8-479765d50cb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79991187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.79991187
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.656387453
Short name T40
Test name
Test status
Simulation time 160970289 ps
CPU time 7.93 seconds
Started Apr 23 02:47:09 PM PDT 24
Finished Apr 23 02:47:17 PM PDT 24
Peak memory 218068 kb
Host smart-9ae7abc5-fd17-42f1-b7f4-d4b523d9125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656387453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.656387453
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4011486423
Short name T867
Test name
Test status
Simulation time 233021871 ps
CPU time 3.64 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:14 PM PDT 24
Peak memory 217900 kb
Host smart-94dd3ff4-1ee6-4478-b208-ebb981ca3f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011486423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4011486423
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1973982222
Short name T72
Test name
Test status
Simulation time 703951699 ps
CPU time 37.02 seconds
Started Apr 23 02:47:09 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 250492 kb
Host smart-97c05925-bf35-4156-8888-644efc1d565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973982222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1973982222
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2446797989
Short name T452
Test name
Test status
Simulation time 509253052 ps
CPU time 2.98 seconds
Started Apr 23 02:47:09 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 217960 kb
Host smart-25c3f1e0-1a1b-477a-8479-037204bfd645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446797989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2446797989
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3431308920
Short name T177
Test name
Test status
Simulation time 4133702743 ps
CPU time 110.06 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:49:04 PM PDT 24
Peak memory 283856 kb
Host smart-d8344b8e-4d75-4000-82aa-2c0ed22be3a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431308920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3431308920
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.232306119
Short name T694
Test name
Test status
Simulation time 21260628 ps
CPU time 0.96 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:11 PM PDT 24
Peak memory 211604 kb
Host smart-2b153888-448e-4d03-bba7-76fb7ce16376
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232306119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.232306119
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.131826874
Short name T334
Test name
Test status
Simulation time 38379938 ps
CPU time 0.94 seconds
Started Apr 23 02:47:19 PM PDT 24
Finished Apr 23 02:47:20 PM PDT 24
Peak memory 209540 kb
Host smart-252e197c-8862-4d18-b242-270a5bb73bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131826874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.131826874
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3439940170
Short name T305
Test name
Test status
Simulation time 3136753575 ps
CPU time 12.85 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:47:27 PM PDT 24
Peak memory 218132 kb
Host smart-479f5fad-c364-4833-a4fc-114a11f081e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439940170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3439940170
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.743120423
Short name T505
Test name
Test status
Simulation time 636380400 ps
CPU time 16.37 seconds
Started Apr 23 02:47:15 PM PDT 24
Finished Apr 23 02:47:32 PM PDT 24
Peak memory 209544 kb
Host smart-e39ba66b-aac9-4c2c-b2e3-9d800ca783c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743120423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.743120423
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1357774161
Short name T235
Test name
Test status
Simulation time 1710578184 ps
CPU time 31.56 seconds
Started Apr 23 02:47:15 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 218012 kb
Host smart-23c17da3-60cf-43e4-8e9d-f9c9658d2dc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357774161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1357774161
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1069846575
Short name T538
Test name
Test status
Simulation time 91990125 ps
CPU time 1.82 seconds
Started Apr 23 02:47:16 PM PDT 24
Finished Apr 23 02:47:18 PM PDT 24
Peak memory 217804 kb
Host smart-c32cb81f-5182-4dc7-9ed1-1a682cc59475
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069846575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
069846575
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.669458617
Short name T570
Test name
Test status
Simulation time 452690901 ps
CPU time 4.39 seconds
Started Apr 23 02:47:15 PM PDT 24
Finished Apr 23 02:47:19 PM PDT 24
Peak memory 217936 kb
Host smart-60494dda-d4cd-4cbd-83e2-cd16584e632b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669458617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.669458617
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2698298735
Short name T853
Test name
Test status
Simulation time 5047208783 ps
CPU time 36.75 seconds
Started Apr 23 02:47:16 PM PDT 24
Finished Apr 23 02:47:53 PM PDT 24
Peak memory 214192 kb
Host smart-21a5889e-06e8-4149-a20a-fcf9857115fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698298735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2698298735
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3799742336
Short name T263
Test name
Test status
Simulation time 2434870818 ps
CPU time 7.88 seconds
Started Apr 23 02:47:16 PM PDT 24
Finished Apr 23 02:47:24 PM PDT 24
Peak memory 214020 kb
Host smart-d9e45a3f-7801-4539-bbf9-a5bc8b1cafaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799742336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3799742336
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3919939876
Short name T88
Test name
Test status
Simulation time 2452472004 ps
CPU time 52.16 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:48:07 PM PDT 24
Peak memory 283828 kb
Host smart-ca06c3e7-f4b2-4c16-a271-4d123cda35c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919939876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3919939876
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4014164513
Short name T590
Test name
Test status
Simulation time 1635498593 ps
CPU time 17.94 seconds
Started Apr 23 02:47:15 PM PDT 24
Finished Apr 23 02:47:34 PM PDT 24
Peak memory 249356 kb
Host smart-9748d272-8edc-48ef-af0f-6aa2fd591cc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014164513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.4014164513
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3197491899
Short name T553
Test name
Test status
Simulation time 180801269 ps
CPU time 2.1 seconds
Started Apr 23 02:47:12 PM PDT 24
Finished Apr 23 02:47:15 PM PDT 24
Peak memory 218016 kb
Host smart-6ceab7ba-665a-420f-a7e5-fe9739bab4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197491899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3197491899
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2424797724
Short name T63
Test name
Test status
Simulation time 1584904522 ps
CPU time 8.55 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:47:23 PM PDT 24
Peak memory 217888 kb
Host smart-ea9fbf3f-4212-46ab-b957-bbecd40bd469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424797724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2424797724
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4111323388
Short name T539
Test name
Test status
Simulation time 1270715781 ps
CPU time 10.59 seconds
Started Apr 23 02:47:15 PM PDT 24
Finished Apr 23 02:47:26 PM PDT 24
Peak memory 218060 kb
Host smart-8bbb96f3-f86f-442d-91f8-2c3bf09b5641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111323388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4111323388
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4134790603
Short name T279
Test name
Test status
Simulation time 1489279357 ps
CPU time 11.48 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:47:26 PM PDT 24
Peak memory 218072 kb
Host smart-0044cc32-5d88-43c8-86be-6c1beac1d86d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134790603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4134790603
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1183617085
Short name T767
Test name
Test status
Simulation time 2325366219 ps
CPU time 11.85 seconds
Started Apr 23 02:47:13 PM PDT 24
Finished Apr 23 02:47:25 PM PDT 24
Peak memory 218068 kb
Host smart-d64703f5-c0fa-4ec9-9e63-281d3db31629
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183617085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
183617085
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.4191730882
Short name T735
Test name
Test status
Simulation time 389107078 ps
CPU time 8.54 seconds
Started Apr 23 02:47:14 PM PDT 24
Finished Apr 23 02:47:22 PM PDT 24
Peak memory 218060 kb
Host smart-29fc19af-4389-454e-8108-529ddd306229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191730882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.4191730882
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4289409736
Short name T734
Test name
Test status
Simulation time 1158170909 ps
CPU time 3.82 seconds
Started Apr 23 02:47:13 PM PDT 24
Finished Apr 23 02:47:17 PM PDT 24
Peak memory 218332 kb
Host smart-e4e8599f-68b5-43ab-a375-a6def9812d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289409736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4289409736
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2760725056
Short name T142
Test name
Test status
Simulation time 1373482584 ps
CPU time 31.76 seconds
Started Apr 23 02:47:10 PM PDT 24
Finished Apr 23 02:47:42 PM PDT 24
Peak memory 250836 kb
Host smart-838afdc2-b7d7-4618-a1f7-e7bc70001f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760725056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2760725056
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2588471060
Short name T362
Test name
Test status
Simulation time 264651857 ps
CPU time 4.39 seconds
Started Apr 23 02:47:12 PM PDT 24
Finished Apr 23 02:47:17 PM PDT 24
Peak memory 226468 kb
Host smart-94f21dd3-993a-4c01-9b26-92ec13cfd3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588471060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2588471060
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4064349284
Short name T273
Test name
Test status
Simulation time 8597662547 ps
CPU time 368.54 seconds
Started Apr 23 02:47:16 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 251088 kb
Host smart-e8b3bddf-69a8-49dd-bd58-57ef547bc8ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064349284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4064349284
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1242204024
Short name T94
Test name
Test status
Simulation time 62183261130 ps
CPU time 4253.87 seconds
Started Apr 23 02:47:18 PM PDT 24
Finished Apr 23 03:58:13 PM PDT 24
Peak memory 955680 kb
Host smart-de34be58-5308-4dd7-be7d-854c54b62d21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1242204024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1242204024
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1749638010
Short name T363
Test name
Test status
Simulation time 11526755 ps
CPU time 0.98 seconds
Started Apr 23 02:47:12 PM PDT 24
Finished Apr 23 02:47:13 PM PDT 24
Peak memory 211660 kb
Host smart-dc5748cb-c8db-412d-affe-11bedac48165
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749638010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1749638010
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1847152314
Short name T394
Test name
Test status
Simulation time 70983510 ps
CPU time 1.13 seconds
Started Apr 23 02:47:26 PM PDT 24
Finished Apr 23 02:47:27 PM PDT 24
Peak memory 209536 kb
Host smart-1fa5dcc2-6834-4ecd-9ae6-eef665993775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847152314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1847152314
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.500934786
Short name T54
Test name
Test status
Simulation time 10903855 ps
CPU time 0.85 seconds
Started Apr 23 02:47:23 PM PDT 24
Finished Apr 23 02:47:24 PM PDT 24
Peak memory 209368 kb
Host smart-eff5fa84-a956-4988-8e31-44f2b041814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500934786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.500934786
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3991390432
Short name T579
Test name
Test status
Simulation time 301980822 ps
CPU time 13.02 seconds
Started Apr 23 02:47:21 PM PDT 24
Finished Apr 23 02:47:34 PM PDT 24
Peak memory 217924 kb
Host smart-5ff21cb5-34ff-41ef-95e2-ef3cfdece6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991390432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3991390432
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2952205154
Short name T719
Test name
Test status
Simulation time 1405218336 ps
CPU time 10.05 seconds
Started Apr 23 02:47:23 PM PDT 24
Finished Apr 23 02:47:33 PM PDT 24
Peak memory 209612 kb
Host smart-89712a86-6879-4cbd-8e21-391db501cfe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952205154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2952205154
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3602871455
Short name T425
Test name
Test status
Simulation time 3763406337 ps
CPU time 98.35 seconds
Started Apr 23 02:47:22 PM PDT 24
Finished Apr 23 02:49:00 PM PDT 24
Peak memory 218984 kb
Host smart-13b883bd-23fb-48ef-ba17-77fa75d987fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602871455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3602871455
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2418272615
Short name T459
Test name
Test status
Simulation time 6436059843 ps
CPU time 7.44 seconds
Started Apr 23 02:47:22 PM PDT 24
Finished Apr 23 02:47:30 PM PDT 24
Peak memory 217836 kb
Host smart-d59711b2-7e7b-4ad4-a328-9d1768463059
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418272615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
418272615
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.774587763
Short name T872
Test name
Test status
Simulation time 3305344639 ps
CPU time 11.8 seconds
Started Apr 23 02:47:21 PM PDT 24
Finished Apr 23 02:47:33 PM PDT 24
Peak memory 218056 kb
Host smart-6710c81f-48db-41a9-8f41-6db9247e591b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774587763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.774587763
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.450507662
Short name T820
Test name
Test status
Simulation time 2689713278 ps
CPU time 41.13 seconds
Started Apr 23 02:47:22 PM PDT 24
Finished Apr 23 02:48:04 PM PDT 24
Peak memory 213956 kb
Host smart-de550222-520f-4239-9416-f747903e5dfc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450507662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.450507662
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3845152859
Short name T494
Test name
Test status
Simulation time 349172695 ps
CPU time 4.59 seconds
Started Apr 23 02:47:22 PM PDT 24
Finished Apr 23 02:47:27 PM PDT 24
Peak memory 213364 kb
Host smart-2b99cb7c-2f44-4ff5-9c1c-7593eb75e9c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845152859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3845152859
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.13874805
Short name T646
Test name
Test status
Simulation time 4776731121 ps
CPU time 55.81 seconds
Started Apr 23 02:47:25 PM PDT 24
Finished Apr 23 02:48:21 PM PDT 24
Peak memory 267724 kb
Host smart-f2b92d26-92ee-49a9-a5af-264783dc7b60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13874805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
state_failure.13874805
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2657576515
Short name T578
Test name
Test status
Simulation time 4277095549 ps
CPU time 23.82 seconds
Started Apr 23 02:47:21 PM PDT 24
Finished Apr 23 02:47:46 PM PDT 24
Peak memory 247268 kb
Host smart-e5e31519-d4c0-4bbf-912b-482ca81c2cfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657576515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2657576515
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.658005976
Short name T784
Test name
Test status
Simulation time 135027466 ps
CPU time 2.81 seconds
Started Apr 23 02:47:19 PM PDT 24
Finished Apr 23 02:47:23 PM PDT 24
Peak memory 218140 kb
Host smart-ac30d3f2-be34-45f8-be6d-77c14cfe064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658005976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.658005976
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3698094658
Short name T367
Test name
Test status
Simulation time 324262886 ps
CPU time 18.07 seconds
Started Apr 23 02:47:18 PM PDT 24
Finished Apr 23 02:47:37 PM PDT 24
Peak memory 214504 kb
Host smart-e49dfdb2-dc8d-47ec-8bbe-f5d2e4d1d83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698094658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3698094658
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1518536153
Short name T431
Test name
Test status
Simulation time 280556215 ps
CPU time 8.67 seconds
Started Apr 23 02:47:22 PM PDT 24
Finished Apr 23 02:47:31 PM PDT 24
Peak memory 218444 kb
Host smart-64cbb61d-5ffc-4578-ba53-7329a9ce1c34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518536153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1518536153
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2915979866
Short name T740
Test name
Test status
Simulation time 516610334 ps
CPU time 10.65 seconds
Started Apr 23 02:47:25 PM PDT 24
Finished Apr 23 02:47:36 PM PDT 24
Peak memory 217996 kb
Host smart-c989bca8-4797-43f4-bd8b-336e233a430c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915979866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2915979866
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2912605514
Short name T701
Test name
Test status
Simulation time 1022789401 ps
CPU time 10.02 seconds
Started Apr 23 02:47:23 PM PDT 24
Finished Apr 23 02:47:34 PM PDT 24
Peak memory 218052 kb
Host smart-cb9fdd1b-2ce5-422e-b066-3748a1cc46d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912605514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
912605514
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2575043986
Short name T492
Test name
Test status
Simulation time 257002346 ps
CPU time 7.93 seconds
Started Apr 23 02:47:18 PM PDT 24
Finished Apr 23 02:47:26 PM PDT 24
Peak memory 218076 kb
Host smart-229facd6-b46b-401e-a4f2-b6e52fdcd0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575043986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2575043986
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2446887755
Short name T67
Test name
Test status
Simulation time 19323570 ps
CPU time 1.6 seconds
Started Apr 23 02:47:19 PM PDT 24
Finished Apr 23 02:47:21 PM PDT 24
Peak memory 213416 kb
Host smart-3e9c0841-b93a-4ed8-ad56-d8a93b67e15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446887755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2446887755
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3576418351
Short name T220
Test name
Test status
Simulation time 985015849 ps
CPU time 22.02 seconds
Started Apr 23 02:47:17 PM PDT 24
Finished Apr 23 02:47:39 PM PDT 24
Peak memory 251012 kb
Host smart-aa8cfa29-6089-4b81-a861-0482a2389104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576418351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3576418351
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.830427096
Short name T572
Test name
Test status
Simulation time 156740984 ps
CPU time 8.35 seconds
Started Apr 23 02:47:18 PM PDT 24
Finished Apr 23 02:47:27 PM PDT 24
Peak memory 251040 kb
Host smart-6f9660aa-1494-40a5-b8b6-0a613263aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830427096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.830427096
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.306015654
Short name T317
Test name
Test status
Simulation time 9777104758 ps
CPU time 295.6 seconds
Started Apr 23 02:47:26 PM PDT 24
Finished Apr 23 02:52:22 PM PDT 24
Peak memory 251020 kb
Host smart-39bd9db5-31b6-4bc4-aa0e-8b31e3aadf68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306015654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.306015654
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.222844255
Short name T199
Test name
Test status
Simulation time 12200533 ps
CPU time 0.9 seconds
Started Apr 23 02:47:19 PM PDT 24
Finished Apr 23 02:47:20 PM PDT 24
Peak memory 212812 kb
Host smart-665b2f72-f333-4ba3-b454-6e83dde94497
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222844255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.222844255
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1494172069
Short name T306
Test name
Test status
Simulation time 23723893 ps
CPU time 0.84 seconds
Started Apr 23 02:47:37 PM PDT 24
Finished Apr 23 02:47:38 PM PDT 24
Peak memory 209368 kb
Host smart-99c7ae7c-eda6-4d39-9fb3-3c87d2460d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494172069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1494172069
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3628984788
Short name T202
Test name
Test status
Simulation time 18851778 ps
CPU time 0.91 seconds
Started Apr 23 02:47:31 PM PDT 24
Finished Apr 23 02:47:32 PM PDT 24
Peak memory 209492 kb
Host smart-b8cda116-790c-46fb-937d-d186a2d7deb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628984788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3628984788
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3407958789
Short name T741
Test name
Test status
Simulation time 789840632 ps
CPU time 15.56 seconds
Started Apr 23 02:47:29 PM PDT 24
Finished Apr 23 02:47:45 PM PDT 24
Peak memory 217960 kb
Host smart-9e83acef-667f-470b-ac0c-0838c717c0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407958789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3407958789
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4243741203
Short name T27
Test name
Test status
Simulation time 652984852 ps
CPU time 8.1 seconds
Started Apr 23 02:47:34 PM PDT 24
Finished Apr 23 02:47:43 PM PDT 24
Peak memory 217088 kb
Host smart-a8264654-dfbd-49b0-87b3-fdc643a4a836
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243741203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4243741203
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.4123193159
Short name T532
Test name
Test status
Simulation time 1596508046 ps
CPU time 31.46 seconds
Started Apr 23 02:47:34 PM PDT 24
Finished Apr 23 02:48:05 PM PDT 24
Peak memory 218012 kb
Host smart-da1e4a33-06cd-4b0e-927d-bbd359ccec5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123193159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.4123193159
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1242291057
Short name T392
Test name
Test status
Simulation time 3930980437 ps
CPU time 9.06 seconds
Started Apr 23 02:47:33 PM PDT 24
Finished Apr 23 02:47:43 PM PDT 24
Peak memory 217840 kb
Host smart-bb9cd99d-70ef-4e01-9a11-a756f6f2a7d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242291057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
242291057
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3059988446
Short name T84
Test name
Test status
Simulation time 650533199 ps
CPU time 3.22 seconds
Started Apr 23 02:47:31 PM PDT 24
Finished Apr 23 02:47:34 PM PDT 24
Peak memory 217992 kb
Host smart-45bdb27d-5bcd-4590-8ea1-c8addf939845
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059988446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3059988446
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2135600967
Short name T61
Test name
Test status
Simulation time 2193574213 ps
CPU time 32.52 seconds
Started Apr 23 02:47:33 PM PDT 24
Finished Apr 23 02:48:06 PM PDT 24
Peak memory 213428 kb
Host smart-05080cfe-baa4-460e-930e-36417feb21ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135600967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2135600967
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1208384911
Short name T373
Test name
Test status
Simulation time 78486370 ps
CPU time 2.87 seconds
Started Apr 23 02:47:31 PM PDT 24
Finished Apr 23 02:47:35 PM PDT 24
Peak memory 213148 kb
Host smart-3cbd194f-02fc-41af-96ea-95298e95f967
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208384911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1208384911
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3425084823
Short name T858
Test name
Test status
Simulation time 916722206 ps
CPU time 45.44 seconds
Started Apr 23 02:47:31 PM PDT 24
Finished Apr 23 02:48:17 PM PDT 24
Peak memory 267416 kb
Host smart-23bd0426-b6e6-4e11-bd43-bd05db61dd68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425084823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3425084823
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.388809908
Short name T674
Test name
Test status
Simulation time 370015917 ps
CPU time 11.87 seconds
Started Apr 23 02:47:32 PM PDT 24
Finished Apr 23 02:47:44 PM PDT 24
Peak memory 221968 kb
Host smart-cf7fcca0-9283-4f30-91dc-da97febb9b22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388809908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.388809908
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3914503695
Short name T856
Test name
Test status
Simulation time 277309898 ps
CPU time 2.92 seconds
Started Apr 23 02:47:30 PM PDT 24
Finished Apr 23 02:47:33 PM PDT 24
Peak memory 217972 kb
Host smart-d445b4a7-e7a8-417f-96e2-abd43d48b3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914503695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3914503695
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2590540723
Short name T825
Test name
Test status
Simulation time 1770368183 ps
CPU time 11.81 seconds
Started Apr 23 02:47:28 PM PDT 24
Finished Apr 23 02:47:40 PM PDT 24
Peak memory 217748 kb
Host smart-7827a9dd-d7c4-4a89-a152-b207db5765f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590540723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2590540723
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1788417983
Short name T549
Test name
Test status
Simulation time 986300605 ps
CPU time 11.52 seconds
Started Apr 23 02:47:33 PM PDT 24
Finished Apr 23 02:47:45 PM PDT 24
Peak memory 217896 kb
Host smart-a39e8bae-5be3-48e8-960b-195fba4f4adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788417983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1788417983
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1008011204
Short name T508
Test name
Test status
Simulation time 886404803 ps
CPU time 6.95 seconds
Started Apr 23 02:47:33 PM PDT 24
Finished Apr 23 02:47:40 PM PDT 24
Peak memory 217956 kb
Host smart-ad24fc86-16f0-4831-9b6d-2800edfb757f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008011204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1008011204
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.569094073
Short name T516
Test name
Test status
Simulation time 1318654317 ps
CPU time 8.15 seconds
Started Apr 23 02:47:31 PM PDT 24
Finished Apr 23 02:47:40 PM PDT 24
Peak memory 217956 kb
Host smart-ee96ffc3-c024-436a-81a1-4006eb21452b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569094073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.569094073
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2595886612
Short name T684
Test name
Test status
Simulation time 237132619 ps
CPU time 7.03 seconds
Started Apr 23 02:47:28 PM PDT 24
Finished Apr 23 02:47:35 PM PDT 24
Peak memory 217992 kb
Host smart-6545a3b5-6155-45cb-bc52-f4ec9734bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595886612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2595886612
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.710573404
Short name T731
Test name
Test status
Simulation time 94486551 ps
CPU time 1.81 seconds
Started Apr 23 02:47:24 PM PDT 24
Finished Apr 23 02:47:26 PM PDT 24
Peak memory 213884 kb
Host smart-66a1a5b5-6cbc-4248-ad85-db655d004649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710573404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.710573404
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1206668480
Short name T528
Test name
Test status
Simulation time 218284103 ps
CPU time 27.38 seconds
Started Apr 23 02:47:31 PM PDT 24
Finished Apr 23 02:47:59 PM PDT 24
Peak memory 250984 kb
Host smart-a185fe2d-b529-4041-a95e-99df5a863677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206668480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1206668480
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3458148661
Short name T649
Test name
Test status
Simulation time 89488972 ps
CPU time 3.08 seconds
Started Apr 23 02:47:29 PM PDT 24
Finished Apr 23 02:47:33 PM PDT 24
Peak memory 222252 kb
Host smart-9acd37d9-9cc9-4146-801a-fb4a20656960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458148661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3458148661
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1621196657
Short name T864
Test name
Test status
Simulation time 7453222665 ps
CPU time 170.26 seconds
Started Apr 23 02:47:34 PM PDT 24
Finished Apr 23 02:50:25 PM PDT 24
Peak memory 272308 kb
Host smart-e34ad7ff-4fbc-4d4a-8b68-7f7d5cc92f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621196657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1621196657
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.879977227
Short name T219
Test name
Test status
Simulation time 13115996 ps
CPU time 0.97 seconds
Started Apr 23 02:47:29 PM PDT 24
Finished Apr 23 02:47:31 PM PDT 24
Peak memory 211684 kb
Host smart-6ff58e65-36f7-4dc4-97d0-3b00f0af8b96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879977227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.879977227
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3058795798
Short name T517
Test name
Test status
Simulation time 42287159 ps
CPU time 1.03 seconds
Started Apr 23 02:47:37 PM PDT 24
Finished Apr 23 02:47:39 PM PDT 24
Peak memory 209540 kb
Host smart-e6ecf0ee-d6ff-4c30-a6ed-5aacfef8736f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058795798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3058795798
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2693151705
Short name T816
Test name
Test status
Simulation time 11332104 ps
CPU time 0.82 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:47:39 PM PDT 24
Peak memory 209272 kb
Host smart-fa4e5e64-87bd-4f28-a4a2-e7f11f7397cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693151705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2693151705
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2464887365
Short name T482
Test name
Test status
Simulation time 1014168743 ps
CPU time 11.38 seconds
Started Apr 23 02:47:35 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 218068 kb
Host smart-9d0de70e-2195-4957-8e4f-e1d286b26f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464887365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2464887365
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.4252059813
Short name T721
Test name
Test status
Simulation time 38926438 ps
CPU time 1.17 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:47:40 PM PDT 24
Peak memory 216820 kb
Host smart-e67ba007-60e2-4f34-bf05-e0a40e980e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252059813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.4252059813
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2092695971
Short name T739
Test name
Test status
Simulation time 3327691565 ps
CPU time 44.56 seconds
Started Apr 23 02:47:34 PM PDT 24
Finished Apr 23 02:48:19 PM PDT 24
Peak memory 219128 kb
Host smart-23922234-76d1-406b-9ac1-ed44a4f25d58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092695971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2092695971
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1786811521
Short name T328
Test name
Test status
Simulation time 206109436 ps
CPU time 1.81 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:47:40 PM PDT 24
Peak memory 217200 kb
Host smart-b9aa11d8-7ba3-4365-bed2-e17774eb5cce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786811521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
786811521
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.920457040
Short name T216
Test name
Test status
Simulation time 119906258 ps
CPU time 2.3 seconds
Started Apr 23 02:47:34 PM PDT 24
Finished Apr 23 02:47:37 PM PDT 24
Peak memory 217932 kb
Host smart-cfbaf65e-3aa2-48c5-b289-f3dfc2913b1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920457040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.920457040
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.80140776
Short name T808
Test name
Test status
Simulation time 890533548 ps
CPU time 13.43 seconds
Started Apr 23 02:47:40 PM PDT 24
Finished Apr 23 02:47:54 PM PDT 24
Peak memory 213216 kb
Host smart-b633f634-d407-46b3-8f30-e3d7f5552783
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80140776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt
ag_regwen_during_op.80140776
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3980435071
Short name T736
Test name
Test status
Simulation time 1260276451 ps
CPU time 5.34 seconds
Started Apr 23 02:47:37 PM PDT 24
Finished Apr 23 02:47:43 PM PDT 24
Peak memory 213932 kb
Host smart-ab77aad4-8af3-4771-9efb-9b577f9ecc9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980435071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3980435071
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.687434791
Short name T587
Test name
Test status
Simulation time 3389623805 ps
CPU time 24.38 seconds
Started Apr 23 02:47:35 PM PDT 24
Finished Apr 23 02:48:00 PM PDT 24
Peak memory 251096 kb
Host smart-4e751758-469f-45f5-80fe-6e92ce568145
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687434791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.687434791
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3116788765
Short name T544
Test name
Test status
Simulation time 444826179 ps
CPU time 15.99 seconds
Started Apr 23 02:47:35 PM PDT 24
Finished Apr 23 02:47:51 PM PDT 24
Peak memory 250616 kb
Host smart-43261b08-82ca-4e89-8f0b-cae38c9fef94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116788765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3116788765
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1142427795
Short name T348
Test name
Test status
Simulation time 111037887 ps
CPU time 3.22 seconds
Started Apr 23 02:47:36 PM PDT 24
Finished Apr 23 02:47:39 PM PDT 24
Peak memory 218036 kb
Host smart-c5975c38-6ec9-41e5-a06a-5c70a0f7bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142427795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1142427795
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1136714622
Short name T293
Test name
Test status
Simulation time 303156850 ps
CPU time 10.83 seconds
Started Apr 23 02:47:36 PM PDT 24
Finished Apr 23 02:47:47 PM PDT 24
Peak memory 218252 kb
Host smart-96e64e15-05a6-4f64-9bf7-de63ddeb52c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136714622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1136714622
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2915805223
Short name T424
Test name
Test status
Simulation time 960466577 ps
CPU time 10.85 seconds
Started Apr 23 02:47:41 PM PDT 24
Finished Apr 23 02:47:52 PM PDT 24
Peak memory 218188 kb
Host smart-f3490c0f-558b-4fcb-b219-b3d49f2c86db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915805223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2915805223
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.4178120505
Short name T547
Test name
Test status
Simulation time 1786646306 ps
CPU time 11.53 seconds
Started Apr 23 02:47:39 PM PDT 24
Finished Apr 23 02:47:51 PM PDT 24
Peak memory 217912 kb
Host smart-17a81e26-69a8-4a58-9339-5fe57bcf75a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178120505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.4178120505
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.326227404
Short name T50
Test name
Test status
Simulation time 2974552247 ps
CPU time 12.92 seconds
Started Apr 23 02:47:45 PM PDT 24
Finished Apr 23 02:47:58 PM PDT 24
Peak memory 217996 kb
Host smart-58af2588-aea3-42e7-ad7e-7b6e0fbcc021
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326227404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.326227404
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.694396191
Short name T349
Test name
Test status
Simulation time 3854033160 ps
CPU time 11.15 seconds
Started Apr 23 02:47:36 PM PDT 24
Finished Apr 23 02:47:48 PM PDT 24
Peak memory 218124 kb
Host smart-d964401a-c5d3-4d61-93ac-48743a72115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694396191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.694396191
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3562051413
Short name T749
Test name
Test status
Simulation time 446753188 ps
CPU time 4.02 seconds
Started Apr 23 02:47:40 PM PDT 24
Finished Apr 23 02:47:44 PM PDT 24
Peak memory 213924 kb
Host smart-06701ff7-4021-48d5-9bf2-6d9db39e0700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562051413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3562051413
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.4016718195
Short name T421
Test name
Test status
Simulation time 220106821 ps
CPU time 19.38 seconds
Started Apr 23 02:47:40 PM PDT 24
Finished Apr 23 02:47:59 PM PDT 24
Peak memory 251040 kb
Host smart-9fe57aee-4257-41ed-964e-60672cc8dfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016718195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4016718195
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4029983489
Short name T779
Test name
Test status
Simulation time 236547630 ps
CPU time 7.53 seconds
Started Apr 23 02:47:37 PM PDT 24
Finished Apr 23 02:47:45 PM PDT 24
Peak memory 251020 kb
Host smart-39ca69c2-a658-48c8-92c2-918781e8a564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029983489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4029983489
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3572034255
Short name T267
Test name
Test status
Simulation time 1686162650 ps
CPU time 39.98 seconds
Started Apr 23 02:47:38 PM PDT 24
Finished Apr 23 02:48:18 PM PDT 24
Peak memory 259308 kb
Host smart-1b786c6b-90c2-4e62-8538-8dd9e28bad14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572034255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3572034255
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2528374759
Short name T512
Test name
Test status
Simulation time 32789306 ps
CPU time 0.73 seconds
Started Apr 23 02:47:35 PM PDT 24
Finished Apr 23 02:47:36 PM PDT 24
Peak memory 206876 kb
Host smart-a611c840-10f9-4aea-a758-1c4548b76d73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528374759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2528374759
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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