Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55958 |
1 |
|
|
T1 |
68 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
1918 |
1 |
|
|
T1 |
5 |
|
T12 |
12 |
|
T13 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57147 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
729 |
1 |
|
|
T8 |
16 |
|
T11 |
21 |
|
T57 |
9 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55672 |
1 |
|
|
T1 |
73 |
|
T2 |
154 |
|
T4 |
89 |
auto[1] |
2204 |
1 |
|
|
T2 |
25 |
|
T12 |
52 |
|
T23 |
8 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55662 |
1 |
|
|
T1 |
73 |
|
T2 |
157 |
|
T4 |
89 |
auto[1] |
2214 |
1 |
|
|
T2 |
22 |
|
T12 |
39 |
|
T23 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55710 |
1 |
|
|
T1 |
73 |
|
T2 |
168 |
|
T4 |
89 |
auto[1] |
2166 |
1 |
|
|
T2 |
11 |
|
T12 |
41 |
|
T23 |
4 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
52564 |
1 |
|
|
T1 |
73 |
|
T2 |
163 |
|
T4 |
35 |
no_err_inj |
5312 |
1 |
|
|
T2 |
16 |
|
T4 |
54 |
|
T12 |
87 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55989 |
1 |
|
|
T1 |
68 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
1887 |
1 |
|
|
T1 |
5 |
|
T12 |
7 |
|
T13 |
5 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57133 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
743 |
1 |
|
|
T8 |
10 |
|
T11 |
18 |
|
T57 |
7 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39747 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[1] |
18129 |
1 |
|
|
T1 |
73 |
|
T2 |
26 |
|
T4 |
41 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55729 |
1 |
|
|
T1 |
73 |
|
T2 |
164 |
|
T4 |
89 |
auto[1] |
2147 |
1 |
|
|
T2 |
15 |
|
T12 |
40 |
|
T23 |
6 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55707 |
1 |
|
|
T1 |
73 |
|
T2 |
160 |
|
T4 |
89 |
auto[1] |
2169 |
1 |
|
|
T2 |
19 |
|
T12 |
41 |
|
T23 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55719 |
1 |
|
|
T1 |
73 |
|
T2 |
161 |
|
T4 |
89 |
auto[1] |
2157 |
1 |
|
|
T2 |
18 |
|
T12 |
40 |
|
T23 |
7 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55962 |
1 |
|
|
T1 |
64 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
1914 |
1 |
|
|
T1 |
9 |
|
T12 |
8 |
|
T13 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55085 |
1 |
|
|
T1 |
73 |
|
T2 |
164 |
|
T4 |
54 |
auto[1] |
2791 |
1 |
|
|
T2 |
15 |
|
T4 |
35 |
|
T12 |
52 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57134 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
742 |
1 |
|
|
T8 |
17 |
|
T11 |
22 |
|
T57 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57166 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
710 |
1 |
|
|
T8 |
14 |
|
T11 |
24 |
|
T57 |
12 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57176 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
700 |
1 |
|
|
T8 |
15 |
|
T11 |
11 |
|
T57 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54833 |
1 |
|
|
T1 |
73 |
|
T2 |
167 |
|
T4 |
89 |
auto[1] |
3043 |
1 |
|
|
T2 |
12 |
|
T12 |
63 |
|
T14 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54249 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
3627 |
1 |
|
|
T19 |
81 |
|
T20 |
51 |
|
T45 |
100 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55667 |
1 |
|
|
T1 |
73 |
|
T2 |
162 |
|
T4 |
89 |
auto[1] |
2209 |
1 |
|
|
T2 |
17 |
|
T12 |
52 |
|
T23 |
2 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55681 |
1 |
|
|
T1 |
73 |
|
T2 |
168 |
|
T4 |
89 |
auto[1] |
2195 |
1 |
|
|
T2 |
11 |
|
T12 |
44 |
|
T23 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55718 |
1 |
|
|
T1 |
73 |
|
T2 |
169 |
|
T4 |
89 |
auto[1] |
2158 |
1 |
|
|
T2 |
10 |
|
T12 |
44 |
|
T23 |
10 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55900 |
1 |
|
|
T1 |
63 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
1976 |
1 |
|
|
T1 |
10 |
|
T12 |
14 |
|
T13 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52256 |
1 |
|
|
T1 |
61 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
5620 |
1 |
|
|
T1 |
12 |
|
T12 |
7 |
|
T221 |
69 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54141 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
3735 |
1 |
|
|
T18 |
89 |
|
T44 |
84 |
|
T56 |
55 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57876 |
1 |
|
|
T1 |
73 |
|
T2 |
179 |
|
T4 |
89 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55914 |
1 |
|
|
T1 |
61 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
1962 |
1 |
|
|
T1 |
12 |
|
T12 |
13 |
|
T13 |
8 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55907 |
1 |
|
|
T1 |
65 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
1969 |
1 |
|
|
T1 |
8 |
|
T12 |
8 |
|
T13 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55954 |
1 |
|
|
T1 |
61 |
|
T2 |
179 |
|
T4 |
89 |
auto[1] |
1922 |
1 |
|
|
T1 |
12 |
|
T12 |
5 |
|
T13 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
51064 |
1 |
|
|
T1 |
73 |
|
T2 |
157 |
|
T4 |
35 |
auto[0] |
no_err_inj |
3769 |
1 |
|
|
T2 |
10 |
|
T4 |
54 |
|
T12 |
54 |
auto[1] |
err_inj |
1500 |
1 |
|
|
T2 |
6 |
|
T12 |
30 |
|
T14 |
10 |
auto[1] |
no_err_inj |
1543 |
1 |
|
|
T2 |
6 |
|
T12 |
33 |
|
T14 |
2 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52823 |
1 |
|
|
T1 |
73 |
|
T2 |
156 |
|
T4 |
89 |
auto[0] |
auto[1] |
2010 |
1 |
|
|
T2 |
11 |
|
T12 |
40 |
|
T23 |
6 |
auto[1] |
auto[0] |
2858 |
1 |
|
|
T2 |
12 |
|
T12 |
59 |
|
T14 |
10 |
auto[1] |
auto[1] |
185 |
1 |
|
|
T12 |
4 |
|
T14 |
2 |
|
T15 |
4 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52825 |
1 |
|
|
T1 |
73 |
|
T2 |
148 |
|
T4 |
89 |
auto[0] |
auto[1] |
2008 |
1 |
|
|
T2 |
19 |
|
T12 |
37 |
|
T23 |
2 |
auto[1] |
auto[0] |
2882 |
1 |
|
|
T2 |
12 |
|
T12 |
59 |
|
T14 |
10 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T12 |
4 |
|
T14 |
2 |
|
T15 |
5 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52825 |
1 |
|
|
T1 |
73 |
|
T2 |
157 |
|
T4 |
89 |
auto[0] |
auto[1] |
2008 |
1 |
|
|
T2 |
10 |
|
T12 |
39 |
|
T23 |
10 |
auto[1] |
auto[0] |
2893 |
1 |
|
|
T2 |
12 |
|
T12 |
58 |
|
T14 |
11 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T12 |
5 |
|
T14 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52793 |
1 |
|
|
T1 |
73 |
|
T2 |
146 |
|
T4 |
89 |
auto[0] |
auto[1] |
2040 |
1 |
|
|
T2 |
21 |
|
T12 |
38 |
|
T23 |
8 |
auto[1] |
auto[0] |
2869 |
1 |
|
|
T2 |
11 |
|
T12 |
62 |
|
T14 |
12 |
auto[1] |
auto[1] |
174 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52849 |
1 |
|
|
T1 |
73 |
|
T2 |
156 |
|
T4 |
89 |
auto[0] |
auto[1] |
1984 |
1 |
|
|
T2 |
11 |
|
T12 |
36 |
|
T23 |
4 |
auto[1] |
auto[0] |
2861 |
1 |
|
|
T2 |
12 |
|
T12 |
58 |
|
T14 |
11 |
auto[1] |
auto[1] |
182 |
1 |
|
|
T12 |
5 |
|
T14 |
1 |
|
T15 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52815 |
1 |
|
|
T1 |
73 |
|
T2 |
143 |
|
T4 |
89 |
auto[0] |
auto[1] |
2018 |
1 |
|
|
T2 |
24 |
|
T12 |
48 |
|
T23 |
8 |
auto[1] |
auto[0] |
2857 |
1 |
|
|
T2 |
11 |
|
T12 |
59 |
|
T14 |
11 |
auto[1] |
auto[1] |
186 |
1 |
|
|
T2 |
1 |
|
T12 |
4 |
|
T14 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38636 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1111 |
1 |
|
|
T12 |
12 |
|
T13 |
8 |
|
T14 |
7 |
auto[1] |
auto[0] |
17322 |
1 |
|
|
T1 |
68 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
807 |
1 |
|
|
T1 |
5 |
|
T15 |
9 |
|
T16 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38612 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1135 |
1 |
|
|
T12 |
7 |
|
T13 |
5 |
|
T14 |
12 |
auto[1] |
auto[0] |
17377 |
1 |
|
|
T1 |
68 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
752 |
1 |
|
|
T1 |
5 |
|
T15 |
5 |
|
T16 |
14 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38163 |
1 |
|
|
T2 |
152 |
|
T4 |
28 |
|
T8 |
72 |
auto[0] |
auto[1] |
1584 |
1 |
|
|
T2 |
1 |
|
T4 |
20 |
|
T12 |
37 |
auto[1] |
auto[0] |
16922 |
1 |
|
|
T1 |
73 |
|
T2 |
12 |
|
T4 |
26 |
auto[1] |
auto[1] |
1207 |
1 |
|
|
T2 |
14 |
|
T4 |
15 |
|
T12 |
15 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38605 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1142 |
1 |
|
|
T12 |
7 |
|
T13 |
11 |
|
T14 |
9 |
auto[1] |
auto[0] |
17357 |
1 |
|
|
T1 |
64 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
772 |
1 |
|
|
T1 |
9 |
|
T12 |
1 |
|
T15 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34869 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
4878 |
1 |
|
|
T12 |
7 |
|
T221 |
69 |
|
T13 |
6 |
auto[1] |
auto[0] |
17387 |
1 |
|
|
T1 |
61 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
742 |
1 |
|
|
T1 |
12 |
|
T15 |
11 |
|
T16 |
6 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38454 |
1 |
|
|
T2 |
142 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1293 |
1 |
|
|
T2 |
11 |
|
T12 |
26 |
|
T23 |
6 |
auto[1] |
auto[0] |
17227 |
1 |
|
|
T1 |
73 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
902 |
1 |
|
|
T12 |
18 |
|
T26 |
13 |
|
T14 |
29 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38429 |
1 |
|
|
T2 |
139 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T2 |
14 |
|
T12 |
33 |
|
T23 |
2 |
auto[1] |
auto[0] |
17238 |
1 |
|
|
T1 |
73 |
|
T2 |
23 |
|
T4 |
41 |
auto[1] |
auto[1] |
891 |
1 |
|
|
T2 |
3 |
|
T12 |
19 |
|
T26 |
9 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38536 |
1 |
|
|
T2 |
134 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1211 |
1 |
|
|
T2 |
19 |
|
T12 |
25 |
|
T23 |
2 |
auto[1] |
auto[0] |
17171 |
1 |
|
|
T1 |
73 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
958 |
1 |
|
|
T12 |
16 |
|
T26 |
12 |
|
T14 |
30 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38506 |
1 |
|
|
T2 |
138 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1241 |
1 |
|
|
T2 |
15 |
|
T12 |
25 |
|
T23 |
6 |
auto[1] |
auto[0] |
17223 |
1 |
|
|
T1 |
73 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
906 |
1 |
|
|
T12 |
15 |
|
T26 |
9 |
|
T14 |
30 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38490 |
1 |
|
|
T2 |
132 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1257 |
1 |
|
|
T2 |
21 |
|
T12 |
29 |
|
T23 |
8 |
auto[1] |
auto[0] |
17172 |
1 |
|
|
T1 |
73 |
|
T2 |
25 |
|
T4 |
41 |
auto[1] |
auto[1] |
957 |
1 |
|
|
T2 |
1 |
|
T12 |
10 |
|
T26 |
10 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38446 |
1 |
|
|
T2 |
129 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1301 |
1 |
|
|
T2 |
24 |
|
T12 |
38 |
|
T23 |
8 |
auto[1] |
auto[0] |
17226 |
1 |
|
|
T1 |
73 |
|
T2 |
25 |
|
T4 |
41 |
auto[1] |
auto[1] |
903 |
1 |
|
|
T2 |
1 |
|
T12 |
14 |
|
T26 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38598 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1149 |
1 |
|
|
T12 |
5 |
|
T13 |
8 |
|
T14 |
14 |
auto[1] |
auto[0] |
17356 |
1 |
|
|
T1 |
61 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
773 |
1 |
|
|
T1 |
12 |
|
T15 |
3 |
|
T16 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38555 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T12 |
7 |
|
T13 |
10 |
|
T14 |
11 |
auto[1] |
auto[0] |
17352 |
1 |
|
|
T1 |
65 |
|
T2 |
26 |
|
T4 |
41 |
auto[1] |
auto[1] |
777 |
1 |
|
|
T1 |
8 |
|
T12 |
1 |
|
T15 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37982 |
1 |
|
|
T2 |
153 |
|
T4 |
48 |
|
T8 |
72 |
auto[0] |
auto[1] |
1765 |
1 |
|
|
T12 |
39 |
|
T15 |
22 |
|
T16 |
39 |
auto[1] |
auto[0] |
16851 |
1 |
|
|
T1 |
73 |
|
T2 |
14 |
|
T4 |
41 |
auto[1] |
auto[1] |
1278 |
1 |
|
|
T2 |
12 |
|
T12 |
24 |
|
T14 |
12 |