Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115630179

1

T1

125455

T2

210267

T3

982

auto[1]

1515431

1

T2

6621

T4

1872

T8

990

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115640261

1

T1

124960

T2

210163

T3

982

auto[1]

1505349

1

T1

495

T2

6725

T4

1579

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7991548	1			T1	6628		T2	21054		T3	86
auto[IdleSt]	22708772	1			T1	61803		T2	56238		T3	58
auto[ClkMuxSt]	37173	1			T1	73		T2	30		T3	1
auto[CntIncrSt]	36900	1			T1	73		T2	30		T3	1
auto[CntProgSt]	1642958	1			T1	293		T2	697		T3	2
auto[TransCheckSt]	28349	1			T1	60		T2	15		T3	1
auto[TokenHashSt]	49043953	1			T1	994		T2	31657		T3	24
auto[FlashRmaSt]	29771	1			T1	23		T2	42		T4	75
auto[TokenCheck0St]	13308	1			T1	14		T2	15		T4	51
auto[TokenCheck1St]	9971	1			T1	10		T2	15		T4	51
auto[TransProgSt]	439117	1			T1	39		T2	387		T4	2326
auto[PostTransSt]	13737790	1			T1	53550		T2	35598		T3	809
auto[ScrapSt]	303646	1			T2	31		T4	4033		T12	9
auto[EscalateSt]	7715008	1			T1	1895		T2	40472		T4	9480
auto[InvalidSt]	13405124	1			T2	30588		T8	1068		T11	1880

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2222	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13405124	1			T2	30588		T8	1068		T11	1880
EscalateSt	7715008	1			T1	1895		T2	40472		T4	9480
ScrapSt	303646	1			T2	31		T4	4033		T12	9
PostTransSt	13737790	1			T1	53550		T2	35598		T3	809
TransProgSt	439117	1			T1	39		T2	387		T4	2326
TokenCheck1St	9971	1			T1	10		T2	15		T4	51
TokenCheck0St	13308	1			T1	14		T2	15		T4	51
FlashRmaSt	29771	1			T1	23		T2	42		T4	75
TokenHashSt	49043953	1			T1	994		T2	31657		T3	24
TransCheckSt	28349	1			T1	60		T2	15		T3	1
CntProgSt	1642958	1			T1	293		T2	697		T3	2
CntIncrSt	36900	1			T1	73		T2	30		T3	1
ClkMuxSt	37173	1			T1	73		T2	30		T3	1
IdleSt	22708772	1			T1	61803		T2	56238		T3	58
ResetSt	7991548	1			T1	6628		T2	21054		T3	86
arcs[ResetSt=>IdleSt]	57904	1			T1	74		T2	167		T3	1
arcs[IdleSt=>ScrapSt]	297	1			T2	1		T4	3		T12	1
arcs[IdleSt=>ClkMuxSt]	36983	1			T1	73		T2	30		T3	1
arcs[ClkMuxSt=>CntIncrSt]	36900	1			T1	73		T2	30		T3	1
arcs[CntIncrSt=>PostTransSt]	1972	1			T1	8		T12	8		T13	10
arcs[CntIncrSt=>CntProgSt]	34871	1			T1	65		T2	30		T3	1
arcs[CntProgSt=>PostTransSt]	5406	1			T1	5		T2	15		T4	35
arcs[CntProgSt=>TransCheckSt]	28349	1			T1	60		T2	15		T3	1
arcs[TransCheckSt=>PostTransSt]	3754	1			T1	12		T12	5		T18	42
arcs[TransCheckSt=>TokenHashSt]	24531	1			T1	48		T2	15		T3	1
arcs[TokenHashSt=>PostTransSt]	10502	1			T1	34		T3	1		T8	7
arcs[TokenHashSt=>FlashRmaSt]	13394	1			T1	14		T2	15		T4	51
arcs[FlashRmaSt=>TokenCheck0St]	13308	1			T1	14		T2	15		T4	51
arcs[TokenCheck0St=>PostTransSt]	3304	1			T1	4		T8	9		T11	12
arcs[TokenCheck0St=>TokenCheck1St]	9971	1			T1	10		T2	15		T4	51
arcs[TokenCheck1St=>PostTransSt]	673	1			T1	1		T8	1		T11	3
arcs[TransProgSt=>PostTransSt]	8370	1			T1	9		T2	15		T4	51
arcs[IdleSt=>EscalateSt]	187	1			T46	6		T48	7		T47	8
arcs[ClkMuxSt=>EscalateSt]	83	1			T19	2		T20	1		T45	3
arcs[CntIncrSt=>EscalateSt]	57	1			T20	1		T46	1		T47	2
arcs[CntProgSt=>EscalateSt]	1116	1			T19	31		T20	29		T45	54
arcs[TransCheckSt=>EscalateSt]	64	1			T49	1		T46	7		T52	1
arcs[TokenHashSt=>EscalateSt]	635	1			T19	16		T20	4		T45	7
arcs[FlashRmaSt=>EscalateSt]	86	1			T19	1		T20	1		T45	1
arcs[TokenCheck0St=>EscalateSt]	33	1			T19	2		T48	1		T47	3
arcs[TokenCheck1St=>EscalateSt]	132	1			T19	1		T20	1		T45	1
arcs[TransProgSt=>EscalateSt]	796	1			T19	23		T20	12		T45	24
arcs[PostTransSt=>EscalateSt]	5590	1			T1	5		T2	15		T4	35
arcs[InvalidSt=>EscalateSt]	16034	1			T2	120		T8	14		T11	24

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7991378	1			T1	6628		T2	21054		T3	86
auto[0]	auto[IdleSt]	22708640	1			T1	61803		T2	56238		T3	58
auto[0]	auto[ClkMuxSt]	37120	1			T1	73		T2	30		T3	1
auto[0]	auto[CntIncrSt]	36864	1			T1	73		T2	30		T3	1
auto[0]	auto[CntProgSt]	1642203	1			T1	293		T2	697		T3	2
auto[0]	auto[TransCheckSt]	28308	1			T1	60		T2	15		T3	1
auto[0]	auto[TokenHashSt]	49043527	1			T1	994		T2	31657		T3	24
auto[0]	auto[FlashRmaSt]	29707	1			T1	23		T2	42		T4	75
auto[0]	auto[TokenCheck0St]	13283	1			T1	14		T2	15		T4	51
auto[0]	auto[TokenCheck1St]	9888	1			T1	10		T2	15		T4	51
auto[0]	auto[TransProgSt]	438587	1			T1	39		T2	387		T4	2326
auto[0]	auto[PostTransSt]	13734953	1			T1	53550		T2	35589		T3	809
auto[0]	auto[ScrapSt]	303611	1			T2	31		T4	4033		T12	9
auto[0]	auto[EscalateSt]	6212773	1			T1	1895		T2	33918		T4	7627
auto[0]	auto[InvalidSt]	13397115	1			T2	30530		T8	1062		T11	1865
auto[1]	auto[ResetSt]	170	1			T19	4		T20	2		T45	4
auto[1]	auto[IdleSt]	132	1			T46	5		T48	4		T47	6
auto[1]	auto[ClkMuxSt]	53	1			T19	1		T20	1		T45	1
auto[1]	auto[CntIncrSt]	36	1			T46	1		T47	2		T52	1
auto[1]	auto[CntProgSt]	755	1			T19	23		T20	22		T45	36
auto[1]	auto[TransCheckSt]	41	1			T49	1		T46	4		T107	3
auto[1]	auto[TokenHashSt]	426	1			T19	8		T20	3		T45	3
auto[1]	auto[FlashRmaSt]	64	1			T19	1		T20	1		T45	1
auto[1]	auto[TokenCheck0St]	25	1			T19	2		T48	1		T47	3
auto[1]	auto[TokenCheck1St]	83	1			T19	1		T20	1		T45	1
auto[1]	auto[TransProgSt]	530	1			T19	15		T20	6		T45	15
auto[1]	auto[PostTransSt]	2837	1			T2	9		T4	19		T8	4
auto[1]	auto[ScrapSt]	35	1			T19	1		T49	1		T46	2
auto[1]	auto[EscalateSt]	1502235	1			T2	6554		T4	1853		T8	980
auto[1]	auto[InvalidSt]	8009	1			T2	58		T8	6		T11	15

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7991392	1			T1	6628		T2	21054		T3	86
auto[0]	auto[IdleSt]	22708652	1			T1	61803		T2	56238		T3	58
auto[0]	auto[ClkMuxSt]	37116	1			T1	73		T2	30		T3	1
auto[0]	auto[CntIncrSt]	36863	1			T1	73		T2	30		T3	1
auto[0]	auto[CntProgSt]	1642198	1			T1	293		T2	697		T3	2
auto[0]	auto[TransCheckSt]	28305	1			T1	60		T2	15		T3	1
auto[0]	auto[TokenHashSt]	49043538	1			T1	994		T2	31657		T3	24
auto[0]	auto[FlashRmaSt]	29722	1			T1	23		T2	42		T4	75
auto[0]	auto[TokenCheck0St]	13291	1			T1	14		T2	15		T4	51
auto[0]	auto[TokenCheck1St]	9876	1			T1	10		T2	15		T4	51
auto[0]	auto[TransProgSt]	438594	1			T1	39		T2	387		T4	2326
auto[0]	auto[PostTransSt]	13734988	1			T1	53545		T2	35592		T3	809
auto[0]	auto[ScrapSt]	303618	1			T2	31		T4	4033		T12	9
auto[0]	auto[EscalateSt]	6222787	1			T1	1405		T2	33815		T4	7917
auto[0]	auto[InvalidSt]	13397099	1			T2	30526		T8	1060		T11	1871
auto[1]	auto[ResetSt]	156	1			T19	3		T20	2		T45	2
auto[1]	auto[IdleSt]	120	1			T46	4		T48	5		T47	5
auto[1]	auto[ClkMuxSt]	57	1			T19	2		T45	2		T49	1
auto[1]	auto[CntIncrSt]	37	1			T20	1		T46	1		T47	2
auto[1]	auto[CntProgSt]	760	1			T19	20		T20	21		T45	35
auto[1]	auto[TransCheckSt]	44	1			T46	5		T52	1		T107	4
auto[1]	auto[TokenHashSt]	415	1			T19	11		T20	3		T45	5
auto[1]	auto[FlashRmaSt]	49	1			T45	1		T49	1		T46	2
auto[1]	auto[TokenCheck0St]	17	1			T19	1		T47	2		T107	1
auto[1]	auto[TokenCheck1St]	95	1			T19	1		T20	1		T49	3
auto[1]	auto[TransProgSt]	523	1			T19	14		T20	7		T45	13
auto[1]	auto[PostTransSt]	2802	1			T1	5		T2	6		T4	16
auto[1]	auto[ScrapSt]	28	1			T19	1		T45	1		T48	1
auto[1]	auto[EscalateSt]	1492221	1			T1	490		T2	6657		T4	1563
auto[1]	auto[InvalidSt]	8025	1			T2	62		T8	8		T11	9