| T818 |
/workspace/coverage/default/23.lc_ctrl_jtag_access.260987348 |
|
|
Apr 25 12:56:04 PM PDT 24 |
Apr 25 12:56:09 PM PDT 24 |
651828710 ps |
| T819 |
/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3624364518 |
|
|
Apr 25 12:55:14 PM PDT 24 |
Apr 25 12:55:35 PM PDT 24 |
13798059671 ps |
| T820 |
/workspace/coverage/default/33.lc_ctrl_errors.399968359 |
|
|
Apr 25 12:56:43 PM PDT 24 |
Apr 25 12:56:56 PM PDT 24 |
347390940 ps |
| T821 |
/workspace/coverage/default/40.lc_ctrl_state_failure.4187939903 |
|
|
Apr 25 12:56:43 PM PDT 24 |
Apr 25 12:57:08 PM PDT 24 |
179670097 ps |
| T822 |
/workspace/coverage/default/21.lc_ctrl_jtag_access.568425678 |
|
|
Apr 25 12:56:00 PM PDT 24 |
Apr 25 12:56:05 PM PDT 24 |
839452246 ps |
| T823 |
/workspace/coverage/default/18.lc_ctrl_sec_token_digest.310990368 |
|
|
Apr 25 12:56:04 PM PDT 24 |
Apr 25 12:56:27 PM PDT 24 |
1227609787 ps |
| T824 |
/workspace/coverage/default/8.lc_ctrl_sec_token_mux.2897670315 |
|
|
Apr 25 12:55:36 PM PDT 24 |
Apr 25 12:55:51 PM PDT 24 |
1398871999 ps |
| T825 |
/workspace/coverage/default/13.lc_ctrl_state_failure.3819008916 |
|
|
Apr 25 12:55:37 PM PDT 24 |
Apr 25 12:56:02 PM PDT 24 |
944844303 ps |
| T826 |
/workspace/coverage/default/46.lc_ctrl_sec_token_digest.3771636904 |
|
|
Apr 25 12:57:02 PM PDT 24 |
Apr 25 12:57:20 PM PDT 24 |
565263636 ps |
| T827 |
/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.669549649 |
|
|
Apr 25 12:55:03 PM PDT 24 |
Apr 25 12:55:07 PM PDT 24 |
22860896 ps |
| T828 |
/workspace/coverage/default/9.lc_ctrl_sec_token_mux.2566673557 |
|
|
Apr 25 12:55:48 PM PDT 24 |
Apr 25 12:55:59 PM PDT 24 |
2283144954 ps |
| T829 |
/workspace/coverage/default/16.lc_ctrl_jtag_errors.3894394980 |
|
|
Apr 25 12:56:09 PM PDT 24 |
Apr 25 12:57:10 PM PDT 24 |
7268923372 ps |
| T830 |
/workspace/coverage/default/20.lc_ctrl_prog_failure.2367698291 |
|
|
Apr 25 12:56:12 PM PDT 24 |
Apr 25 12:56:22 PM PDT 24 |
299506343 ps |
| T43 |
/workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3138530567 |
|
|
Apr 25 12:55:36 PM PDT 24 |
Apr 25 12:58:30 PM PDT 24 |
15425816025 ps |
| T831 |
/workspace/coverage/default/43.lc_ctrl_jtag_access.2923926374 |
|
|
Apr 25 12:56:47 PM PDT 24 |
Apr 25 12:56:51 PM PDT 24 |
405478603 ps |
| T832 |
/workspace/coverage/default/41.lc_ctrl_state_failure.4115843244 |
|
|
Apr 25 12:56:46 PM PDT 24 |
Apr 25 12:57:09 PM PDT 24 |
190189055 ps |
| T833 |
/workspace/coverage/default/6.lc_ctrl_stress_all.763414475 |
|
|
Apr 25 12:55:20 PM PDT 24 |
Apr 25 12:57:08 PM PDT 24 |
6486532489 ps |
| T834 |
/workspace/coverage/default/9.lc_ctrl_sec_token_digest.2070422773 |
|
|
Apr 25 12:55:42 PM PDT 24 |
Apr 25 12:56:02 PM PDT 24 |
1680482607 ps |
| T835 |
/workspace/coverage/default/8.lc_ctrl_claim_transition_if.2367932646 |
|
|
Apr 25 12:55:29 PM PDT 24 |
Apr 25 12:55:31 PM PDT 24 |
50587165 ps |
| T836 |
/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4272782301 |
|
|
Apr 25 12:55:10 PM PDT 24 |
Apr 25 12:55:12 PM PDT 24 |
15277782 ps |
| T837 |
/workspace/coverage/default/43.lc_ctrl_security_escalation.93733888 |
|
|
Apr 25 12:56:43 PM PDT 24 |
Apr 25 12:56:55 PM PDT 24 |
401255876 ps |
| T838 |
/workspace/coverage/default/49.lc_ctrl_state_post_trans.3069049783 |
|
|
Apr 25 12:56:49 PM PDT 24 |
Apr 25 12:56:54 PM PDT 24 |
230868509 ps |
| T839 |
/workspace/coverage/default/29.lc_ctrl_stress_all.868510080 |
|
|
Apr 25 12:56:11 PM PDT 24 |
Apr 25 12:58:42 PM PDT 24 |
30511855594 ps |
| T840 |
/workspace/coverage/default/40.lc_ctrl_errors.1192779410 |
|
|
Apr 25 12:56:46 PM PDT 24 |
Apr 25 12:56:58 PM PDT 24 |
4236345553 ps |
| T841 |
/workspace/coverage/default/14.lc_ctrl_alert_test.1617222149 |
|
|
Apr 25 12:55:31 PM PDT 24 |
Apr 25 12:55:33 PM PDT 24 |
66529140 ps |
| T842 |
/workspace/coverage/default/1.lc_ctrl_jtag_access.1376951578 |
|
|
Apr 25 12:55:14 PM PDT 24 |
Apr 25 12:55:19 PM PDT 24 |
179642512 ps |
| T843 |
/workspace/coverage/default/32.lc_ctrl_errors.913963653 |
|
|
Apr 25 12:56:11 PM PDT 24 |
Apr 25 12:56:29 PM PDT 24 |
683126456 ps |
| T88 |
/workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2770146088 |
|
|
Apr 25 12:56:07 PM PDT 24 |
Apr 25 01:04:07 PM PDT 24 |
36314193860 ps |
| T89 |
/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2883935328 |
|
|
Apr 25 12:55:12 PM PDT 24 |
Apr 25 12:55:32 PM PDT 24 |
1611828282 ps |
| T90 |
/workspace/coverage/default/26.lc_ctrl_jtag_access.2087545521 |
|
|
Apr 25 12:56:08 PM PDT 24 |
Apr 25 12:56:16 PM PDT 24 |
72359562 ps |
| T91 |
/workspace/coverage/default/46.lc_ctrl_smoke.2485976031 |
|
|
Apr 25 12:56:55 PM PDT 24 |
Apr 25 12:57:01 PM PDT 24 |
347120980 ps |
| T92 |
/workspace/coverage/default/15.lc_ctrl_smoke.310359976 |
|
|
Apr 25 12:55:59 PM PDT 24 |
Apr 25 12:56:03 PM PDT 24 |
276935495 ps |
| T93 |
/workspace/coverage/default/0.lc_ctrl_prog_failure.2857483165 |
|
|
Apr 25 12:55:00 PM PDT 24 |
Apr 25 12:55:04 PM PDT 24 |
85606493 ps |
| T94 |
/workspace/coverage/default/1.lc_ctrl_claim_transition_if.3254806591 |
|
|
Apr 25 12:55:07 PM PDT 24 |
Apr 25 12:55:10 PM PDT 24 |
16607537 ps |
| T95 |
/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2294830401 |
|
|
Apr 25 12:55:43 PM PDT 24 |
Apr 25 12:56:01 PM PDT 24 |
510835685 ps |
| T96 |
/workspace/coverage/default/32.lc_ctrl_state_failure.2460560191 |
|
|
Apr 25 12:56:31 PM PDT 24 |
Apr 25 12:57:06 PM PDT 24 |
1445287390 ps |
| T97 |
/workspace/coverage/default/6.lc_ctrl_claim_transition_if.2474133753 |
|
|
Apr 25 12:55:20 PM PDT 24 |
Apr 25 12:55:24 PM PDT 24 |
11860874 ps |
| T844 |
/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3537304739 |
|
|
Apr 25 12:55:44 PM PDT 24 |
Apr 25 12:56:04 PM PDT 24 |
385931315 ps |
| T845 |
/workspace/coverage/default/18.lc_ctrl_smoke.3475698151 |
|
|
Apr 25 12:56:11 PM PDT 24 |
Apr 25 12:56:18 PM PDT 24 |
78100298 ps |
| T846 |
/workspace/coverage/default/30.lc_ctrl_sec_token_mux.1465941665 |
|
|
Apr 25 12:56:13 PM PDT 24 |
Apr 25 12:56:25 PM PDT 24 |
317384259 ps |
| T847 |
/workspace/coverage/default/46.lc_ctrl_stress_all.427665034 |
|
|
Apr 25 12:57:00 PM PDT 24 |
Apr 25 12:59:23 PM PDT 24 |
27440828151 ps |
| T848 |
/workspace/coverage/default/25.lc_ctrl_smoke.2812262650 |
|
|
Apr 25 12:55:51 PM PDT 24 |
Apr 25 12:55:56 PM PDT 24 |
64141991 ps |
| T849 |
/workspace/coverage/default/17.lc_ctrl_security_escalation.3601799325 |
|
|
Apr 25 12:55:54 PM PDT 24 |
Apr 25 12:56:09 PM PDT 24 |
2412961226 ps |
| T850 |
/workspace/coverage/default/21.lc_ctrl_errors.105674254 |
|
|
Apr 25 12:55:52 PM PDT 24 |
Apr 25 12:56:03 PM PDT 24 |
892344219 ps |
| T851 |
/workspace/coverage/default/9.lc_ctrl_security_escalation.967678426 |
|
|
Apr 25 12:55:38 PM PDT 24 |
Apr 25 12:55:50 PM PDT 24 |
1096887703 ps |
| T852 |
/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2849468221 |
|
|
Apr 25 12:55:00 PM PDT 24 |
Apr 25 12:55:21 PM PDT 24 |
7437285693 ps |
| T853 |
/workspace/coverage/default/39.lc_ctrl_sec_token_digest.339172234 |
|
|
Apr 25 12:56:38 PM PDT 24 |
Apr 25 12:56:50 PM PDT 24 |
1596814868 ps |
| T854 |
/workspace/coverage/default/29.lc_ctrl_errors.665102782 |
|
|
Apr 25 12:56:07 PM PDT 24 |
Apr 25 12:56:27 PM PDT 24 |
422151961 ps |
| T855 |
/workspace/coverage/default/4.lc_ctrl_state_failure.1029411505 |
|
|
Apr 25 12:55:04 PM PDT 24 |
Apr 25 12:55:42 PM PDT 24 |
1103037582 ps |
| T856 |
/workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4223378722 |
|
|
Apr 25 12:54:54 PM PDT 24 |
Apr 25 01:01:23 PM PDT 24 |
101488491775 ps |
| T857 |
/workspace/coverage/default/8.lc_ctrl_state_failure.4267071724 |
|
|
Apr 25 12:55:33 PM PDT 24 |
Apr 25 12:56:07 PM PDT 24 |
1142923045 ps |
| T858 |
/workspace/coverage/default/31.lc_ctrl_sec_token_digest.3746683333 |
|
|
Apr 25 12:56:24 PM PDT 24 |
Apr 25 12:56:36 PM PDT 24 |
6524545494 ps |
| T859 |
/workspace/coverage/default/41.lc_ctrl_sec_mubi.4231612449 |
|
|
Apr 25 12:56:49 PM PDT 24 |
Apr 25 12:57:10 PM PDT 24 |
2939756752 ps |
| T860 |
/workspace/coverage/default/19.lc_ctrl_state_post_trans.1011657890 |
|
|
Apr 25 12:56:01 PM PDT 24 |
Apr 25 12:56:10 PM PDT 24 |
157497224 ps |
| T861 |
/workspace/coverage/default/44.lc_ctrl_jtag_access.3559240716 |
|
|
Apr 25 12:56:56 PM PDT 24 |
Apr 25 12:57:07 PM PDT 24 |
1853114160 ps |
| T862 |
/workspace/coverage/default/26.lc_ctrl_security_escalation.3038665753 |
|
|
Apr 25 12:56:07 PM PDT 24 |
Apr 25 12:56:20 PM PDT 24 |
277592509 ps |
| T863 |
/workspace/coverage/default/32.lc_ctrl_sec_mubi.260042716 |
|
|
Apr 25 12:56:11 PM PDT 24 |
Apr 25 12:56:29 PM PDT 24 |
4989130568 ps |
| T864 |
/workspace/coverage/default/13.lc_ctrl_prog_failure.2088356791 |
|
|
Apr 25 12:55:36 PM PDT 24 |
Apr 25 12:55:41 PM PDT 24 |
211026288 ps |
| T865 |
/workspace/coverage/default/23.lc_ctrl_prog_failure.3679433982 |
|
|
Apr 25 12:56:19 PM PDT 24 |
Apr 25 12:56:23 PM PDT 24 |
196911849 ps |
| T866 |
/workspace/coverage/default/5.lc_ctrl_jtag_priority.2694849653 |
|
|
Apr 25 12:55:10 PM PDT 24 |
Apr 25 12:55:21 PM PDT 24 |
403392377 ps |
| T98 |
/workspace/coverage/default/1.lc_ctrl_sec_cm.3587509347 |
|
|
Apr 25 12:55:03 PM PDT 24 |
Apr 25 12:55:29 PM PDT 24 |
465532746 ps |
| T867 |
/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2434469812 |
|
|
Apr 25 12:55:27 PM PDT 24 |
Apr 25 12:56:19 PM PDT 24 |
5627538241 ps |
| T868 |
/workspace/coverage/default/34.lc_ctrl_prog_failure.3939200887 |
|
|
Apr 25 12:56:26 PM PDT 24 |
Apr 25 12:56:31 PM PDT 24 |
473022468 ps |
| T869 |
/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.992809183 |
|
|
Apr 25 12:55:35 PM PDT 24 |
Apr 25 12:55:51 PM PDT 24 |
3449562373 ps |
| T870 |
/workspace/coverage/default/47.lc_ctrl_smoke.269820536 |
|
|
Apr 25 12:56:56 PM PDT 24 |
Apr 25 12:57:01 PM PDT 24 |
36362385 ps |
| T871 |
/workspace/coverage/default/3.lc_ctrl_state_post_trans.100248913 |
|
|
Apr 25 12:55:14 PM PDT 24 |
Apr 25 12:55:22 PM PDT 24 |
69997362 ps |
| T872 |
/workspace/coverage/default/3.lc_ctrl_smoke.1210788851 |
|
|
Apr 25 12:55:23 PM PDT 24 |
Apr 25 12:55:27 PM PDT 24 |
38789277 ps |
| T873 |
/workspace/coverage/default/29.lc_ctrl_jtag_access.206428828 |
|
|
Apr 25 12:56:11 PM PDT 24 |
Apr 25 12:56:21 PM PDT 24 |
134073625 ps |
| T119 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4104954957 |
|
|
Apr 25 12:35:24 PM PDT 24 |
Apr 25 12:35:27 PM PDT 24 |
135428858 ps |
| T114 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4262234968 |
|
|
Apr 25 12:35:29 PM PDT 24 |
Apr 25 12:35:34 PM PDT 24 |
35598002 ps |
| T115 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3750081810 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
145984778 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2152009862 |
|
|
Apr 25 12:35:30 PM PDT 24 |
Apr 25 12:35:35 PM PDT 24 |
98682239 ps |
| T141 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4110943380 |
|
|
Apr 25 12:35:05 PM PDT 24 |
Apr 25 12:35:09 PM PDT 24 |
154173909 ps |
| T111 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1896266803 |
|
|
Apr 25 12:35:30 PM PDT 24 |
Apr 25 12:35:35 PM PDT 24 |
223958299 ps |
| T206 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4126405197 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
42172905 ps |
| T120 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3771255574 |
|
|
Apr 25 12:35:39 PM PDT 24 |
Apr 25 12:35:44 PM PDT 24 |
49530675 ps |
| T874 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.846834120 |
|
|
Apr 25 12:35:29 PM PDT 24 |
Apr 25 12:35:33 PM PDT 24 |
39810525 ps |
| T112 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.395013713 |
|
|
Apr 25 12:35:33 PM PDT 24 |
Apr 25 12:35:38 PM PDT 24 |
171608670 ps |
| T116 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3323680798 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
467440602 ps |
| T142 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.676464479 |
|
|
Apr 25 12:35:09 PM PDT 24 |
Apr 25 12:35:14 PM PDT 24 |
159024901 ps |
| T875 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.871507908 |
|
|
Apr 25 12:34:59 PM PDT 24 |
Apr 25 12:35:01 PM PDT 24 |
23752953 ps |
| T207 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3913075932 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
232259996 ps |
| T138 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.984775560 |
|
|
Apr 25 12:35:06 PM PDT 24 |
Apr 25 12:35:10 PM PDT 24 |
827367235 ps |
| T139 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3840318748 |
|
|
Apr 25 12:35:43 PM PDT 24 |
Apr 25 12:35:47 PM PDT 24 |
158780457 ps |
| T150 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.760563357 |
|
|
Apr 25 12:35:28 PM PDT 24 |
Apr 25 12:35:32 PM PDT 24 |
16468701 ps |
| T117 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.677294592 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
467042441 ps |
| T130 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2234043570 |
|
|
Apr 25 12:35:35 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
747457280 ps |
| T876 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.473172152 |
|
|
Apr 25 12:35:17 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
138086503 ps |
| T877 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2642621506 |
|
|
Apr 25 12:35:16 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
56431896 ps |
| T161 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2730009484 |
|
|
Apr 25 12:35:25 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
22097890 ps |
| T208 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2559618553 |
|
|
Apr 25 12:35:38 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
91089045 ps |
| T118 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1427024531 |
|
|
Apr 25 12:35:35 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
113540658 ps |
| T209 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3912319864 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:18 PM PDT 24 |
43608775 ps |
| T136 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1265439149 |
|
|
Apr 25 12:35:41 PM PDT 24 |
Apr 25 12:35:47 PM PDT 24 |
540375301 ps |
| T220 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.443168842 |
|
|
Apr 25 12:35:06 PM PDT 24 |
Apr 25 12:35:10 PM PDT 24 |
177311694 ps |
| T878 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3233703879 |
|
|
Apr 25 12:35:31 PM PDT 24 |
Apr 25 12:35:35 PM PDT 24 |
61472624 ps |
| T879 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2050039939 |
|
|
Apr 25 12:35:11 PM PDT 24 |
Apr 25 12:35:16 PM PDT 24 |
51684592 ps |
| T210 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2827298528 |
|
|
Apr 25 12:35:37 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
178369904 ps |
| T122 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.260595432 |
|
|
Apr 25 12:35:31 PM PDT 24 |
Apr 25 12:35:35 PM PDT 24 |
289551646 ps |
| T121 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3301762451 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
235392712 ps |
| T140 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1961662052 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
4644027099 ps |
| T880 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2745300008 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:18 PM PDT 24 |
45206628 ps |
| T211 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1803211985 |
|
|
Apr 25 12:35:25 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
99703951 ps |
| T881 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2356698346 |
|
|
Apr 25 12:35:08 PM PDT 24 |
Apr 25 12:35:13 PM PDT 24 |
327136117 ps |
| T212 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1201793579 |
|
|
Apr 25 12:35:34 PM PDT 24 |
Apr 25 12:35:38 PM PDT 24 |
23711023 ps |
| T213 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3874582067 |
|
|
Apr 25 12:35:15 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
95612505 ps |
| T882 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.700886818 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
826285959 ps |
| T195 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3876922793 |
|
|
Apr 25 12:35:24 PM PDT 24 |
Apr 25 12:35:26 PM PDT 24 |
23394647 ps |
| T214 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2201244085 |
|
|
Apr 25 12:35:12 PM PDT 24 |
Apr 25 12:35:17 PM PDT 24 |
94997633 ps |
| T883 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2096569833 |
|
|
Apr 25 12:35:26 PM PDT 24 |
Apr 25 12:35:31 PM PDT 24 |
929241771 ps |
| T884 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2071910997 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
37197029 ps |
| T885 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3745488282 |
|
|
Apr 25 12:35:42 PM PDT 24 |
Apr 25 12:35:46 PM PDT 24 |
28039641 ps |
| T886 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2330155372 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
2171619869 ps |
| T887 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2560689689 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
199461050 ps |
| T888 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3542592876 |
|
|
Apr 25 12:35:37 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
275776253 ps |
| T889 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3109804263 |
|
|
Apr 25 12:35:17 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
172353636 ps |
| T135 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3809428153 |
|
|
Apr 25 12:35:07 PM PDT 24 |
Apr 25 12:35:23 PM PDT 24 |
230967745 ps |
| T890 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.890991723 |
|
|
Apr 25 12:35:20 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
163319414 ps |
| T891 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1677111937 |
|
|
Apr 25 12:35:30 PM PDT 24 |
Apr 25 12:35:39 PM PDT 24 |
22235801 ps |
| T132 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.813387635 |
|
|
Apr 25 12:35:11 PM PDT 24 |
Apr 25 12:35:17 PM PDT 24 |
81575447 ps |
| T892 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2051445731 |
|
|
Apr 25 12:35:27 PM PDT 24 |
Apr 25 12:35:30 PM PDT 24 |
53784464 ps |
| T893 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2579992801 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
124002652 ps |
| T196 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2655583278 |
|
|
Apr 25 12:35:42 PM PDT 24 |
Apr 25 12:35:45 PM PDT 24 |
38687099 ps |
| T894 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1663574719 |
|
|
Apr 25 12:35:21 PM PDT 24 |
Apr 25 12:35:25 PM PDT 24 |
167880523 ps |
| T125 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2551375463 |
|
|
Apr 25 12:35:15 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
242496069 ps |
| T895 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3209153413 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
173521268 ps |
| T896 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.918071597 |
|
|
Apr 25 12:35:11 PM PDT 24 |
Apr 25 12:35:17 PM PDT 24 |
122118910 ps |
| T897 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1840039811 |
|
|
Apr 25 12:35:30 PM PDT 24 |
Apr 25 12:35:34 PM PDT 24 |
41318286 ps |
| T197 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2983422036 |
|
|
Apr 25 12:35:35 PM PDT 24 |
Apr 25 12:35:39 PM PDT 24 |
29665055 ps |
| T198 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2330123948 |
|
|
Apr 25 12:35:21 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
13501580 ps |
| T898 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.676193627 |
|
|
Apr 25 12:35:16 PM PDT 24 |
Apr 25 12:35:38 PM PDT 24 |
781368610 ps |
| T899 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3921974653 |
|
|
Apr 25 12:35:25 PM PDT 24 |
Apr 25 12:35:34 PM PDT 24 |
80242642 ps |
| T900 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2004662507 |
|
|
Apr 25 12:35:37 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
63787617 ps |
| T901 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2751804060 |
|
|
Apr 25 12:35:09 PM PDT 24 |
Apr 25 12:35:13 PM PDT 24 |
38726292 ps |
| T902 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.427207135 |
|
|
Apr 25 12:34:59 PM PDT 24 |
Apr 25 12:35:03 PM PDT 24 |
217604880 ps |
| T199 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1636453837 |
|
|
Apr 25 12:35:10 PM PDT 24 |
Apr 25 12:35:16 PM PDT 24 |
65488132 ps |
| T134 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4185373625 |
|
|
Apr 25 12:35:42 PM PDT 24 |
Apr 25 12:35:47 PM PDT 24 |
394664104 ps |
| T903 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3358576913 |
|
|
Apr 25 12:35:11 PM PDT 24 |
Apr 25 12:35:16 PM PDT 24 |
106146921 ps |
| T904 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3477878918 |
|
|
Apr 25 12:35:32 PM PDT 24 |
Apr 25 12:35:35 PM PDT 24 |
11390265 ps |
| T905 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3753495036 |
|
|
Apr 25 12:35:08 PM PDT 24 |
Apr 25 12:35:12 PM PDT 24 |
867765491 ps |
| T906 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2344541467 |
|
|
Apr 25 12:35:17 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
53238491 ps |
| T907 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3854835546 |
|
|
Apr 25 12:35:21 PM PDT 24 |
Apr 25 12:35:26 PM PDT 24 |
144454763 ps |
| T127 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.991265687 |
|
|
Apr 25 12:35:30 PM PDT 24 |
Apr 25 12:35:38 PM PDT 24 |
130187687 ps |
| T133 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.17706127 |
|
|
Apr 25 12:35:28 PM PDT 24 |
Apr 25 12:35:32 PM PDT 24 |
119515704 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.440350304 |
|
|
Apr 25 12:35:21 PM PDT 24 |
Apr 25 12:35:26 PM PDT 24 |
2087992597 ps |
| T908 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.625375853 |
|
|
Apr 25 12:35:08 PM PDT 24 |
Apr 25 12:35:11 PM PDT 24 |
92126126 ps |
| T909 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.4074576293 |
|
|
Apr 25 12:35:16 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
361660129 ps |
| T910 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3819105125 |
|
|
Apr 25 12:35:26 PM PDT 24 |
Apr 25 12:35:29 PM PDT 24 |
30564966 ps |
| T911 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3576034287 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
119888859 ps |
| T912 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3601000905 |
|
|
Apr 25 12:35:11 PM PDT 24 |
Apr 25 12:35:16 PM PDT 24 |
16309591 ps |
| T913 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2411320009 |
|
|
Apr 25 12:35:17 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
17884710 ps |
| T914 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1069582999 |
|
|
Apr 25 12:35:01 PM PDT 24 |
Apr 25 12:35:04 PM PDT 24 |
218959537 ps |
| T915 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2451729077 |
|
|
Apr 25 12:35:33 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
347665814 ps |
| T916 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1846234814 |
|
|
Apr 25 12:35:22 PM PDT 24 |
Apr 25 12:35:25 PM PDT 24 |
161821651 ps |
| T917 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.447426643 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
50061554 ps |
| T918 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1929596733 |
|
|
Apr 25 12:35:19 PM PDT 24 |
Apr 25 12:35:31 PM PDT 24 |
345538690 ps |
| T919 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2678274008 |
|
|
Apr 25 12:35:31 PM PDT 24 |
Apr 25 12:36:01 PM PDT 24 |
2425668047 ps |
| T200 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1367472918 |
|
|
Apr 25 12:35:07 PM PDT 24 |
Apr 25 12:35:09 PM PDT 24 |
13418139 ps |
| T920 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3963348681 |
|
|
Apr 25 12:35:16 PM PDT 24 |
Apr 25 12:35:25 PM PDT 24 |
363555370 ps |
| T921 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2452416573 |
|
|
Apr 25 12:35:34 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
95561531 ps |
| T922 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2704777425 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:42 PM PDT 24 |
8731608985 ps |
| T923 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1096744662 |
|
|
Apr 25 12:35:28 PM PDT 24 |
Apr 25 12:35:33 PM PDT 24 |
129870911 ps |
| T924 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2551752480 |
|
|
Apr 25 12:35:34 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
109347431 ps |
| T925 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1468269624 |
|
|
Apr 25 12:35:16 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
196206455 ps |
| T926 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1758340693 |
|
|
Apr 25 12:35:09 PM PDT 24 |
Apr 25 12:35:13 PM PDT 24 |
20757462 ps |
| T927 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2220829375 |
|
|
Apr 25 12:35:27 PM PDT 24 |
Apr 25 12:35:29 PM PDT 24 |
48881968 ps |
| T928 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1246035798 |
|
|
Apr 25 12:35:31 PM PDT 24 |
Apr 25 12:35:37 PM PDT 24 |
539474881 ps |
| T929 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3538696429 |
|
|
Apr 25 12:35:35 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
25786090 ps |
| T930 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1563426298 |
|
|
Apr 25 12:35:27 PM PDT 24 |
Apr 25 12:35:30 PM PDT 24 |
83355287 ps |
| T931 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1254818133 |
|
|
Apr 25 12:35:37 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
42912979 ps |
| T932 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1923441708 |
|
|
Apr 25 12:35:10 PM PDT 24 |
Apr 25 12:35:14 PM PDT 24 |
47070127 ps |
| T933 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.188886186 |
|
|
Apr 25 12:35:27 PM PDT 24 |
Apr 25 12:35:32 PM PDT 24 |
217917229 ps |
| T201 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4212694198 |
|
|
Apr 25 12:35:12 PM PDT 24 |
Apr 25 12:35:17 PM PDT 24 |
13696470 ps |
| T934 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3441675768 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
512695644 ps |
| T935 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.862688357 |
|
|
Apr 25 12:35:15 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
108677103 ps |
| T936 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2915693259 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
18297793 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1348483068 |
|
|
Apr 25 12:35:30 PM PDT 24 |
Apr 25 12:35:37 PM PDT 24 |
121840470 ps |
| T937 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3125596949 |
|
|
Apr 25 12:35:11 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
540132923 ps |
| T938 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3448204655 |
|
|
Apr 25 12:35:26 PM PDT 24 |
Apr 25 12:35:34 PM PDT 24 |
782165279 ps |
| T939 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.994643745 |
|
|
Apr 25 12:35:26 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
83739939 ps |
| T940 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1363085258 |
|
|
Apr 25 12:35:31 PM PDT 24 |
Apr 25 12:35:35 PM PDT 24 |
33881307 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2422588805 |
|
|
Apr 25 12:35:09 PM PDT 24 |
Apr 25 12:35:13 PM PDT 24 |
47139209 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2858920005 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
37116924 ps |
| T943 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.556925034 |
|
|
Apr 25 12:35:23 PM PDT 24 |
Apr 25 12:35:26 PM PDT 24 |
33033040 ps |
| T944 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4091959527 |
|
|
Apr 25 12:35:12 PM PDT 24 |
Apr 25 12:35:18 PM PDT 24 |
250827663 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2563581804 |
|
|
Apr 25 12:34:59 PM PDT 24 |
Apr 25 12:35:02 PM PDT 24 |
55730431 ps |
| T202 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3485768537 |
|
|
Apr 25 12:35:37 PM PDT 24 |
Apr 25 12:35:41 PM PDT 24 |
15260626 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1636731536 |
|
|
Apr 25 12:35:10 PM PDT 24 |
Apr 25 12:35:14 PM PDT 24 |
15900316 ps |
| T947 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1737339617 |
|
|
Apr 25 12:35:25 PM PDT 24 |
Apr 25 12:35:29 PM PDT 24 |
30734100 ps |
| T948 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3662367059 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
13278943 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1859249768 |
|
|
Apr 25 12:35:10 PM PDT 24 |
Apr 25 12:35:18 PM PDT 24 |
413629780 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2424233946 |
|
|
Apr 25 12:35:25 PM PDT 24 |
Apr 25 12:35:29 PM PDT 24 |
934897564 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2173403316 |
|
|
Apr 25 12:35:10 PM PDT 24 |
Apr 25 12:35:15 PM PDT 24 |
140413908 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1406299860 |
|
|
Apr 25 12:35:17 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
45796829 ps |
| T953 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1646973448 |
|
|
Apr 25 12:35:39 PM PDT 24 |
Apr 25 12:35:43 PM PDT 24 |
53315525 ps |
| T954 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1191933678 |
|
|
Apr 25 12:35:24 PM PDT 24 |
Apr 25 12:35:33 PM PDT 24 |
347109142 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.910200540 |
|
|
Apr 25 12:35:10 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
2163068727 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3703990956 |
|
|
Apr 25 12:35:29 PM PDT 24 |
Apr 25 12:35:34 PM PDT 24 |
122306894 ps |
| T203 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3121274492 |
|
|
Apr 25 12:35:05 PM PDT 24 |
Apr 25 12:35:08 PM PDT 24 |
37816011 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4042628828 |
|
|
Apr 25 12:35:18 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
70957637 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2691261454 |
|
|
Apr 25 12:35:34 PM PDT 24 |
Apr 25 12:35:38 PM PDT 24 |
142046229 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2379878008 |
|
|
Apr 25 12:35:18 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
73400088 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2832718589 |
|
|
Apr 25 12:35:15 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
138722989 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3235242791 |
|
|
Apr 25 12:35:04 PM PDT 24 |
Apr 25 12:35:06 PM PDT 24 |
52742607 ps |
| T129 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2526331455 |
|
|
Apr 25 12:35:22 PM PDT 24 |
Apr 25 12:35:26 PM PDT 24 |
213959534 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.870049244 |
|
|
Apr 25 12:35:40 PM PDT 24 |
Apr 25 12:35:44 PM PDT 24 |
17440415 ps |
| T126 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.14808153 |
|
|
Apr 25 12:35:24 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
267524058 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1595247242 |
|
|
Apr 25 12:35:32 PM PDT 24 |
Apr 25 12:35:36 PM PDT 24 |
28454741 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1674829741 |
|
|
Apr 25 12:35:12 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
86758157 ps |
| T965 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4278224679 |
|
|
Apr 25 12:35:33 PM PDT 24 |
Apr 25 12:35:38 PM PDT 24 |
178179854 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.776928000 |
|
|
Apr 25 12:35:00 PM PDT 24 |
Apr 25 12:35:03 PM PDT 24 |
183860113 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.645662721 |
|
|
Apr 25 12:35:04 PM PDT 24 |
Apr 25 12:35:07 PM PDT 24 |
47300062 ps |
| T968 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1106714083 |
|
|
Apr 25 12:35:17 PM PDT 24 |
Apr 25 12:35:25 PM PDT 24 |
4977192185 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1181923791 |
|
|
Apr 25 12:35:28 PM PDT 24 |
Apr 25 12:35:31 PM PDT 24 |
450486156 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2353620475 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:23 PM PDT 24 |
570943224 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.584415281 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
28354777 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3528958840 |
|
|
Apr 25 12:35:28 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
4140196068 ps |
| T973 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2825877953 |
|
|
Apr 25 12:35:31 PM PDT 24 |
Apr 25 12:35:36 PM PDT 24 |
19542033 ps |
| T974 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.610860382 |
|
|
Apr 25 12:35:19 PM PDT 24 |
Apr 25 12:35:23 PM PDT 24 |
42328924 ps |
| T975 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.145909850 |
|
|
Apr 25 12:35:43 PM PDT 24 |
Apr 25 12:35:46 PM PDT 24 |
27244483 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3365917319 |
|
|
Apr 25 12:35:25 PM PDT 24 |
Apr 25 12:35:29 PM PDT 24 |
876006441 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4176293536 |
|
|
Apr 25 12:35:28 PM PDT 24 |
Apr 25 12:35:31 PM PDT 24 |
64064066 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3870180598 |
|
|
Apr 25 12:35:15 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
264750992 ps |
| T979 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1752705685 |
|
|
Apr 25 12:35:24 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
26982674 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.996353195 |
|
|
Apr 25 12:35:14 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
33367546 ps |
| T137 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1035652513 |
|
|
Apr 25 12:35:35 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
139507181 ps |
| T981 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3003413908 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
363800736 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.692394275 |
|
|
Apr 25 12:35:09 PM PDT 24 |
Apr 25 12:35:20 PM PDT 24 |
340976079 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3192184227 |
|
|
Apr 25 12:35:25 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
68589642 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3762557036 |
|
|
Apr 25 12:35:17 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
334580499 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2107861412 |
|
|
Apr 25 12:35:15 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
55927218 ps |
| T204 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.284550647 |
|
|
Apr 25 12:35:26 PM PDT 24 |
Apr 25 12:35:28 PM PDT 24 |
12448116 ps |
| T986 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2133580367 |
|
|
Apr 25 12:35:21 PM PDT 24 |
Apr 25 12:35:29 PM PDT 24 |
11576738205 ps |
| T987 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2508558316 |
|
|
Apr 25 12:35:31 PM PDT 24 |
Apr 25 12:35:35 PM PDT 24 |
42369076 ps |
| T123 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.106154262 |
|
|
Apr 25 12:35:33 PM PDT 24 |
Apr 25 12:35:39 PM PDT 24 |
309997647 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3045188577 |
|
|
Apr 25 12:35:00 PM PDT 24 |
Apr 25 12:35:06 PM PDT 24 |
450102410 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3105522894 |
|
|
Apr 25 12:35:21 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
44319973 ps |
| T205 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1690201029 |
|
|
Apr 25 12:35:06 PM PDT 24 |
Apr 25 12:35:09 PM PDT 24 |
18344028 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2748189762 |
|
|
Apr 25 12:35:19 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
165644694 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1890898462 |
|
|
Apr 25 12:35:18 PM PDT 24 |
Apr 25 12:35:45 PM PDT 24 |
2367627162 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.920586846 |
|
|
Apr 25 12:35:16 PM PDT 24 |
Apr 25 12:35:21 PM PDT 24 |
65362961 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3586884567 |
|
|
Apr 25 12:35:13 PM PDT 24 |
Apr 25 12:35:19 PM PDT 24 |
52710045 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3276330816 |
|
|
Apr 25 12:35:29 PM PDT 24 |
Apr 25 12:35:33 PM PDT 24 |
35723390 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4202211736 |
|
|
Apr 25 12:35:12 PM PDT 24 |
Apr 25 12:35:18 PM PDT 24 |
17733344 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3618031513 |
|
|
Apr 25 12:35:20 PM PDT 24 |
Apr 25 12:35:29 PM PDT 24 |
1059930637 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2471743611 |
|
|
Apr 25 12:35:29 PM PDT 24 |
Apr 25 12:35:33 PM PDT 24 |
30659214 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3323952911 |
|
|
Apr 25 12:35:32 PM PDT 24 |
Apr 25 12:35:40 PM PDT 24 |
248294936 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2868146135 |
|
|
Apr 25 12:35:15 PM PDT 24 |
Apr 25 12:35:22 PM PDT 24 |
302467383 ps |
| T999 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3929945134 |
|
|
Apr 25 12:35:21 PM PDT 24 |
Apr 25 12:35:33 PM PDT 24 |
739249065 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1581612267 |
|
|
Apr 25 12:35:18 PM PDT 24 |
Apr 25 12:35:24 PM PDT 24 |
102965159 ps |