Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54476 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
286 |
auto[1] |
1896 |
1 |
|
|
T3 |
19 |
|
T13 |
25 |
|
T15 |
28 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55634 |
1 |
|
|
T1 |
71 |
|
T2 |
39 |
|
T3 |
305 |
auto[1] |
738 |
1 |
|
|
T1 |
13 |
|
T2 |
11 |
|
T12 |
24 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54243 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
293 |
auto[1] |
2129 |
1 |
|
|
T3 |
12 |
|
T11 |
15 |
|
T14 |
8 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54249 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
291 |
auto[1] |
2123 |
1 |
|
|
T3 |
14 |
|
T11 |
7 |
|
T14 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54194 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
290 |
auto[1] |
2178 |
1 |
|
|
T3 |
15 |
|
T11 |
13 |
|
T13 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51193 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
258 |
no_err_inj |
5179 |
1 |
|
|
T3 |
47 |
|
T13 |
5 |
|
T4 |
10 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54436 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
292 |
auto[1] |
1936 |
1 |
|
|
T3 |
13 |
|
T13 |
24 |
|
T15 |
41 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55739 |
1 |
|
|
T1 |
68 |
|
T2 |
44 |
|
T3 |
305 |
auto[1] |
633 |
1 |
|
|
T1 |
16 |
|
T2 |
6 |
|
T12 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39163 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
280 |
auto[1] |
17209 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
209 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54265 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
291 |
auto[1] |
2107 |
1 |
|
|
T3 |
14 |
|
T11 |
9 |
|
T13 |
2 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54199 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
295 |
auto[1] |
2173 |
1 |
|
|
T3 |
10 |
|
T11 |
11 |
|
T13 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54330 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
293 |
auto[1] |
2042 |
1 |
|
|
T3 |
12 |
|
T11 |
11 |
|
T13 |
3 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54450 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
287 |
auto[1] |
1922 |
1 |
|
|
T3 |
18 |
|
T13 |
26 |
|
T15 |
40 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54200 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
296 |
auto[1] |
2172 |
1 |
|
|
T3 |
9 |
|
T21 |
7 |
|
T55 |
17 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55681 |
1 |
|
|
T1 |
65 |
|
T2 |
41 |
|
T3 |
305 |
auto[1] |
691 |
1 |
|
|
T1 |
19 |
|
T2 |
9 |
|
T12 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55649 |
1 |
|
|
T1 |
64 |
|
T2 |
39 |
|
T3 |
305 |
auto[1] |
723 |
1 |
|
|
T1 |
20 |
|
T2 |
11 |
|
T12 |
18 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55658 |
1 |
|
|
T1 |
68 |
|
T2 |
37 |
|
T3 |
305 |
auto[1] |
714 |
1 |
|
|
T1 |
16 |
|
T2 |
13 |
|
T12 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53414 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
280 |
auto[1] |
2958 |
1 |
|
|
T3 |
25 |
|
T13 |
14 |
|
T15 |
24 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52630 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
305 |
auto[1] |
3742 |
1 |
|
|
T9 |
63 |
|
T36 |
57 |
|
T17 |
98 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54350 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
296 |
auto[1] |
2022 |
1 |
|
|
T3 |
9 |
|
T11 |
10 |
|
T14 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54349 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
288 |
auto[1] |
2023 |
1 |
|
|
T3 |
17 |
|
T11 |
7 |
|
T14 |
7 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54333 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
290 |
auto[1] |
2039 |
1 |
|
|
T3 |
15 |
|
T11 |
10 |
|
T13 |
2 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54451 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
287 |
auto[1] |
1921 |
1 |
|
|
T3 |
18 |
|
T13 |
16 |
|
T15 |
30 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50774 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
296 |
auto[1] |
5598 |
1 |
|
|
T3 |
9 |
|
T10 |
54 |
|
T13 |
18 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52557 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
305 |
auto[1] |
3815 |
1 |
|
|
T44 |
60 |
|
T56 |
75 |
|
T57 |
100 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56372 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
305 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54405 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
289 |
auto[1] |
1967 |
1 |
|
|
T3 |
16 |
|
T13 |
15 |
|
T15 |
23 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54416 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
283 |
auto[1] |
1956 |
1 |
|
|
T3 |
22 |
|
T13 |
13 |
|
T15 |
37 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54439 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
289 |
auto[1] |
1933 |
1 |
|
|
T3 |
16 |
|
T13 |
26 |
|
T15 |
35 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49697 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
245 |
auto[0] |
no_err_inj |
3717 |
1 |
|
|
T3 |
35 |
|
T4 |
10 |
|
T15 |
8 |
auto[1] |
err_inj |
1496 |
1 |
|
|
T3 |
13 |
|
T13 |
9 |
|
T15 |
14 |
auto[1] |
no_err_inj |
1462 |
1 |
|
|
T3 |
12 |
|
T13 |
5 |
|
T15 |
10 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51553 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
265 |
auto[0] |
auto[1] |
1861 |
1 |
|
|
T3 |
15 |
|
T11 |
7 |
|
T14 |
7 |
auto[1] |
auto[0] |
2796 |
1 |
|
|
T3 |
23 |
|
T13 |
14 |
|
T15 |
24 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T3 |
2 |
|
T22 |
3 |
|
T42 |
8 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51420 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
270 |
auto[0] |
auto[1] |
1994 |
1 |
|
|
T3 |
10 |
|
T11 |
11 |
|
T14 |
9 |
auto[1] |
auto[0] |
2779 |
1 |
|
|
T3 |
25 |
|
T13 |
13 |
|
T15 |
21 |
auto[1] |
auto[1] |
179 |
1 |
|
|
T13 |
1 |
|
T15 |
3 |
|
T22 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51548 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
267 |
auto[0] |
auto[1] |
1866 |
1 |
|
|
T3 |
13 |
|
T11 |
10 |
|
T14 |
3 |
auto[1] |
auto[0] |
2785 |
1 |
|
|
T3 |
23 |
|
T13 |
12 |
|
T15 |
24 |
auto[1] |
auto[1] |
173 |
1 |
|
|
T3 |
2 |
|
T13 |
2 |
|
T22 |
4 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51439 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
268 |
auto[0] |
auto[1] |
1975 |
1 |
|
|
T3 |
12 |
|
T11 |
7 |
|
T14 |
9 |
auto[1] |
auto[0] |
2810 |
1 |
|
|
T3 |
23 |
|
T13 |
14 |
|
T15 |
21 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T3 |
2 |
|
T15 |
3 |
|
T22 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51415 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
267 |
auto[0] |
auto[1] |
1999 |
1 |
|
|
T3 |
13 |
|
T11 |
13 |
|
T14 |
5 |
auto[1] |
auto[0] |
2779 |
1 |
|
|
T3 |
23 |
|
T13 |
13 |
|
T15 |
24 |
auto[1] |
auto[1] |
179 |
1 |
|
|
T3 |
2 |
|
T13 |
1 |
|
T22 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51448 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
269 |
auto[0] |
auto[1] |
1966 |
1 |
|
|
T3 |
11 |
|
T11 |
15 |
|
T14 |
8 |
auto[1] |
auto[0] |
2795 |
1 |
|
|
T3 |
24 |
|
T13 |
14 |
|
T15 |
23 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T3 |
1 |
|
T15 |
1 |
|
T22 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38034 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
261 |
auto[0] |
auto[1] |
1129 |
1 |
|
|
T3 |
19 |
|
T13 |
25 |
|
T15 |
3 |
auto[1] |
auto[0] |
16442 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
184 |
auto[1] |
auto[1] |
767 |
1 |
|
|
T15 |
25 |
|
T22 |
12 |
|
T16 |
9 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37976 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
267 |
auto[0] |
auto[1] |
1187 |
1 |
|
|
T3 |
13 |
|
T13 |
24 |
|
T15 |
9 |
auto[1] |
auto[0] |
16460 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
177 |
auto[1] |
auto[1] |
749 |
1 |
|
|
T15 |
32 |
|
T22 |
14 |
|
T16 |
10 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37943 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
271 |
auto[0] |
auto[1] |
1220 |
1 |
|
|
T3 |
9 |
|
T21 |
7 |
|
T55 |
17 |
auto[1] |
auto[0] |
16257 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
209 |
auto[1] |
auto[1] |
952 |
1 |
|
|
T22 |
18 |
|
T16 |
15 |
|
T23 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37974 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
262 |
auto[0] |
auto[1] |
1189 |
1 |
|
|
T3 |
18 |
|
T13 |
26 |
|
T15 |
7 |
auto[1] |
auto[0] |
16476 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
176 |
auto[1] |
auto[1] |
733 |
1 |
|
|
T15 |
33 |
|
T22 |
16 |
|
T16 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34308 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
271 |
auto[0] |
auto[1] |
4855 |
1 |
|
|
T3 |
9 |
|
T10 |
54 |
|
T13 |
18 |
auto[1] |
auto[0] |
16466 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
187 |
auto[1] |
auto[1] |
743 |
1 |
|
|
T15 |
22 |
|
T22 |
23 |
|
T16 |
7 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38007 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
265 |
auto[0] |
auto[1] |
1156 |
1 |
|
|
T3 |
15 |
|
T11 |
7 |
|
T14 |
7 |
auto[1] |
auto[0] |
16342 |
1 |
|
|
T3 |
23 |
|
T4 |
10 |
|
T15 |
209 |
auto[1] |
auto[1] |
867 |
1 |
|
|
T3 |
2 |
|
T22 |
3 |
|
T16 |
10 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38015 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
271 |
auto[0] |
auto[1] |
1148 |
1 |
|
|
T3 |
9 |
|
T11 |
10 |
|
T14 |
8 |
auto[1] |
auto[0] |
16335 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
209 |
auto[1] |
auto[1] |
874 |
1 |
|
|
T22 |
5 |
|
T16 |
17 |
|
T25 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37931 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
270 |
auto[0] |
auto[1] |
1232 |
1 |
|
|
T3 |
10 |
|
T11 |
11 |
|
T13 |
1 |
auto[1] |
auto[0] |
16268 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
209 |
auto[1] |
auto[1] |
941 |
1 |
|
|
T22 |
3 |
|
T16 |
19 |
|
T25 |
5 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37972 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
269 |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T3 |
11 |
|
T11 |
9 |
|
T13 |
2 |
auto[1] |
auto[0] |
16293 |
1 |
|
|
T3 |
22 |
|
T4 |
10 |
|
T15 |
209 |
auto[1] |
auto[1] |
916 |
1 |
|
|
T3 |
3 |
|
T22 |
1 |
|
T16 |
15 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37949 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
268 |
auto[0] |
auto[1] |
1214 |
1 |
|
|
T3 |
12 |
|
T11 |
7 |
|
T14 |
9 |
auto[1] |
auto[0] |
16300 |
1 |
|
|
T3 |
23 |
|
T4 |
10 |
|
T15 |
209 |
auto[1] |
auto[1] |
909 |
1 |
|
|
T3 |
2 |
|
T22 |
1 |
|
T16 |
13 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37973 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
269 |
auto[0] |
auto[1] |
1190 |
1 |
|
|
T3 |
11 |
|
T11 |
15 |
|
T14 |
8 |
auto[1] |
auto[0] |
16270 |
1 |
|
|
T3 |
24 |
|
T4 |
10 |
|
T15 |
209 |
auto[1] |
auto[1] |
939 |
1 |
|
|
T3 |
1 |
|
T22 |
2 |
|
T16 |
14 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37971 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
264 |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T3 |
16 |
|
T13 |
26 |
|
T15 |
5 |
auto[1] |
auto[0] |
16468 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
179 |
auto[1] |
auto[1] |
741 |
1 |
|
|
T15 |
30 |
|
T22 |
18 |
|
T16 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37954 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
258 |
auto[0] |
auto[1] |
1209 |
1 |
|
|
T3 |
22 |
|
T13 |
13 |
|
T15 |
9 |
auto[1] |
auto[0] |
16462 |
1 |
|
|
T3 |
25 |
|
T4 |
10 |
|
T15 |
181 |
auto[1] |
auto[1] |
747 |
1 |
|
|
T15 |
28 |
|
T22 |
14 |
|
T16 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37368 |
1 |
|
|
T1 |
84 |
|
T2 |
50 |
|
T3 |
280 |
auto[0] |
auto[1] |
1795 |
1 |
|
|
T13 |
14 |
|
T15 |
24 |
|
T200 |
10 |
auto[1] |
auto[0] |
16046 |
1 |
|
|
T4 |
10 |
|
T15 |
209 |
|
T22 |
159 |
auto[1] |
auto[1] |
1163 |
1 |
|
|
T3 |
25 |
|
T22 |
32 |
|
T42 |
53 |