Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105494494

1

T1

29237

T2

46083

T3

175781

auto[1]

1461265

1

T1

1584

T2

1188

T3

6432

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105487903

1

T1

29138

T2

46281

T3

176874

auto[1]

1467856

1

T1

1683

T2

990

T3

5339

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7721379	1			T1	9702		T2	5663		T3	30897
auto[IdleSt]	22607349	1			T1	2222		T2	4909		T3	40976
auto[ClkMuxSt]	36429	1			T1	64		T2	39		T3	185
auto[CntIncrSt]	36184	1			T1	64		T2	39		T3	185
auto[CntProgSt]	2014216	1			T1	1578		T2	558		T3	310
auto[TransCheckSt]	28302	1			T1	51		T2	28		T3	138
auto[TokenHashSt]	39153335	1			T1	1733		T2	23717		T3	2671
auto[FlashRmaSt]	29277	1			T1	127		T2	63		T3	182
auto[TokenCheck0St]	13078	1			T1	42		T2	24		T3	79
auto[TokenCheck1St]	9829	1			T1	29		T2	19		T3	66
auto[TransProgSt]	542268	1			T1	742		T2	411		T3	129
auto[PostTransSt]	13256214	1			T1	8561		T2	6305		T3	48978
auto[ScrapSt]	361308	1			T3	661		T39	83		T36	6
auto[EscalateSt]	7477595	1			T1	4354		T2	3218		T3	28424
auto[InvalidSt]	13666742	1			T1	1552		T2	2278		T3	28322

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2254	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13666742	1			T1	1552		T2	2278		T3	28322
EscalateSt	7477595	1			T1	4354		T2	3218		T3	28424
ScrapSt	361308	1			T3	661		T39	83		T36	6
PostTransSt	13256214	1			T1	8561		T2	6305		T3	48978
TransProgSt	542268	1			T1	742		T2	411		T3	129
TokenCheck1St	9829	1			T1	29		T2	19		T3	66
TokenCheck0St	13078	1			T1	42		T2	24		T3	79
FlashRmaSt	29277	1			T1	127		T2	63		T3	182
TokenHashSt	39153335	1			T1	1733		T2	23717		T3	2671
TransCheckSt	28302	1			T1	51		T2	28		T3	138
CntProgSt	2014216	1			T1	1578		T2	558		T3	310
CntIncrSt	36184	1			T1	64		T2	39		T3	185
ClkMuxSt	36429	1			T1	64		T2	39		T3	185
IdleSt	22607349	1			T1	2222		T2	4909		T3	40976
ResetSt	7721379	1			T1	9702		T2	5663		T3	30897
arcs[ResetSt=>IdleSt]	56583	1			T1	85		T2	51		T3	301
arcs[IdleSt=>ScrapSt]	292	1			T3	2		T39	6		T36	2
arcs[IdleSt=>ClkMuxSt]	36247	1			T1	64		T2	39		T3	185
arcs[ClkMuxSt=>CntIncrSt]	36184	1			T1	64		T2	39		T3	185
arcs[CntIncrSt=>PostTransSt]	1960	1			T3	22		T13	13		T15	37
arcs[CntIncrSt=>CntProgSt]	34166	1			T1	64		T2	39		T3	163
arcs[CntProgSt=>PostTransSt]	4779	1			T1	13		T2	11		T3	25
arcs[CntProgSt=>TransCheckSt]	28302	1			T1	51		T2	28		T3	138
arcs[TransCheckSt=>PostTransSt]	3924	1			T3	16		T13	26		T15	35
arcs[TransCheckSt=>TokenHashSt]	24242	1			T1	51		T2	28		T3	122
arcs[TokenHashSt=>PostTransSt]	10403	1			T1	9		T2	4		T3	43
arcs[TokenHashSt=>FlashRmaSt]	13168	1			T1	42		T2	24		T3	79
arcs[FlashRmaSt=>TokenCheck0St]	13078	1			T1	42		T2	24		T3	79
arcs[TokenCheck0St=>PostTransSt]	3231	1			T1	13		T2	5		T3	13
arcs[TokenCheck0St=>TokenCheck1St]	9829	1			T1	29		T2	19		T3	66
arcs[TokenCheck1St=>PostTransSt]	678	1			T1	3		T2	1		T12	2
arcs[TransProgSt=>PostTransSt]	8265	1			T1	26		T2	18		T3	66
arcs[IdleSt=>EscalateSt]	174	1			T9	3		T36	4		T46	7
arcs[ClkMuxSt=>EscalateSt]	63	1			T9	1		T36	1		T17	2
arcs[CntIncrSt=>EscalateSt]	58	1			T36	1		T17	3		T45	1
arcs[CntProgSt=>EscalateSt]	1085	1			T9	6		T36	14		T17	22
arcs[TransCheckSt=>EscalateSt]	136	1			T9	6		T36	3		T17	3
arcs[TokenHashSt=>EscalateSt]	671	1			T9	10		T36	15		T17	24
arcs[FlashRmaSt=>EscalateSt]	90	1			T17	2		T46	3		T47	1
arcs[TokenCheck0St=>EscalateSt]	18	1			T36	2		T50	1		T51	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T9	2		T36	1		T17	3
arcs[TransProgSt=>EscalateSt]	747	1			T9	11		T36	5		T17	26
arcs[PostTransSt=>EscalateSt]	5046	1			T1	13		T2	11		T3	28
arcs[InvalidSt=>EscalateSt]	15488	1			T1	20		T2	11		T3	91

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7721196	1			T1	9702		T2	5663		T3	30897
auto[0]	auto[IdleSt]	22607228	1			T1	2222		T2	4909		T3	40976
auto[0]	auto[ClkMuxSt]	36385	1			T1	64		T2	39		T3	185
auto[0]	auto[CntIncrSt]	36147	1			T1	64		T2	39		T3	185
auto[0]	auto[CntProgSt]	2013501	1			T1	1578		T2	558		T3	310
auto[0]	auto[TransCheckSt]	28211	1			T1	51		T2	28		T3	138
auto[0]	auto[TokenHashSt]	39152870	1			T1	1733		T2	23717		T3	2671
auto[0]	auto[FlashRmaSt]	29222	1			T1	127		T2	63		T3	182
auto[0]	auto[TokenCheck0St]	13068	1			T1	42		T2	24		T3	79
auto[0]	auto[TokenCheck1St]	9738	1			T1	29		T2	19		T3	66
auto[0]	auto[TransProgSt]	541782	1			T1	742		T2	411		T3	129
auto[0]	auto[PostTransSt]	13253690	1			T1	8554		T2	6299		T3	48966
auto[0]	auto[ScrapSt]	361266	1			T3	661		T39	83		T36	6
auto[0]	auto[EscalateSt]	6028916	1			T1	2786		T2	2042		T3	22057
auto[0]	auto[InvalidSt]	13659020	1			T1	1543		T2	2272		T3	28269
auto[1]	auto[ResetSt]	183	1			T9	3		T36	2		T17	8
auto[1]	auto[IdleSt]	121	1			T9	3		T36	3		T46	5
auto[1]	auto[ClkMuxSt]	44	1			T9	1		T36	1		T17	2
auto[1]	auto[CntIncrSt]	37	1			T17	3		T45	1		T196	1
auto[1]	auto[CntProgSt]	715	1			T9	4		T36	6		T17	14
auto[1]	auto[TransCheckSt]	91	1			T9	5		T36	1		T17	3
auto[1]	auto[TokenHashSt]	465	1			T9	8		T36	13		T17	17
auto[1]	auto[FlashRmaSt]	55	1			T17	2		T46	1		T47	1
auto[1]	auto[TokenCheck0St]	10	1			T36	1		T50	1		T51	1
auto[1]	auto[TokenCheck1St]	91	1			T9	1		T17	1		T47	1
auto[1]	auto[TransProgSt]	486	1			T9	7		T36	5		T17	23
auto[1]	auto[PostTransSt]	2524	1			T1	7		T2	6		T3	12
auto[1]	auto[ScrapSt]	42	1			T17	1		T46	1		T45	1
auto[1]	auto[EscalateSt]	1448679	1			T1	1568		T2	1176		T3	6367
auto[1]	auto[InvalidSt]	7722	1			T1	9		T2	6		T3	53

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7721211	1			T1	9702		T2	5663		T3	30897
auto[0]	auto[IdleSt]	22607241	1			T1	2222		T2	4909		T3	40976
auto[0]	auto[ClkMuxSt]	36382	1			T1	64		T2	39		T3	185
auto[0]	auto[CntIncrSt]	36140	1			T1	64		T2	39		T3	185
auto[0]	auto[CntProgSt]	2013489	1			T1	1578		T2	558		T3	310
auto[0]	auto[TransCheckSt]	28208	1			T1	51		T2	28		T3	138
auto[0]	auto[TokenHashSt]	39152899	1			T1	1733		T2	23717		T3	2671
auto[0]	auto[FlashRmaSt]	29217	1			T1	127		T2	63		T3	182
auto[0]	auto[TokenCheck0St]	13068	1			T1	42		T2	24		T3	79
auto[0]	auto[TokenCheck1St]	9736	1			T1	29		T2	19		T3	66
auto[0]	auto[TransProgSt]	541765	1			T1	742		T2	411		T3	129
auto[0]	auto[PostTransSt]	13253611	1			T1	8555		T2	6300		T3	48962
auto[0]	auto[ScrapSt]	361262	1			T3	661		T39	83		T36	4
auto[0]	auto[EscalateSt]	6022444	1			T1	2688		T2	2238		T3	23139
auto[0]	auto[InvalidSt]	13658976	1			T1	1541		T2	2273		T3	28284
auto[1]	auto[ResetSt]	168	1			T9	4		T36	4		T17	5
auto[1]	auto[IdleSt]	108	1			T9	1		T36	3		T46	6
auto[1]	auto[ClkMuxSt]	47	1			T46	1		T47	2		T45	1
auto[1]	auto[CntIncrSt]	44	1			T36	1		T17	3		T196	2
auto[1]	auto[CntProgSt]	727	1			T9	5		T36	11		T17	14
auto[1]	auto[TransCheckSt]	94	1			T9	3		T36	3		T17	2
auto[1]	auto[TokenHashSt]	436	1			T9	3		T36	8		T17	14
auto[1]	auto[FlashRmaSt]	60	1			T46	2		T196	4		T197	3
auto[1]	auto[TokenCheck0St]	10	1			T36	1		T198	2		T199	1
auto[1]	auto[TokenCheck1St]	93	1			T9	1		T36	1		T17	2
auto[1]	auto[TransProgSt]	503	1			T9	7		T36	3		T17	13
auto[1]	auto[PostTransSt]	2603	1			T1	6		T2	5		T3	16
auto[1]	auto[ScrapSt]	46	1			T36	2		T17	2		T46	2
auto[1]	auto[EscalateSt]	1455151	1			T1	1666		T2	980		T3	5285
auto[1]	auto[InvalidSt]	7766	1			T1	11		T2	5		T3	38