| T805 |
/workspace/coverage/default/10.lc_ctrl_jtag_errors.3569297578 |
|
|
Apr 28 04:51:47 PM PDT 24 |
Apr 28 04:52:10 PM PDT 24 |
1315199789 ps |
| T806 |
/workspace/coverage/default/26.lc_ctrl_state_failure.4237406595 |
|
|
Apr 28 04:52:58 PM PDT 24 |
Apr 28 04:53:27 PM PDT 24 |
2423690735 ps |
| T807 |
/workspace/coverage/default/1.lc_ctrl_alert_test.2617065098 |
|
|
Apr 28 04:50:39 PM PDT 24 |
Apr 28 04:50:40 PM PDT 24 |
55622688 ps |
| T808 |
/workspace/coverage/default/33.lc_ctrl_jtag_access.957543695 |
|
|
Apr 28 04:53:19 PM PDT 24 |
Apr 28 04:53:29 PM PDT 24 |
3062393990 ps |
| T809 |
/workspace/coverage/default/11.lc_ctrl_sec_token_digest.135283486 |
|
|
Apr 28 04:51:54 PM PDT 24 |
Apr 28 04:52:10 PM PDT 24 |
3498898364 ps |
| T810 |
/workspace/coverage/default/35.lc_ctrl_alert_test.3463577043 |
|
|
Apr 28 04:53:35 PM PDT 24 |
Apr 28 04:53:36 PM PDT 24 |
19407467 ps |
| T811 |
/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.319928244 |
|
|
Apr 28 04:51:20 PM PDT 24 |
Apr 28 04:51:33 PM PDT 24 |
1297522476 ps |
| T812 |
/workspace/coverage/default/39.lc_ctrl_jtag_access.2653496078 |
|
|
Apr 28 04:53:39 PM PDT 24 |
Apr 28 04:53:42 PM PDT 24 |
121155149 ps |
| T813 |
/workspace/coverage/default/15.lc_ctrl_jtag_smoke.3805933555 |
|
|
Apr 28 04:52:11 PM PDT 24 |
Apr 28 04:52:18 PM PDT 24 |
1066880960 ps |
| T814 |
/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3925736107 |
|
|
Apr 28 04:51:59 PM PDT 24 |
Apr 28 04:52:06 PM PDT 24 |
323659232 ps |
| T815 |
/workspace/coverage/default/8.lc_ctrl_security_escalation.439191816 |
|
|
Apr 28 04:51:33 PM PDT 24 |
Apr 28 04:51:41 PM PDT 24 |
414183770 ps |
| T816 |
/workspace/coverage/default/17.lc_ctrl_state_post_trans.2990408468 |
|
|
Apr 28 04:52:24 PM PDT 24 |
Apr 28 04:52:32 PM PDT 24 |
279986097 ps |
| T817 |
/workspace/coverage/default/47.lc_ctrl_sec_mubi.2129664087 |
|
|
Apr 28 04:54:05 PM PDT 24 |
Apr 28 04:54:23 PM PDT 24 |
1530150873 ps |
| T818 |
/workspace/coverage/default/32.lc_ctrl_errors.52968793 |
|
|
Apr 28 04:53:14 PM PDT 24 |
Apr 28 04:53:25 PM PDT 24 |
1024454608 ps |
| T819 |
/workspace/coverage/default/10.lc_ctrl_sec_token_mux.1474689655 |
|
|
Apr 28 04:51:48 PM PDT 24 |
Apr 28 04:52:11 PM PDT 24 |
2511513605 ps |
| T820 |
/workspace/coverage/default/36.lc_ctrl_alert_test.1344282880 |
|
|
Apr 28 04:53:33 PM PDT 24 |
Apr 28 04:53:35 PM PDT 24 |
14323838 ps |
| T821 |
/workspace/coverage/default/10.lc_ctrl_smoke.1305509864 |
|
|
Apr 28 04:51:47 PM PDT 24 |
Apr 28 04:51:50 PM PDT 24 |
153100573 ps |
| T822 |
/workspace/coverage/default/44.lc_ctrl_alert_test.1793105587 |
|
|
Apr 28 04:53:56 PM PDT 24 |
Apr 28 04:53:58 PM PDT 24 |
32321787 ps |
| T823 |
/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.811892953 |
|
|
Apr 28 04:53:46 PM PDT 24 |
Apr 28 04:53:47 PM PDT 24 |
71747381 ps |
| T824 |
/workspace/coverage/default/5.lc_ctrl_regwen_during_op.2977031395 |
|
|
Apr 28 04:51:11 PM PDT 24 |
Apr 28 04:51:22 PM PDT 24 |
400774898 ps |
| T825 |
/workspace/coverage/default/9.lc_ctrl_errors.3972738594 |
|
|
Apr 28 04:51:44 PM PDT 24 |
Apr 28 04:51:58 PM PDT 24 |
1203032228 ps |
| T826 |
/workspace/coverage/default/37.lc_ctrl_alert_test.4150303006 |
|
|
Apr 28 04:53:49 PM PDT 24 |
Apr 28 04:53:51 PM PDT 24 |
15076722 ps |
| T827 |
/workspace/coverage/default/31.lc_ctrl_smoke.1746112053 |
|
|
Apr 28 04:53:11 PM PDT 24 |
Apr 28 04:53:16 PM PDT 24 |
550459225 ps |
| T191 |
/workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.288380924 |
|
|
Apr 28 04:53:15 PM PDT 24 |
Apr 28 05:13:26 PM PDT 24 |
30493871807 ps |
| T828 |
/workspace/coverage/default/18.lc_ctrl_alert_test.1008936367 |
|
|
Apr 28 04:52:31 PM PDT 24 |
Apr 28 04:52:32 PM PDT 24 |
64456257 ps |
| T829 |
/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1136667794 |
|
|
Apr 28 04:52:01 PM PDT 24 |
Apr 28 04:52:43 PM PDT 24 |
12891871220 ps |
| T830 |
/workspace/coverage/default/39.lc_ctrl_alert_test.4232274355 |
|
|
Apr 28 04:53:43 PM PDT 24 |
Apr 28 04:53:45 PM PDT 24 |
66891344 ps |
| T831 |
/workspace/coverage/default/38.lc_ctrl_stress_all.1829038914 |
|
|
Apr 28 04:53:37 PM PDT 24 |
Apr 28 04:54:45 PM PDT 24 |
5451628902 ps |
| T832 |
/workspace/coverage/default/30.lc_ctrl_security_escalation.3031539064 |
|
|
Apr 28 04:53:13 PM PDT 24 |
Apr 28 04:53:25 PM PDT 24 |
296174385 ps |
| T833 |
/workspace/coverage/default/0.lc_ctrl_claim_transition_if.3677948505 |
|
|
Apr 28 04:50:20 PM PDT 24 |
Apr 28 04:50:22 PM PDT 24 |
19288495 ps |
| T834 |
/workspace/coverage/default/16.lc_ctrl_sec_token_mux.3709881398 |
|
|
Apr 28 04:52:22 PM PDT 24 |
Apr 28 04:52:31 PM PDT 24 |
295209413 ps |
| T835 |
/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3017328480 |
|
|
Apr 28 04:52:19 PM PDT 24 |
Apr 28 04:53:06 PM PDT 24 |
3665201203 ps |
| T836 |
/workspace/coverage/default/2.lc_ctrl_state_post_trans.923502094 |
|
|
Apr 28 04:50:42 PM PDT 24 |
Apr 28 04:50:46 PM PDT 24 |
109512309 ps |
| T837 |
/workspace/coverage/default/27.lc_ctrl_smoke.354989262 |
|
|
Apr 28 04:53:00 PM PDT 24 |
Apr 28 04:53:05 PM PDT 24 |
257802603 ps |
| T838 |
/workspace/coverage/default/39.lc_ctrl_security_escalation.3478446457 |
|
|
Apr 28 04:53:43 PM PDT 24 |
Apr 28 04:53:52 PM PDT 24 |
483602959 ps |
| T839 |
/workspace/coverage/default/0.lc_ctrl_smoke.1132064549 |
|
|
Apr 28 04:50:18 PM PDT 24 |
Apr 28 04:50:21 PM PDT 24 |
60960122 ps |
| T840 |
/workspace/coverage/default/21.lc_ctrl_sec_token_digest.2162448585 |
|
|
Apr 28 04:52:42 PM PDT 24 |
Apr 28 04:52:58 PM PDT 24 |
2970605181 ps |
| T841 |
/workspace/coverage/default/6.lc_ctrl_security_escalation.31366839 |
|
|
Apr 28 04:51:20 PM PDT 24 |
Apr 28 04:51:30 PM PDT 24 |
1064912142 ps |
| T842 |
/workspace/coverage/default/43.lc_ctrl_sec_mubi.1072660096 |
|
|
Apr 28 04:54:03 PM PDT 24 |
Apr 28 04:54:16 PM PDT 24 |
322414794 ps |
| T843 |
/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3802305732 |
|
|
Apr 28 04:52:29 PM PDT 24 |
Apr 28 04:53:41 PM PDT 24 |
26156107155 ps |
| T844 |
/workspace/coverage/default/9.lc_ctrl_security_escalation.636475033 |
|
|
Apr 28 04:51:47 PM PDT 24 |
Apr 28 04:52:02 PM PDT 24 |
1471426559 ps |
| T845 |
/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1166993932 |
|
|
Apr 28 04:51:47 PM PDT 24 |
Apr 28 04:52:03 PM PDT 24 |
1149480524 ps |
| T846 |
/workspace/coverage/default/43.lc_ctrl_sec_token_mux.3871080968 |
|
|
Apr 28 04:54:09 PM PDT 24 |
Apr 28 04:54:21 PM PDT 24 |
2038297016 ps |
| T847 |
/workspace/coverage/default/6.lc_ctrl_state_failure.1088783063 |
|
|
Apr 28 04:51:20 PM PDT 24 |
Apr 28 04:51:42 PM PDT 24 |
918059992 ps |
| T848 |
/workspace/coverage/default/35.lc_ctrl_errors.2891271943 |
|
|
Apr 28 04:53:29 PM PDT 24 |
Apr 28 04:53:43 PM PDT 24 |
457133088 ps |
| T849 |
/workspace/coverage/default/13.lc_ctrl_state_post_trans.1171020680 |
|
|
Apr 28 04:52:05 PM PDT 24 |
Apr 28 04:52:09 PM PDT 24 |
87005135 ps |
| T850 |
/workspace/coverage/default/35.lc_ctrl_security_escalation.340528991 |
|
|
Apr 28 04:53:34 PM PDT 24 |
Apr 28 04:53:43 PM PDT 24 |
311011824 ps |
| T851 |
/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2996770119 |
|
|
Apr 28 04:52:53 PM PDT 24 |
Apr 28 04:52:56 PM PDT 24 |
30432993 ps |
| T852 |
/workspace/coverage/default/37.lc_ctrl_sec_token_mux.3871564164 |
|
|
Apr 28 04:53:33 PM PDT 24 |
Apr 28 04:53:43 PM PDT 24 |
211315349 ps |
| T853 |
/workspace/coverage/default/29.lc_ctrl_alert_test.1217833383 |
|
|
Apr 28 04:53:07 PM PDT 24 |
Apr 28 04:53:09 PM PDT 24 |
117926516 ps |
| T854 |
/workspace/coverage/default/18.lc_ctrl_sec_mubi.1454234120 |
|
|
Apr 28 04:52:30 PM PDT 24 |
Apr 28 04:52:43 PM PDT 24 |
232909399 ps |
| T855 |
/workspace/coverage/default/33.lc_ctrl_errors.2136913755 |
|
|
Apr 28 04:53:23 PM PDT 24 |
Apr 28 04:53:34 PM PDT 24 |
999352704 ps |
| T856 |
/workspace/coverage/default/27.lc_ctrl_sec_token_digest.1254659875 |
|
|
Apr 28 04:53:01 PM PDT 24 |
Apr 28 04:53:15 PM PDT 24 |
337930491 ps |
| T857 |
/workspace/coverage/default/33.lc_ctrl_state_post_trans.2914473278 |
|
|
Apr 28 04:53:20 PM PDT 24 |
Apr 28 04:53:28 PM PDT 24 |
661407618 ps |
| T858 |
/workspace/coverage/default/14.lc_ctrl_stress_all.1330069057 |
|
|
Apr 28 04:52:11 PM PDT 24 |
Apr 28 04:53:03 PM PDT 24 |
3436619600 ps |
| T859 |
/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3197878662 |
|
|
Apr 28 04:52:36 PM PDT 24 |
Apr 28 04:53:21 PM PDT 24 |
6700051015 ps |
| T860 |
/workspace/coverage/default/10.lc_ctrl_state_post_trans.3741213136 |
|
|
Apr 28 04:51:46 PM PDT 24 |
Apr 28 04:51:51 PM PDT 24 |
269885889 ps |
| T861 |
/workspace/coverage/default/1.lc_ctrl_stress_all.1092283034 |
|
|
Apr 28 04:50:36 PM PDT 24 |
Apr 28 04:52:45 PM PDT 24 |
4448903003 ps |
| T862 |
/workspace/coverage/default/19.lc_ctrl_jtag_access.4179028913 |
|
|
Apr 28 04:52:35 PM PDT 24 |
Apr 28 04:52:51 PM PDT 24 |
686864012 ps |
| T863 |
/workspace/coverage/default/45.lc_ctrl_sec_mubi.2371298279 |
|
|
Apr 28 04:54:12 PM PDT 24 |
Apr 28 04:54:23 PM PDT 24 |
224107668 ps |
| T864 |
/workspace/coverage/default/43.lc_ctrl_stress_all.1524759984 |
|
|
Apr 28 04:53:55 PM PDT 24 |
Apr 28 04:55:53 PM PDT 24 |
4905387474 ps |
| T865 |
/workspace/coverage/default/17.lc_ctrl_state_failure.3111446835 |
|
|
Apr 28 04:52:22 PM PDT 24 |
Apr 28 04:52:49 PM PDT 24 |
193110272 ps |
| T866 |
/workspace/coverage/default/40.lc_ctrl_errors.3284753463 |
|
|
Apr 28 04:53:43 PM PDT 24 |
Apr 28 04:53:57 PM PDT 24 |
3304261068 ps |
| T867 |
/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2468882998 |
|
|
Apr 28 04:52:09 PM PDT 24 |
Apr 28 04:52:46 PM PDT 24 |
4605879643 ps |
| T868 |
/workspace/coverage/default/33.lc_ctrl_sec_token_mux.4046425017 |
|
|
Apr 28 04:53:21 PM PDT 24 |
Apr 28 04:53:33 PM PDT 24 |
6414279586 ps |
| T869 |
/workspace/coverage/default/8.lc_ctrl_sec_token_digest.2700890741 |
|
|
Apr 28 04:51:39 PM PDT 24 |
Apr 28 04:51:53 PM PDT 24 |
305442468 ps |
| T870 |
/workspace/coverage/default/19.lc_ctrl_security_escalation.2002771555 |
|
|
Apr 28 04:52:30 PM PDT 24 |
Apr 28 04:52:44 PM PDT 24 |
888930513 ps |
| T103 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3616574509 |
|
|
Apr 28 03:18:27 PM PDT 24 |
Apr 28 03:18:31 PM PDT 24 |
109872314 ps |
| T113 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3006187710 |
|
|
Apr 28 03:17:56 PM PDT 24 |
Apr 28 03:17:58 PM PDT 24 |
223541903 ps |
| T132 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3560011369 |
|
|
Apr 28 03:18:27 PM PDT 24 |
Apr 28 03:18:29 PM PDT 24 |
59513441 ps |
| T104 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1907256492 |
|
|
Apr 28 03:18:38 PM PDT 24 |
Apr 28 03:18:40 PM PDT 24 |
105087387 ps |
| T109 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.291999287 |
|
|
Apr 28 03:18:49 PM PDT 24 |
Apr 28 03:18:50 PM PDT 24 |
75177980 ps |
| T105 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.234890589 |
|
|
Apr 28 03:18:46 PM PDT 24 |
Apr 28 03:18:50 PM PDT 24 |
110276540 ps |
| T149 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.915801340 |
|
|
Apr 28 03:18:42 PM PDT 24 |
Apr 28 03:18:43 PM PDT 24 |
82778246 ps |
| T108 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2110129519 |
|
|
Apr 28 03:18:24 PM PDT 24 |
Apr 28 03:18:28 PM PDT 24 |
103403952 ps |
| T110 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2933343044 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:24 PM PDT 24 |
47693680 ps |
| T129 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.175708813 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:27 PM PDT 24 |
121877414 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1684821011 |
|
|
Apr 28 03:18:02 PM PDT 24 |
Apr 28 03:18:07 PM PDT 24 |
291596973 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3246515439 |
|
|
Apr 28 03:18:19 PM PDT 24 |
Apr 28 03:18:22 PM PDT 24 |
158225173 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1515816682 |
|
|
Apr 28 03:18:46 PM PDT 24 |
Apr 28 03:18:49 PM PDT 24 |
199721930 ps |
| T144 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1375220658 |
|
|
Apr 28 03:18:36 PM PDT 24 |
Apr 28 03:18:38 PM PDT 24 |
38531615 ps |
| T130 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.752606451 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:34 PM PDT 24 |
127252262 ps |
| T111 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3208207567 |
|
|
Apr 28 03:17:52 PM PDT 24 |
Apr 28 03:17:55 PM PDT 24 |
96975422 ps |
| T157 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2203999585 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:45 PM PDT 24 |
80820318 ps |
| T127 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1455153338 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:46 PM PDT 24 |
63494749 ps |
| T117 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.536363154 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:37 PM PDT 24 |
185601504 ps |
| T871 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1975283813 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:40 PM PDT 24 |
7621455820 ps |
| T872 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3660080564 |
|
|
Apr 28 03:18:02 PM PDT 24 |
Apr 28 03:18:06 PM PDT 24 |
477220405 ps |
| T873 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.999610165 |
|
|
Apr 28 03:18:29 PM PDT 24 |
Apr 28 03:18:31 PM PDT 24 |
127033773 ps |
| T874 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2429786423 |
|
|
Apr 28 03:18:01 PM PDT 24 |
Apr 28 03:18:03 PM PDT 24 |
16693389 ps |
| T119 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2519321082 |
|
|
Apr 28 03:18:08 PM PDT 24 |
Apr 28 03:18:10 PM PDT 24 |
40691040 ps |
| T158 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1656840748 |
|
|
Apr 28 03:18:10 PM PDT 24 |
Apr 28 03:18:16 PM PDT 24 |
1570759129 ps |
| T174 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2354026131 |
|
|
Apr 28 03:17:52 PM PDT 24 |
Apr 28 03:17:54 PM PDT 24 |
38150542 ps |
| T875 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.157304866 |
|
|
Apr 28 03:18:02 PM PDT 24 |
Apr 28 03:18:50 PM PDT 24 |
8678682039 ps |
| T876 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.829422705 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:35 PM PDT 24 |
1902199283 ps |
| T175 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2510157665 |
|
|
Apr 28 03:18:50 PM PDT 24 |
Apr 28 03:18:51 PM PDT 24 |
11882862 ps |
| T877 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1267057192 |
|
|
Apr 28 03:17:52 PM PDT 24 |
Apr 28 03:17:54 PM PDT 24 |
41773223 ps |
| T159 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3796235544 |
|
|
Apr 28 03:18:14 PM PDT 24 |
Apr 28 03:18:16 PM PDT 24 |
89296498 ps |
| T878 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.706498603 |
|
|
Apr 28 03:18:47 PM PDT 24 |
Apr 28 03:18:49 PM PDT 24 |
78402519 ps |
| T879 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3683374388 |
|
|
Apr 28 03:17:56 PM PDT 24 |
Apr 28 03:17:58 PM PDT 24 |
339018408 ps |
| T184 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1216458980 |
|
|
Apr 28 03:18:44 PM PDT 24 |
Apr 28 03:18:46 PM PDT 24 |
27734274 ps |
| T880 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.7477833 |
|
|
Apr 28 03:17:46 PM PDT 24 |
Apr 28 03:17:50 PM PDT 24 |
317231307 ps |
| T145 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3280735731 |
|
|
Apr 28 03:18:40 PM PDT 24 |
Apr 28 03:18:42 PM PDT 24 |
287307320 ps |
| T185 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2149594568 |
|
|
Apr 28 03:18:39 PM PDT 24 |
Apr 28 03:18:41 PM PDT 24 |
20590180 ps |
| T186 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.146489563 |
|
|
Apr 28 03:18:28 PM PDT 24 |
Apr 28 03:18:29 PM PDT 24 |
36393438 ps |
| T881 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2696405783 |
|
|
Apr 28 03:18:38 PM PDT 24 |
Apr 28 03:18:40 PM PDT 24 |
49877446 ps |
| T112 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2445497248 |
|
|
Apr 28 03:18:16 PM PDT 24 |
Apr 28 03:18:18 PM PDT 24 |
73405432 ps |
| T882 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.729928016 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:35 PM PDT 24 |
268687304 ps |
| T187 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3424243011 |
|
|
Apr 28 03:18:10 PM PDT 24 |
Apr 28 03:18:13 PM PDT 24 |
38653522 ps |
| T883 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3860867637 |
|
|
Apr 28 03:18:45 PM PDT 24 |
Apr 28 03:18:48 PM PDT 24 |
107982498 ps |
| T884 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2229386078 |
|
|
Apr 28 03:17:50 PM PDT 24 |
Apr 28 03:17:52 PM PDT 24 |
295130643 ps |
| T885 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3751473299 |
|
|
Apr 28 03:18:27 PM PDT 24 |
Apr 28 03:18:31 PM PDT 24 |
100392593 ps |
| T886 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4068751600 |
|
|
Apr 28 03:17:56 PM PDT 24 |
Apr 28 03:17:58 PM PDT 24 |
221332911 ps |
| T887 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4007458172 |
|
|
Apr 28 03:18:08 PM PDT 24 |
Apr 28 03:18:13 PM PDT 24 |
893688662 ps |
| T888 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3130269282 |
|
|
Apr 28 03:18:18 PM PDT 24 |
Apr 28 03:18:19 PM PDT 24 |
14086071 ps |
| T188 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2542092294 |
|
|
Apr 28 03:18:35 PM PDT 24 |
Apr 28 03:18:37 PM PDT 24 |
25065067 ps |
| T189 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2986316981 |
|
|
Apr 28 03:18:28 PM PDT 24 |
Apr 28 03:18:30 PM PDT 24 |
81833795 ps |
| T125 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2677226775 |
|
|
Apr 28 03:18:41 PM PDT 24 |
Apr 28 03:18:45 PM PDT 24 |
173221456 ps |
| T146 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3464384622 |
|
|
Apr 28 03:18:02 PM PDT 24 |
Apr 28 03:18:04 PM PDT 24 |
35741486 ps |
| T889 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.204157935 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:35 PM PDT 24 |
154884977 ps |
| T190 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3624506672 |
|
|
Apr 28 03:18:37 PM PDT 24 |
Apr 28 03:18:39 PM PDT 24 |
25147185 ps |
| T890 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3739716744 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:34 PM PDT 24 |
69679125 ps |
| T891 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1505007117 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:34 PM PDT 24 |
31462440 ps |
| T892 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1288198642 |
|
|
Apr 28 03:18:42 PM PDT 24 |
Apr 28 03:18:44 PM PDT 24 |
36152551 ps |
| T893 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3935339446 |
|
|
Apr 28 03:17:57 PM PDT 24 |
Apr 28 03:18:13 PM PDT 24 |
2685415697 ps |
| T176 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.216613920 |
|
|
Apr 28 03:18:09 PM PDT 24 |
Apr 28 03:18:11 PM PDT 24 |
15832194 ps |
| T894 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2780536195 |
|
|
Apr 28 03:18:48 PM PDT 24 |
Apr 28 03:18:52 PM PDT 24 |
95173149 ps |
| T895 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2785660266 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:36 PM PDT 24 |
93626185 ps |
| T896 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3910284410 |
|
|
Apr 28 03:18:46 PM PDT 24 |
Apr 28 03:18:48 PM PDT 24 |
236057935 ps |
| T897 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1073358417 |
|
|
Apr 28 03:18:08 PM PDT 24 |
Apr 28 03:18:10 PM PDT 24 |
22631970 ps |
| T898 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2390883365 |
|
|
Apr 28 03:18:39 PM PDT 24 |
Apr 28 03:18:41 PM PDT 24 |
224217992 ps |
| T899 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.364129212 |
|
|
Apr 28 03:17:51 PM PDT 24 |
Apr 28 03:17:57 PM PDT 24 |
501232748 ps |
| T147 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3105703613 |
|
|
Apr 28 03:18:03 PM PDT 24 |
Apr 28 03:18:07 PM PDT 24 |
216756061 ps |
| T900 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3067707799 |
|
|
Apr 28 03:18:25 PM PDT 24 |
Apr 28 03:18:28 PM PDT 24 |
1016256452 ps |
| T901 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2406005967 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:55 PM PDT 24 |
3877137272 ps |
| T902 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.974649201 |
|
|
Apr 28 03:18:14 PM PDT 24 |
Apr 28 03:18:17 PM PDT 24 |
227734217 ps |
| T903 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2585226579 |
|
|
Apr 28 03:18:09 PM PDT 24 |
Apr 28 03:18:10 PM PDT 24 |
31165559 ps |
| T904 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.731405077 |
|
|
Apr 28 03:18:21 PM PDT 24 |
Apr 28 03:18:23 PM PDT 24 |
28392738 ps |
| T905 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4095167444 |
|
|
Apr 28 03:18:18 PM PDT 24 |
Apr 28 03:18:25 PM PDT 24 |
3926481873 ps |
| T906 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3916622681 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:45 PM PDT 24 |
97284967 ps |
| T907 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1960928281 |
|
|
Apr 28 03:18:04 PM PDT 24 |
Apr 28 03:18:05 PM PDT 24 |
133045211 ps |
| T908 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3725165573 |
|
|
Apr 28 03:18:49 PM PDT 24 |
Apr 28 03:18:50 PM PDT 24 |
38755340 ps |
| T909 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4256500083 |
|
|
Apr 28 03:18:28 PM PDT 24 |
Apr 28 03:18:32 PM PDT 24 |
256115865 ps |
| T910 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3082406960 |
|
|
Apr 28 03:18:24 PM PDT 24 |
Apr 28 03:18:26 PM PDT 24 |
54657597 ps |
| T911 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1590925934 |
|
|
Apr 28 03:18:41 PM PDT 24 |
Apr 28 03:18:42 PM PDT 24 |
22387279 ps |
| T912 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2896292394 |
|
|
Apr 28 03:17:47 PM PDT 24 |
Apr 28 03:17:49 PM PDT 24 |
69224449 ps |
| T913 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3498119715 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:44 PM PDT 24 |
14117953 ps |
| T124 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3526267393 |
|
|
Apr 28 03:18:41 PM PDT 24 |
Apr 28 03:18:46 PM PDT 24 |
75812026 ps |
| T914 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1746023605 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:37 PM PDT 24 |
78406593 ps |
| T915 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.468618656 |
|
|
Apr 28 03:18:42 PM PDT 24 |
Apr 28 03:18:44 PM PDT 24 |
54374596 ps |
| T916 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3478467575 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:25 PM PDT 24 |
61468985 ps |
| T917 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.337076857 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:34 PM PDT 24 |
138831575 ps |
| T918 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2596681749 |
|
|
Apr 28 03:18:17 PM PDT 24 |
Apr 28 03:18:19 PM PDT 24 |
24233801 ps |
| T177 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3736871607 |
|
|
Apr 28 03:18:27 PM PDT 24 |
Apr 28 03:18:28 PM PDT 24 |
18107437 ps |
| T919 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1795289280 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:45 PM PDT 24 |
41758633 ps |
| T920 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3897991934 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:35 PM PDT 24 |
156782197 ps |
| T921 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1313698329 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:46 PM PDT 24 |
4884279066 ps |
| T922 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.549939192 |
|
|
Apr 28 03:18:13 PM PDT 24 |
Apr 28 03:18:15 PM PDT 24 |
78476020 ps |
| T923 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.349933814 |
|
|
Apr 28 03:18:30 PM PDT 24 |
Apr 28 03:18:35 PM PDT 24 |
399648870 ps |
| T924 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4173734356 |
|
|
Apr 28 03:18:29 PM PDT 24 |
Apr 28 03:18:31 PM PDT 24 |
230498287 ps |
| T925 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2860737113 |
|
|
Apr 28 03:18:09 PM PDT 24 |
Apr 28 03:18:11 PM PDT 24 |
211064558 ps |
| T126 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.354175893 |
|
|
Apr 28 03:18:46 PM PDT 24 |
Apr 28 03:18:50 PM PDT 24 |
447586564 ps |
| T926 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2342325658 |
|
|
Apr 28 03:18:51 PM PDT 24 |
Apr 28 03:18:53 PM PDT 24 |
54269619 ps |
| T927 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4276296743 |
|
|
Apr 28 03:18:19 PM PDT 24 |
Apr 28 03:18:22 PM PDT 24 |
171173937 ps |
| T178 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1622213221 |
|
|
Apr 28 03:18:41 PM PDT 24 |
Apr 28 03:18:43 PM PDT 24 |
15345410 ps |
| T928 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3733760830 |
|
|
Apr 28 03:18:38 PM PDT 24 |
Apr 28 03:18:40 PM PDT 24 |
21951809 ps |
| T929 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2425414566 |
|
|
Apr 28 03:18:40 PM PDT 24 |
Apr 28 03:18:42 PM PDT 24 |
127758854 ps |
| T930 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3577862289 |
|
|
Apr 28 03:18:13 PM PDT 24 |
Apr 28 03:18:16 PM PDT 24 |
131287036 ps |
| T931 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1442422832 |
|
|
Apr 28 03:18:13 PM PDT 24 |
Apr 28 03:18:16 PM PDT 24 |
975412084 ps |
| T932 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2055849025 |
|
|
Apr 28 03:17:51 PM PDT 24 |
Apr 28 03:17:53 PM PDT 24 |
14251584 ps |
| T933 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.74285626 |
|
|
Apr 28 03:18:50 PM PDT 24 |
Apr 28 03:18:52 PM PDT 24 |
49008005 ps |
| T934 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2123308393 |
|
|
Apr 28 03:18:42 PM PDT 24 |
Apr 28 03:18:43 PM PDT 24 |
166156156 ps |
| T935 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1011988650 |
|
|
Apr 28 03:18:20 PM PDT 24 |
Apr 28 03:18:21 PM PDT 24 |
14278949 ps |
| T183 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1619405945 |
|
|
Apr 28 03:18:08 PM PDT 24 |
Apr 28 03:18:10 PM PDT 24 |
49274774 ps |
| T936 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1649499978 |
|
|
Apr 28 03:17:52 PM PDT 24 |
Apr 28 03:17:57 PM PDT 24 |
132910290 ps |
| T937 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4167281113 |
|
|
Apr 28 03:18:19 PM PDT 24 |
Apr 28 03:18:21 PM PDT 24 |
174122522 ps |
| T938 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3773187927 |
|
|
Apr 28 03:18:46 PM PDT 24 |
Apr 28 03:18:48 PM PDT 24 |
58025610 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3732441470 |
|
|
Apr 28 03:17:57 PM PDT 24 |
Apr 28 03:18:01 PM PDT 24 |
185953627 ps |
| T940 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3139798552 |
|
|
Apr 28 03:18:18 PM PDT 24 |
Apr 28 03:18:20 PM PDT 24 |
132322161 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2829762956 |
|
|
Apr 28 03:18:18 PM PDT 24 |
Apr 28 03:18:21 PM PDT 24 |
678121237 ps |
| T942 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.988642772 |
|
|
Apr 28 03:18:29 PM PDT 24 |
Apr 28 03:18:31 PM PDT 24 |
85201115 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.918186224 |
|
|
Apr 28 03:18:35 PM PDT 24 |
Apr 28 03:18:37 PM PDT 24 |
25754813 ps |
| T179 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3406982808 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:34 PM PDT 24 |
56453002 ps |
| T944 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2694935055 |
|
|
Apr 28 03:17:58 PM PDT 24 |
Apr 28 03:18:01 PM PDT 24 |
98053613 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3095622532 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:25 PM PDT 24 |
26356008 ps |
| T180 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3769077088 |
|
|
Apr 28 03:18:03 PM PDT 24 |
Apr 28 03:18:05 PM PDT 24 |
24155596 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3733322476 |
|
|
Apr 28 03:18:46 PM PDT 24 |
Apr 28 03:18:48 PM PDT 24 |
44078037 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.862573240 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:34 PM PDT 24 |
53128371 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1564226295 |
|
|
Apr 28 03:18:08 PM PDT 24 |
Apr 28 03:18:11 PM PDT 24 |
185038175 ps |
| T949 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3567809928 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:46 PM PDT 24 |
37215246 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.145253649 |
|
|
Apr 28 03:18:09 PM PDT 24 |
Apr 28 03:18:11 PM PDT 24 |
22265328 ps |
| T951 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3613030132 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:36 PM PDT 24 |
108690803 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1766736398 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:35 PM PDT 24 |
38457930 ps |
| T953 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4163428217 |
|
|
Apr 28 03:18:25 PM PDT 24 |
Apr 28 03:18:28 PM PDT 24 |
44766855 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.123560374 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:36 PM PDT 24 |
1155430199 ps |
| T116 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.999516894 |
|
|
Apr 28 03:18:40 PM PDT 24 |
Apr 28 03:18:46 PM PDT 24 |
1112271079 ps |
| T954 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2338465353 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:40 PM PDT 24 |
876640268 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2459901519 |
|
|
Apr 28 03:18:19 PM PDT 24 |
Apr 28 03:18:21 PM PDT 24 |
50177757 ps |
| T181 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1628379165 |
|
|
Apr 28 03:18:37 PM PDT 24 |
Apr 28 03:18:39 PM PDT 24 |
32105241 ps |
| T182 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2739696809 |
|
|
Apr 28 03:18:15 PM PDT 24 |
Apr 28 03:18:16 PM PDT 24 |
12382398 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4160104575 |
|
|
Apr 28 03:17:57 PM PDT 24 |
Apr 28 03:17:59 PM PDT 24 |
44788833 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3398585852 |
|
|
Apr 28 03:17:56 PM PDT 24 |
Apr 28 03:17:58 PM PDT 24 |
46572885 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3226608685 |
|
|
Apr 28 03:18:03 PM PDT 24 |
Apr 28 03:18:05 PM PDT 24 |
15328334 ps |
| T959 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4058035155 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:39 PM PDT 24 |
1644361870 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.339442570 |
|
|
Apr 28 03:18:19 PM PDT 24 |
Apr 28 03:19:10 PM PDT 24 |
2402263890 ps |
| T120 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.706195500 |
|
|
Apr 28 03:18:19 PM PDT 24 |
Apr 28 03:18:22 PM PDT 24 |
158412707 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3870814506 |
|
|
Apr 28 03:17:48 PM PDT 24 |
Apr 28 03:17:57 PM PDT 24 |
3326126971 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3737653284 |
|
|
Apr 28 03:18:44 PM PDT 24 |
Apr 28 03:18:48 PM PDT 24 |
305017886 ps |
| T118 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2936103827 |
|
|
Apr 28 03:17:52 PM PDT 24 |
Apr 28 03:17:56 PM PDT 24 |
105464145 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1153548878 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:34 PM PDT 24 |
205978650 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.573674531 |
|
|
Apr 28 03:18:27 PM PDT 24 |
Apr 28 03:18:29 PM PDT 24 |
23450189 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4046648018 |
|
|
Apr 28 03:18:39 PM PDT 24 |
Apr 28 03:18:41 PM PDT 24 |
181088996 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.954907567 |
|
|
Apr 28 03:18:08 PM PDT 24 |
Apr 28 03:18:10 PM PDT 24 |
94703023 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2592883751 |
|
|
Apr 28 03:18:26 PM PDT 24 |
Apr 28 03:18:28 PM PDT 24 |
374264858 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3178133056 |
|
|
Apr 28 03:18:14 PM PDT 24 |
Apr 28 03:18:17 PM PDT 24 |
89015132 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3226707001 |
|
|
Apr 28 03:18:37 PM PDT 24 |
Apr 28 03:18:40 PM PDT 24 |
201721717 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1651507158 |
|
|
Apr 28 03:17:57 PM PDT 24 |
Apr 28 03:17:59 PM PDT 24 |
632698681 ps |
| T971 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3835440957 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:25 PM PDT 24 |
196996921 ps |
| T121 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.653882839 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:36 PM PDT 24 |
141068922 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2272872875 |
|
|
Apr 28 03:18:26 PM PDT 24 |
Apr 28 03:18:27 PM PDT 24 |
95062565 ps |
| T973 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3151489385 |
|
|
Apr 28 03:18:09 PM PDT 24 |
Apr 28 03:18:14 PM PDT 24 |
227081548 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1229216086 |
|
|
Apr 28 03:18:10 PM PDT 24 |
Apr 28 03:18:12 PM PDT 24 |
82278053 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2247891175 |
|
|
Apr 28 03:18:10 PM PDT 24 |
Apr 28 03:18:12 PM PDT 24 |
31858558 ps |
| T976 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.126873052 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:45 PM PDT 24 |
76767484 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1239072459 |
|
|
Apr 28 03:18:47 PM PDT 24 |
Apr 28 03:18:49 PM PDT 24 |
33540383 ps |
| T122 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1794272285 |
|
|
Apr 28 03:18:47 PM PDT 24 |
Apr 28 03:18:50 PM PDT 24 |
592280223 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1038534698 |
|
|
Apr 28 03:17:53 PM PDT 24 |
Apr 28 03:17:54 PM PDT 24 |
23119365 ps |
| T979 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2717324191 |
|
|
Apr 28 03:18:43 PM PDT 24 |
Apr 28 03:18:46 PM PDT 24 |
47668636 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2219481354 |
|
|
Apr 28 03:18:39 PM PDT 24 |
Apr 28 03:18:40 PM PDT 24 |
47990726 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3278010039 |
|
|
Apr 28 03:18:21 PM PDT 24 |
Apr 28 03:18:36 PM PDT 24 |
5757003558 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1656591654 |
|
|
Apr 28 03:18:48 PM PDT 24 |
Apr 28 03:18:50 PM PDT 24 |
68244811 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2267044160 |
|
|
Apr 28 03:18:09 PM PDT 24 |
Apr 28 03:18:10 PM PDT 24 |
41212969 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1288250626 |
|
|
Apr 28 03:18:08 PM PDT 24 |
Apr 28 03:18:32 PM PDT 24 |
2658688632 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3497852611 |
|
|
Apr 28 03:18:20 PM PDT 24 |
Apr 28 03:18:22 PM PDT 24 |
172584115 ps |
| T986 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4204515868 |
|
|
Apr 28 03:18:41 PM PDT 24 |
Apr 28 03:18:42 PM PDT 24 |
38291423 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.136344336 |
|
|
Apr 28 03:18:47 PM PDT 24 |
Apr 28 03:18:49 PM PDT 24 |
40612978 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2788142399 |
|
|
Apr 28 03:17:51 PM PDT 24 |
Apr 28 03:17:53 PM PDT 24 |
93547766 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2187410826 |
|
|
Apr 28 03:18:26 PM PDT 24 |
Apr 28 03:18:27 PM PDT 24 |
12823753 ps |
| T990 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.884476427 |
|
|
Apr 28 03:18:32 PM PDT 24 |
Apr 28 03:18:36 PM PDT 24 |
88072079 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.859210848 |
|
|
Apr 28 03:18:20 PM PDT 24 |
Apr 28 03:18:22 PM PDT 24 |
50452174 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2381972224 |
|
|
Apr 28 03:18:29 PM PDT 24 |
Apr 28 03:18:33 PM PDT 24 |
1784736739 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1005243768 |
|
|
Apr 28 03:18:02 PM PDT 24 |
Apr 28 03:18:05 PM PDT 24 |
188211003 ps |
| T994 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4109826521 |
|
|
Apr 28 03:18:14 PM PDT 24 |
Apr 28 03:18:16 PM PDT 24 |
17393074 ps |
| T995 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4028915397 |
|
|
Apr 28 03:18:27 PM PDT 24 |
Apr 28 03:18:33 PM PDT 24 |
190633108 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3718567795 |
|
|
Apr 28 03:18:39 PM PDT 24 |
Apr 28 03:18:41 PM PDT 24 |
24469716 ps |
| T997 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.388926123 |
|
|
Apr 28 03:18:28 PM PDT 24 |
Apr 28 03:18:30 PM PDT 24 |
25815563 ps |
| T123 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2368583360 |
|
|
Apr 28 03:18:23 PM PDT 24 |
Apr 28 03:18:27 PM PDT 24 |
162765404 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2109375867 |
|
|
Apr 28 03:18:02 PM PDT 24 |
Apr 28 03:18:05 PM PDT 24 |
625676577 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2821544284 |
|
|
Apr 28 03:18:33 PM PDT 24 |
Apr 28 03:18:43 PM PDT 24 |
1446175408 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2846157139 |
|
|
Apr 28 03:18:14 PM PDT 24 |
Apr 28 03:18:17 PM PDT 24 |
96958005 ps |