Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53336 |
1 |
|
|
T1 |
58 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
1842 |
1 |
|
|
T1 |
10 |
|
T17 |
3 |
|
T18 |
10 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54419 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
759 |
1 |
|
|
T13 |
26 |
|
T61 |
12 |
|
T62 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53263 |
1 |
|
|
T1 |
68 |
|
T2 |
174 |
|
T3 |
8 |
auto[1] |
1915 |
1 |
|
|
T2 |
25 |
|
T15 |
5 |
|
T25 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53213 |
1 |
|
|
T1 |
68 |
|
T2 |
178 |
|
T3 |
8 |
auto[1] |
1965 |
1 |
|
|
T2 |
21 |
|
T15 |
10 |
|
T25 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53228 |
1 |
|
|
T1 |
68 |
|
T2 |
179 |
|
T3 |
8 |
auto[1] |
1950 |
1 |
|
|
T2 |
20 |
|
T15 |
7 |
|
T25 |
3 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50052 |
1 |
|
|
T1 |
68 |
|
T2 |
181 |
|
T3 |
8 |
no_err_inj |
5126 |
1 |
|
|
T2 |
18 |
|
T25 |
1 |
|
T4 |
13 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53286 |
1 |
|
|
T1 |
62 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
1892 |
1 |
|
|
T1 |
6 |
|
T17 |
8 |
|
T18 |
10 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54466 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
712 |
1 |
|
|
T13 |
16 |
|
T61 |
14 |
|
T62 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38241 |
1 |
|
|
T2 |
26 |
|
T3 |
8 |
|
T10 |
99 |
auto[1] |
16937 |
1 |
|
|
T1 |
68 |
|
T2 |
173 |
|
T4 |
13 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53223 |
1 |
|
|
T1 |
68 |
|
T2 |
178 |
|
T3 |
8 |
auto[1] |
1955 |
1 |
|
|
T2 |
21 |
|
T15 |
5 |
|
T25 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53270 |
1 |
|
|
T1 |
68 |
|
T2 |
187 |
|
T3 |
8 |
auto[1] |
1908 |
1 |
|
|
T2 |
12 |
|
T15 |
8 |
|
T25 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53152 |
1 |
|
|
T1 |
68 |
|
T2 |
182 |
|
T3 |
8 |
auto[1] |
2026 |
1 |
|
|
T2 |
17 |
|
T15 |
8 |
|
T23 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53297 |
1 |
|
|
T1 |
56 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
1881 |
1 |
|
|
T1 |
12 |
|
T17 |
4 |
|
T18 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52803 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T10 |
99 |
auto[1] |
2375 |
1 |
|
|
T3 |
8 |
|
T21 |
4 |
|
T59 |
15 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54422 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
756 |
1 |
|
|
T13 |
16 |
|
T61 |
9 |
|
T62 |
16 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54428 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
750 |
1 |
|
|
T13 |
21 |
|
T61 |
12 |
|
T62 |
13 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54437 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
741 |
1 |
|
|
T13 |
19 |
|
T61 |
10 |
|
T62 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52426 |
1 |
|
|
T1 |
68 |
|
T2 |
173 |
|
T3 |
8 |
auto[1] |
2752 |
1 |
|
|
T2 |
26 |
|
T25 |
14 |
|
T23 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51549 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
3629 |
1 |
|
|
T14 |
50 |
|
T50 |
76 |
|
T48 |
81 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53134 |
1 |
|
|
T1 |
68 |
|
T2 |
178 |
|
T3 |
8 |
auto[1] |
2044 |
1 |
|
|
T2 |
21 |
|
T15 |
12 |
|
T23 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53184 |
1 |
|
|
T1 |
68 |
|
T2 |
176 |
|
T3 |
8 |
auto[1] |
1994 |
1 |
|
|
T2 |
23 |
|
T15 |
8 |
|
T25 |
2 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53156 |
1 |
|
|
T1 |
68 |
|
T2 |
178 |
|
T3 |
8 |
auto[1] |
2022 |
1 |
|
|
T2 |
21 |
|
T15 |
3 |
|
T25 |
3 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53319 |
1 |
|
|
T1 |
56 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
1859 |
1 |
|
|
T1 |
12 |
|
T17 |
4 |
|
T18 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49539 |
1 |
|
|
T1 |
61 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
5639 |
1 |
|
|
T1 |
7 |
|
T10 |
99 |
|
T16 |
57 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51362 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
3816 |
1 |
|
|
T11 |
82 |
|
T39 |
50 |
|
T60 |
62 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55178 |
1 |
|
|
T1 |
68 |
|
T2 |
199 |
|
T3 |
8 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53317 |
1 |
|
|
T1 |
62 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
1861 |
1 |
|
|
T1 |
6 |
|
T17 |
9 |
|
T18 |
12 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53274 |
1 |
|
|
T1 |
61 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
1904 |
1 |
|
|
T1 |
7 |
|
T17 |
7 |
|
T18 |
13 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53321 |
1 |
|
|
T1 |
60 |
|
T2 |
199 |
|
T3 |
8 |
auto[1] |
1857 |
1 |
|
|
T1 |
8 |
|
T17 |
5 |
|
T18 |
11 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48680 |
1 |
|
|
T1 |
68 |
|
T2 |
167 |
|
T3 |
8 |
auto[0] |
no_err_inj |
3746 |
1 |
|
|
T2 |
6 |
|
T4 |
13 |
|
T23 |
19 |
auto[1] |
err_inj |
1372 |
1 |
|
|
T2 |
14 |
|
T25 |
13 |
|
T23 |
7 |
auto[1] |
no_err_inj |
1380 |
1 |
|
|
T2 |
12 |
|
T25 |
1 |
|
T23 |
3 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50596 |
1 |
|
|
T1 |
68 |
|
T2 |
151 |
|
T3 |
8 |
auto[0] |
auto[1] |
1830 |
1 |
|
|
T2 |
22 |
|
T15 |
8 |
|
T23 |
14 |
auto[1] |
auto[0] |
2588 |
1 |
|
|
T2 |
25 |
|
T25 |
12 |
|
T23 |
10 |
auto[1] |
auto[1] |
164 |
1 |
|
|
T2 |
1 |
|
T25 |
2 |
|
T83 |
7 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50671 |
1 |
|
|
T1 |
68 |
|
T2 |
162 |
|
T3 |
8 |
auto[0] |
auto[1] |
1755 |
1 |
|
|
T2 |
11 |
|
T15 |
8 |
|
T23 |
10 |
auto[1] |
auto[0] |
2599 |
1 |
|
|
T2 |
25 |
|
T25 |
12 |
|
T23 |
10 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T2 |
1 |
|
T25 |
2 |
|
T21 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50566 |
1 |
|
|
T1 |
68 |
|
T2 |
154 |
|
T3 |
8 |
auto[0] |
auto[1] |
1860 |
1 |
|
|
T2 |
19 |
|
T15 |
3 |
|
T23 |
11 |
auto[1] |
auto[0] |
2590 |
1 |
|
|
T2 |
24 |
|
T25 |
11 |
|
T23 |
6 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T2 |
2 |
|
T25 |
3 |
|
T23 |
4 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50612 |
1 |
|
|
T1 |
68 |
|
T2 |
154 |
|
T3 |
8 |
auto[0] |
auto[1] |
1814 |
1 |
|
|
T2 |
19 |
|
T15 |
10 |
|
T23 |
8 |
auto[1] |
auto[0] |
2601 |
1 |
|
|
T2 |
24 |
|
T25 |
13 |
|
T23 |
10 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T2 |
2 |
|
T25 |
1 |
|
T84 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50615 |
1 |
|
|
T1 |
68 |
|
T2 |
157 |
|
T3 |
8 |
auto[0] |
auto[1] |
1811 |
1 |
|
|
T2 |
16 |
|
T15 |
7 |
|
T23 |
10 |
auto[1] |
auto[0] |
2613 |
1 |
|
|
T2 |
22 |
|
T25 |
11 |
|
T23 |
10 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T2 |
4 |
|
T25 |
3 |
|
T21 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50666 |
1 |
|
|
T1 |
68 |
|
T2 |
149 |
|
T3 |
8 |
auto[0] |
auto[1] |
1760 |
1 |
|
|
T2 |
24 |
|
T15 |
5 |
|
T23 |
9 |
auto[1] |
auto[0] |
2597 |
1 |
|
|
T2 |
25 |
|
T25 |
13 |
|
T23 |
9 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T2 |
1 |
|
T25 |
1 |
|
T23 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37169 |
1 |
|
|
T2 |
26 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1072 |
1 |
|
|
T17 |
3 |
|
T18 |
10 |
|
T41 |
10 |
auto[1] |
auto[0] |
16167 |
1 |
|
|
T1 |
58 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
770 |
1 |
|
|
T1 |
10 |
|
T40 |
9 |
|
T83 |
4 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37038 |
1 |
|
|
T2 |
26 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1203 |
1 |
|
|
T17 |
8 |
|
T18 |
10 |
|
T41 |
6 |
auto[1] |
auto[0] |
16248 |
1 |
|
|
T1 |
62 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
689 |
1 |
|
|
T1 |
6 |
|
T40 |
4 |
|
T83 |
8 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36862 |
1 |
|
|
T2 |
26 |
|
T10 |
99 |
|
T11 |
82 |
auto[0] |
auto[1] |
1379 |
1 |
|
|
T3 |
8 |
|
T21 |
4 |
|
T213 |
13 |
auto[1] |
auto[0] |
15941 |
1 |
|
|
T1 |
68 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
996 |
1 |
|
|
T59 |
15 |
|
T44 |
4 |
|
T181 |
16 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37051 |
1 |
|
|
T2 |
26 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1190 |
1 |
|
|
T17 |
4 |
|
T18 |
11 |
|
T41 |
10 |
auto[1] |
auto[0] |
16246 |
1 |
|
|
T1 |
56 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
691 |
1 |
|
|
T1 |
12 |
|
T40 |
8 |
|
T83 |
4 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33323 |
1 |
|
|
T2 |
26 |
|
T3 |
8 |
|
T11 |
82 |
auto[0] |
auto[1] |
4918 |
1 |
|
|
T10 |
99 |
|
T16 |
57 |
|
T22 |
73 |
auto[1] |
auto[0] |
16216 |
1 |
|
|
T1 |
61 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
721 |
1 |
|
|
T1 |
7 |
|
T40 |
11 |
|
T83 |
6 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37154 |
1 |
|
|
T2 |
25 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1087 |
1 |
|
|
T2 |
1 |
|
T15 |
8 |
|
T25 |
2 |
auto[1] |
auto[0] |
16030 |
1 |
|
|
T1 |
68 |
|
T2 |
151 |
|
T4 |
13 |
auto[1] |
auto[1] |
907 |
1 |
|
|
T2 |
22 |
|
T23 |
14 |
|
T21 |
11 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37094 |
1 |
|
|
T2 |
25 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1147 |
1 |
|
|
T2 |
1 |
|
T15 |
12 |
|
T23 |
1 |
auto[1] |
auto[0] |
16040 |
1 |
|
|
T1 |
68 |
|
T2 |
153 |
|
T4 |
13 |
auto[1] |
auto[1] |
897 |
1 |
|
|
T2 |
20 |
|
T23 |
9 |
|
T21 |
12 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37206 |
1 |
|
|
T2 |
25 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1035 |
1 |
|
|
T2 |
1 |
|
T15 |
8 |
|
T25 |
2 |
auto[1] |
auto[0] |
16064 |
1 |
|
|
T1 |
68 |
|
T2 |
162 |
|
T4 |
13 |
auto[1] |
auto[1] |
873 |
1 |
|
|
T2 |
11 |
|
T23 |
10 |
|
T21 |
15 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37143 |
1 |
|
|
T2 |
25 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1098 |
1 |
|
|
T2 |
1 |
|
T15 |
5 |
|
T25 |
1 |
auto[1] |
auto[0] |
16080 |
1 |
|
|
T1 |
68 |
|
T2 |
153 |
|
T4 |
13 |
auto[1] |
auto[1] |
857 |
1 |
|
|
T2 |
20 |
|
T23 |
7 |
|
T21 |
16 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37158 |
1 |
|
|
T2 |
24 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1083 |
1 |
|
|
T2 |
2 |
|
T15 |
10 |
|
T25 |
1 |
auto[1] |
auto[0] |
16055 |
1 |
|
|
T1 |
68 |
|
T2 |
154 |
|
T4 |
13 |
auto[1] |
auto[1] |
882 |
1 |
|
|
T2 |
19 |
|
T23 |
8 |
|
T21 |
13 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37135 |
1 |
|
|
T2 |
25 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1106 |
1 |
|
|
T2 |
1 |
|
T15 |
5 |
|
T25 |
1 |
auto[1] |
auto[0] |
16128 |
1 |
|
|
T1 |
68 |
|
T2 |
149 |
|
T4 |
13 |
auto[1] |
auto[1] |
809 |
1 |
|
|
T2 |
24 |
|
T23 |
9 |
|
T21 |
8 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37081 |
1 |
|
|
T2 |
26 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1160 |
1 |
|
|
T17 |
5 |
|
T18 |
11 |
|
T41 |
6 |
auto[1] |
auto[0] |
16240 |
1 |
|
|
T1 |
60 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
697 |
1 |
|
|
T1 |
8 |
|
T40 |
6 |
|
T83 |
10 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37084 |
1 |
|
|
T2 |
26 |
|
T3 |
8 |
|
T10 |
99 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T17 |
7 |
|
T18 |
13 |
|
T41 |
3 |
auto[1] |
auto[0] |
16190 |
1 |
|
|
T1 |
61 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
747 |
1 |
|
|
T1 |
7 |
|
T40 |
9 |
|
T83 |
5 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36796 |
1 |
|
|
T3 |
8 |
|
T10 |
99 |
|
T11 |
82 |
auto[0] |
auto[1] |
1445 |
1 |
|
|
T2 |
26 |
|
T25 |
14 |
|
T23 |
10 |
auto[1] |
auto[0] |
15630 |
1 |
|
|
T1 |
68 |
|
T2 |
173 |
|
T4 |
13 |
auto[1] |
auto[1] |
1307 |
1 |
|
|
T84 |
14 |
|
T214 |
10 |
|
T215 |
11 |